From 04d80dbe858d801efbecf3e5172b31b0a3757308 Mon Sep 17 00:00:00 2001 From: Heyi Guo Date: Tue, 25 Feb 2020 17:00:23 +0800 Subject: [PATCH] irqchip/gic-v3-its: Fix access width for gicr_syncr GICR_SYNCR is a 32bit register, so it is better to access it with 32bit access width, though we have not seen any real problem. Signed-off-by: Heyi Guo Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20200225090023.28020-1-guoheyi@huawei.com --- drivers/irqchip/irq-gic-v3-its.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 83b1186..6bb2bea 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set) static void wait_for_syncr(void __iomem *rdbase) { - while (gic_read_lpir(rdbase + GICR_SYNCR) & 1) + while (readl_relaxed(rdbase + GICR_SYNCR) & 1) cpu_relax(); } -- 2.7.4