From 04ac5b95df838a19592df6405a56b58c0e1c7ee0 Mon Sep 17 00:00:00 2001 From: Richard Kenner Date: Sun, 26 Nov 1995 14:13:47 -0500 Subject: [PATCH] (pattern for HImode PSHM): Corrected. (trunchiqi2, zero_extendqihi2, extendhftqf2): Corrected. (pattern for movhi of CONST_INT to REG): Corrected. (divmodqi pattern for DISN): Corrected. (all shift patterns): Corrected. From-SVN: r10594 --- gcc/config/1750a/1750a.md | 207 ++++++++++++++++++++++++++++++---------------- 1 file changed, 134 insertions(+), 73 deletions(-) diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md index 62332dc..e2d4f26 100644 --- a/gcc/config/1750a/1750a.md +++ b/gcc/config/1750a/1750a.md @@ -55,7 +55,7 @@ [(set (match_operand:QI 0 "push_operand" "=<") (match_operand:QI 1 "general_operand" "r"))] "" - "pshm r%1,r%1") + "pshm r%1,r%1 ; stackptr = R%0") (define_insn "" [(set (match_operand:HI 0 "push_operand" "=<") @@ -63,9 +63,12 @@ "" "* { - rtx new_operands[2]; + rtx new_operands[3]; + new_operands[2] = operands[0]; new_operands[0] = operands[1]; new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1); + output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands); + return \";\"; } ") (define_insn "" @@ -74,11 +77,12 @@ "" "* { - rtx new_operands[2]; + rtx new_operands[3]; + new_operands[2] = operands[0]; new_operands[0] = operands[1]; new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+1); - output_asm_insn(\"pshm r%0,r%1\",new_operands); - return \"\;\"; + output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands); + return \";\"; } ") (define_insn "" @@ -87,11 +91,12 @@ "" "* { - rtx new_operands[2]; + rtx new_operands[3]; + new_operands[2] = operands[0]; new_operands[0] = operands[1]; new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[1])+2); - output_asm_insn(\"pshm r%0,r%1\",new_operands); - return \"\;\"; + output_asm_insn(\"pshm r%0,r%1 ; stackptr = r%2\",new_operands); + return \";\"; } ") ;; stackpop @@ -111,7 +116,7 @@ new_operands[0] = operands[0]; new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1); output_asm_insn(\"popm r%0,r%1\",new_operands); - return \"\;\"; + return \";\"; } ") (define_insn "" @@ -124,7 +129,7 @@ new_operands[0] = operands[0]; new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+1); output_asm_insn(\"popm r%0,r%1\",new_operands); - return \"\;\"; + return \";\"; } ") (define_insn "" @@ -137,7 +142,7 @@ new_operands[0] = operands[0]; new_operands[1] = gen_rtx(CONST_INT,VOIDmode,REGNO(operands[0])+2); output_asm_insn(\"popm r%0,r%1\",new_operands); - return \"\;\"; + return \";\"; } ") ;; Test operations. These shouldn't really occur for 1750: @@ -262,8 +267,11 @@ "" "* { - REGNO(operands[1]) += 1; - return \"lr r%0,r%1 ;trunchiqi2\"; + rtx new_operands[2]; + new_operands[0] = operands[0]; + new_operands[1] = gen_rtx (REG, HImode, REGNO(operands[1]) + 1); + output_asm_insn(\"lr r%0,r%1 ;trunchiqi2\",new_operands); + return \";\"; } ") ;; zero extension instructions @@ -274,17 +282,23 @@ "" "* { + rtx new_opnds[2]; output_asm_insn(\"xorr r%0,r%0 ;zero_extendqihi2\",operands); - REGNO(operands[0]) += 1; + new_opnds[0] = gen_rtx (REG, HImode, REGNO(operands[0]) + 1); + new_opnds[1] = operands[1]; switch (which_alternative) { case 0: - return \"lr r%0,r%1\"; + output_asm_insn(\"lr r%0,r%1\",new_opnds); + break; case 1: - return \"l r%0,%1\"; + output_asm_insn(\"l r%0,%1\",new_opnds); + break; case 2: - return \"lim r%0,%1\"; + output_asm_insn(\"lim r%0,%1\",new_opnds); + break; } + return \";\"; } ") ;; sign extension instructions @@ -304,18 +318,18 @@ ; 1750 HF-to-TQF extend: just append 16 bits (least signif.) with all bits zero (define_insn "extendhftqf2" [(set (match_operand:TQF 0 "register_operand" "=r,r") - (float_extend:TQF - (match_operand:HF 1 "general_operand" "r,m")))] + (float_extend:TQF (match_operand:HF 1 "general_operand" "r,m")))] "" "* { - REGNO(operands[0]) += 2; - output_asm_insn(\"xorr r%0,r%0 ;extendhftqf2\",operands); - REGNO(operands[0]) -= 2; + rtx new_opnds[2]; + new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 2); + new_opnds[1] = operands[1]; + output_asm_insn(\"xorr r%0,r%0 ;extendhftqf2\",new_opnds); if (which_alternative == 0) - return \"dlr r%0,r%1\"; + return \"dlr r%0,r%1 ; put condition codes back on track\"; else - return \"dl r%0,%1\"; + return \"dl r%0,%1 ; put condition codes back on track\"; } ") ; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits @@ -386,38 +400,42 @@ ;; 32-bit moves -;; Set HIreg to constant +; Set HIreg to constant (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") - (match_operand 1 "immediate_operand" "i"))] + (match_operand:HI 1 "immediate_operand" "i"))] "" "* - if (GET_CODE(operands[1]) == CONST_INT) { + rtx new_opnds[2]; int val = INTVAL(operands[1]); if (val >= 0) { if (val <= 65535) { - output_asm_insn(\"xorr r%0,r%0 ;movhi cst->reg\",operands); - operands[0] = gen_rtx(REG,QImode,REGNO(operands[0]) + 1); + new_opnds[0] = gen_rtx(REG,QImode,REGNO(operands[0])); + new_opnds[1] = operands[1]; + output_asm_insn(\"xorr r%0,r%0 ;movhi cst->reg\",new_opnds); + REGNO(new_opnds[0]) += 1; if (val == 0) - return \"xorr r%0,r%0\"; + output_asm_insn(\"xorr r%0,r%0\",new_opnds); else if (val <= 16) - return \"lisp r%0,%1\"; + output_asm_insn(\"lisp r%0,%1\",new_opnds); else - return \"lim r%0,%1\"; + output_asm_insn(\"lim r%0,%1\",new_opnds); + return \";\"; } } else if (val >= -16) return \"lisn r%0,%J1\;dsra r%0,16 ;movhi cst\"; - INTVAL(operands[1]) >>= 16; - output_asm_insn(\"lim r%0,%1 ;movhi cst->reg\",operands); - REGNO(operands[0]) += 1; - INTVAL(operands[1]) = val & 0xFFFF; - return \"lim r%0,%1\"; + new_opnds[0] = gen_rtx(REG, QImode, REGNO(operands[0])); + new_opnds[1] = gen_rtx(CONST_INT,VOIDmode,(INTVAL(operands[1])) >> 16); + output_asm_insn(\"lim r%0,%1 ;movhi cst->reg\",new_opnds); + INTVAL(new_opnds[1]) = val & 0xFFFF; + REGNO(new_opnds[0]) += 1; + output_asm_insn(\"lim r%0,%1\",new_opnds); + return \";\"; } - return \"lim r%0,%1\;dsra r%0,16 ;movhi cst\"; ") (define_insn "movhi" @@ -671,8 +689,15 @@ istr = \"disp\"; break; case 1: - INTVAL(operands[2]) = - INTVAL(operands[2]); /* to be corrected */ - istr = \"disn\"; + { + rtx new_opnds[4]; + new_opnds[0] = operands[0]; + new_opnds[1] = operands[1]; + new_opnds[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL(operands[2])); + new_opnds[3] = operands[3]; + istr = \"disn\"; + return (char *)mod_regno_adjust(istr,new_opnds); + } break; case 2: istr = \"dvim\"; @@ -880,7 +905,7 @@ (define_insn "ashlqi3" [(set (match_operand:QI 0 "register_operand" "=r,r") (ashift:QI (match_operand:QI 1 "register_operand" "0,0") - (match_operand:QI 2 "general_operand" "I,r")))] + (match_operand:QI 2 "nonmemory_operand" "I,r")))] "" "@ sll r%0,%2 @@ -889,11 +914,24 @@ (define_insn "ashlhi3" [(set (match_operand:HI 0 "register_operand" "=r,r") (ashift:HI (match_operand:HI 1 "register_operand" "0,0") - (match_operand:QI 2 "general_operand" "L,r")))] + (match_operand:QI 2 "nonmemory_operand" "L,r")))] "" ; the 'L' constraint is a slight imprecise... - "@ - dsll r%0,%2 - dslr r%0,r%2 ") + "* + if (which_alternative == 1) + return \"dslr r%0,r%2\"; + else if (INTVAL(operands[2]) <= 16) + return \"dsll r%0,%2\"; + else + { + rtx new_opnds[2]; + new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0])); + new_opnds[1] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1); + output_asm_insn(\"lr r%0,r%1 ; ashlhi3 shiftcount > 16\",new_opnds); + new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL(operands[2]) - 16); + output_asm_insn(\"sll r%0,%1\",new_opnds); + return \";\"; + } ") + ;; Right shift by a variable shiftcount works by negating the shift count, ;; then emitting a right shift with the shift count negated. This means @@ -901,9 +939,9 @@ ;; prevents converting shifts to ZERO_EXTRACTs with negative positions, ;; which isn't valid. (define_expand "lshrqi3" - [(set (match_operand:QI 0 "general_operand" "=g") + [(set (match_operand:QI 0 "general_operand" "=r") (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") - (match_operand:QI 2 "general_operand" "g")))] + (match_operand:QI 2 "nonmemory_operand" "g")))] "" " { @@ -916,7 +954,7 @@ (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "immediate_operand" "I")))] "" - "srl r%0,%1") + "srl r%0,%2") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") @@ -926,23 +964,35 @@ "slr r%0,r%2 ") ;; Same thing for HImode. + (define_expand "lshrhi3" - [(set (match_operand:HI 0 "general_operand" "=g") - (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") - (match_operand:QI 2 "general_operand" "g")))] + [(set (match_operand:HI 0 "register_operand" "=r") + (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "g")))] "" " -{ - if (GET_CODE (operands[2]) != CONST_INT) - operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); -}") + { + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); + }") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") (match_operand:QI 2 "immediate_operand" "L")))] "" - "dsrl r%0,%1") + "* + { + rtx new_opnds[2]; + int amount = INTVAL(operands[2]); + if (amount <= 16) + return \"dsrl r%0,%2\"; + output_asm_insn(\"dsrl r%0,16 ; lshrhi3 shiftcount > 16\",operands); + new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1); + new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16); + output_asm_insn(\"srl r%0,%1\",new_opnds); + return \";\"; + } ") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") @@ -953,22 +1003,22 @@ ;; Same applies for arithmetic shift right. (define_expand "ashrqi3" - [(set (match_operand:QI 0 "general_operand" "=g") + [(set (match_operand:QI 0 "general_operand" "=r") (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") - (match_operand:QI 2 "general_operand" "g")))] + (match_operand:QI 2 "nonmemory_operand" "g")))] "" " -{ - if (GET_CODE (operands[2]) != CONST_INT) - operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); -}") + { + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); + }") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") (match_operand:QI 2 "immediate_operand" "I")))] "" - "sra r%0,%1") + "sra r%0,%2") (define_insn "" [(set (match_operand:QI 0 "register_operand" "=r") @@ -979,22 +1029,33 @@ ;; HImode arithmetic shift right. (define_expand "ashrhi3" - [(set (match_operand:HI 0 "general_operand" "=g") + [(set (match_operand:HI 0 "general_operand" "=r") (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") - (match_operand:QI 2 "general_operand" "g")))] + (match_operand:QI 2 "nonmemory_operand" "g")))] "" " -{ - if (GET_CODE (operands[2]) != CONST_INT) - operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); -}") + { + if (GET_CODE (operands[2]) != CONST_INT) + operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2])); + }") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") (match_operand:QI 2 "immediate_operand" "L")))] "" - "dsra r%0,%1") + "* + { + rtx new_opnds[2]; + int amount = INTVAL(operands[2]); + if (amount <= 16) + return \"dsra r%0,%2\"; + output_asm_insn(\"dsra r%0,16 ; ashrhi3 shiftcount > 16\",operands); + new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1); + new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, amount - 16); + output_asm_insn(\"sra r%0,%1\",new_opnds); + return \";\"; + } ") (define_insn "" [(set (match_operand:HI 0 "register_operand" "=r") @@ -1009,7 +1070,7 @@ (define_insn "rotlqi3" [(set (match_operand:QI 0 "register_operand" "=r,r") (rotate:QI (match_operand:QI 1 "register_operand" "0,0") - (match_operand:QI 2 "general_operand" "I,r")))] + (match_operand:QI 2 "nonmemory_operand" "I,r")))] "" "@ slc r%0,%2 @@ -1018,7 +1079,7 @@ (define_insn "rotlhi3" [(set (match_operand:HI 0 "register_operand" "=r,r") (rotate:HI (match_operand:HI 1 "register_operand" "0,0") - (match_operand:QI 2 "general_operand" "I,r")))] + (match_operand:QI 2 "nonmemory_operand" "I,r")))] "" "@ dslc r%0,%2 @@ -1034,7 +1095,7 @@ (define_insn "rotrhi3" [(set (match_operand:HI 0 "register_operand" "=r") (rotatert:HI (match_operand:HI 1 "register_operand" "0") - (match_operand:QI 2 "general_operand" "r")))] + (match_operand:QI 2 "nonmemory_operand" "r")))] "" "neg r%2,r%2\;dscr r%0,r%2 ") -- 2.7.4