From 04816e672d46a1aabb1a35d73ca5f90d6d252ca3 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Fri, 22 May 2020 15:02:26 +0530 Subject: [PATCH] mmc: sdhci-msm: Update dll_config_3 as per HSR Update dll_config_3 as per the host clock frequency as specified in the DLL Hardware Reference Guide. Signed-off-by: Sarthak Garg Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/1590139950-7288-5-git-send-email-sartgarg@codeaurora.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-msm.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 6588077..054b151 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -62,6 +62,9 @@ #define FINE_TUNE_MODE_EN BIT(27) #define BIAS_OK_SIGNAL BIT(29) +#define DLL_CONFIG_3_LOW_FREQ_VAL 0x08 +#define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10 + #define CORE_VENDOR_SPEC_POR_VAL 0xa9c #define CORE_CLK_PWRSAVE BIT(1) #define CORE_HC_MCLK_SEL_DFLT (2 << 8) @@ -695,6 +698,16 @@ static int msm_init_cm_dll(struct sdhci_host *host) ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL; writel_relaxed(config, host->ioaddr + msm_offset->core_dll_usr_ctl); + + config = readl_relaxed(host->ioaddr + + msm_offset->core_dll_config_3); + config &= ~0xFF; + if (msm_host->clk_rate < 150000000) + config |= DLL_CONFIG_3_LOW_FREQ_VAL; + else + config |= DLL_CONFIG_3_HIGH_FREQ_VAL; + writel_relaxed(config, host->ioaddr + + msm_offset->core_dll_config_3); } config = readl_relaxed(host->ioaddr + -- 2.7.4