From 043e4787211609e987799050ba2944b77a53ddb5 Mon Sep 17 00:00:00 2001 From: Victor Huang Date: Wed, 5 Feb 2020 13:47:54 -0600 Subject: [PATCH] [PowerPC][NFC] Clang-format on commit 4b414d --- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 7 ++++--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp | 4 ++-- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 5 ++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 343c0eb..ed98852 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -356,9 +356,10 @@ public: bool isS16ImmX16() const { return Kind == Expression || (Kind == Immediate && isInt<16>(getImm()) && (getImm() & 15) == 0); } - bool isS34ImmX16() const { return Kind == Expression || - (Kind == Immediate && isInt<34>(getImm()) && - (getImm() & 15) == 0); } + bool isS34ImmX16() const { + return Kind == Expression || + (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); + } bool isS34Imm() const { // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit // ContextImmediate is needed. diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index 9113592..2ff3f5d 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -469,7 +469,7 @@ void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, raw_ostream &O) { printS34ImmOperand(MI, OpNo, O); O << '('; - printImmZeroOperand(MI, OpNo+1, O); + printImmZeroOperand(MI, OpNo + 1, O); O << ')'; } @@ -477,7 +477,7 @@ void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo, raw_ostream &O) { printS34ImmOperand(MI, OpNo, O); O << '('; - printOperand(MI, OpNo+1, O); + printOperand(MI, OpNo + 1, O); O << ')'; } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 86c93ab..672f6e0 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -183,9 +183,8 @@ PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo, // Encode (imm, reg) as a memri34, which has the low 34-bits as the // displacement and the next 5 bits as the register #. assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register."); - uint64_t RegBits = - getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34; - + uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) + << 34; const MCOperand &MO = MI.getOperand(OpNo); return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits; } -- 2.7.4