From 03ff435da540b0feb8272784e05ce742831d5bc2 Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Sun, 5 Feb 2023 18:29:55 -0800 Subject: [PATCH] [RISCV] Default to -ffixed-x18 for Fuchsia Fuchsia's ABI always reserves the x18 (s2) register for the ShadowCallStack ABI, even when -fsanitize=shadow-call-stack is not enabled. Reviewed By: phosek Differential Revision: https://reviews.llvm.org/D143355 --- clang/lib/Driver/SanitizerArgs.cpp | 4 +++- clang/test/Driver/sanitizer-ld.c | 5 +++++ llvm/include/llvm/TargetParser/RISCVTargetParser.h | 5 +++++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 3 +++ llvm/lib/TargetParser/RISCVTargetParser.cpp | 6 ++++++ llvm/test/CodeGen/RISCV/reserved-regs.ll | 2 ++ 6 files changed, 24 insertions(+), 1 deletion(-) diff --git a/clang/lib/Driver/SanitizerArgs.cpp b/clang/lib/Driver/SanitizerArgs.cpp index 84be06b..49ae5cc 100644 --- a/clang/lib/Driver/SanitizerArgs.cpp +++ b/clang/lib/Driver/SanitizerArgs.cpp @@ -19,6 +19,7 @@ #include "llvm/Support/TargetParser.h" #include "llvm/Support/VirtualFileSystem.h" #include "llvm/TargetParser/AArch64TargetParser.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #include "llvm/Transforms/Instrumentation/AddressSanitizerOptions.h" #include @@ -545,7 +546,8 @@ SanitizerArgs::SanitizerArgs(const ToolChain &TC, if ((Kinds & SanitizerKind::ShadowCallStack) && ((TC.getTriple().isAArch64() && !llvm::AArch64::isX18ReservedByDefault(TC.getTriple())) || - TC.getTriple().isRISCV()) && + (TC.getTriple().isRISCV() && + !llvm::RISCV::isX18ReservedByDefault(TC.getTriple()))) && !Args.hasArg(options::OPT_ffixed_x18) && DiagnoseErrors) { D.Diag(diag::err_drv_argument_only_allowed_with) << lastArgumentForMask(D, Args, Kinds & SanitizerKind::ShadowCallStack) diff --git a/clang/test/Driver/sanitizer-ld.c b/clang/test/Driver/sanitizer-ld.c index 3621d12..0ba209d 100644 --- a/clang/test/Driver/sanitizer-ld.c +++ b/clang/test/Driver/sanitizer-ld.c @@ -732,6 +732,11 @@ // CHECK-SHADOWCALLSTACK-LINUX-RISCV64: '-fsanitize=shadow-call-stack' only allowed with '-ffixed-x18' // RUN: %clang -fsanitize=shadow-call-stack -### %s 2>&1 \ +// RUN: --target=riscv64-unknown-fuchsia -fuse-ld=ld \ +// RUN: | FileCheck --check-prefix=CHECK-SHADOWCALLSTACK-FUCHSIA-RISCV64 %s +// CHECK-SHADOWCALLSTACK-FUCHSIA-RISCV64-NOT: error: + +// RUN: %clang -fsanitize=shadow-call-stack -### %s 2>&1 \ // RUN: --target=aarch64-unknown-linux -fuse-ld=ld -ffixed-x18 \ // RUN: | FileCheck --check-prefix=CHECK-SHADOWCALLSTACK-LINUX-AARCH64-X18 %s // RUN: %clang -fsanitize=shadow-call-stack -### %s 2>&1 \ diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h index da2ecd8..f50576b 100644 --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -18,6 +18,9 @@ #include namespace llvm { + +class Triple; + namespace RISCV { // We use 64 bits as the known part in the scalable vector types. @@ -38,6 +41,8 @@ void fillValidCPUArchList(SmallVectorImpl &Values, bool IsRV64); void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64); bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector &Features); +bool isX18ReservedByDefault(const Triple &TT); + } // namespace RISCV } // namespace llvm diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp index 2d134b2..1101d7e 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -83,6 +83,9 @@ RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, FrameLowering( initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) { + if (RISCV::isX18ReservedByDefault(TT)) + UserReservedRegister.set(RISCV::X18); + CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering())); Legalizer.reset(new RISCVLegalizerInfo(*this)); diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index 89cd5c0..933a82b 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -14,6 +14,7 @@ #include "llvm/TargetParser/RISCVTargetParser.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringSwitch.h" +#include "llvm/TargetParser/Triple.h" namespace llvm { namespace RISCV { @@ -100,5 +101,10 @@ bool getCPUFeaturesExceptStdExt(CPUKind Kind, return true; } +bool isX18ReservedByDefault(const Triple &TT) { + // X18 is reserved for the ShadowCallStack ABI (even when not enabled). + return TT.isOSFuchsia(); +} + } // namespace RISCV } // namespace llvm diff --git a/llvm/test/CodeGen/RISCV/reserved-regs.ll b/llvm/test/CodeGen/RISCV/reserved-regs.ll index 045ffab..da549c0 100644 --- a/llvm/test/CodeGen/RISCV/reserved-regs.ll +++ b/llvm/test/CodeGen/RISCV/reserved-regs.ll @@ -57,6 +57,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31 ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31 +; RUN: llc -mtriple=riscv64-fuchsia -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18 + ; This program is free to use all registers, but needs a stack pointer for ; spill values, so do not test for reserving the stack pointer. -- 2.7.4