From 03fc4f2e9a66cc316937fc6326fdd9cd51d397d2 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 4 Dec 2020 18:36:14 -0800 Subject: [PATCH] [RISCV] Use fcvt.h/d/f.w if the input is an assertsexti32 not just when the input is sext_inreg. --- llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td | 2 +- llvm/test/CodeGen/RISCV/rv64d-double-convert.ll | 2 +- llvm/test/CodeGen/RISCV/rv64f-float-convert.ll | 2 +- llvm/test/CodeGen/RISCV/rv64f-half-convert.ll | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td index b7d8708..182c399 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -373,7 +373,7 @@ def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR64:$rs1)), i32), (FCVT_WU_D $rs1, 0b001)>; // [u]int32->fp -def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_D_W $rs1)>; +def : Pat<(sint_to_fp (sexti32 GPR:$rs1)), (FCVT_D_W $rs1)>; def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_D_WU $rs1)>; def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_L_D FPR64:$rs1, 0b001)>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index c21bb30..7a069da 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -417,7 +417,7 @@ def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_L_S $rs1, 0b001)>; def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_LU_S $rs1, 0b001)>; // [u]int->fp. Match GCC and default to using dynamic rounding mode. -def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_S_W $rs1, 0b111)>; +def : Pat<(sint_to_fp (sexti32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>; def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>; def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>; def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td index f142b65..3a94de0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td @@ -374,7 +374,7 @@ def : Pat<(fp_to_sint FPR16:$rs1), (FCVT_L_H $rs1, 0b001)>; def : Pat<(fp_to_uint FPR16:$rs1), (FCVT_LU_H $rs1, 0b001)>; // [u]int->fp. Match GCC and default to using dynamic rounding mode. -def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_H_W $rs1, 0b111)>; +def : Pat<(sint_to_fp (sexti32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>; def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>; def : Pat<(sint_to_fp GPR:$rs1), (FCVT_H_L $rs1, 0b111)>; def : Pat<(uint_to_fp GPR:$rs1), (FCVT_H_LU $rs1, 0b111)>; diff --git a/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll b/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll index da3fcf6..210f882 100644 --- a/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll +++ b/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll @@ -112,7 +112,7 @@ define double @sitofp_aext_i32_to_f64(i32 %a) nounwind { define double @sitofp_sext_i32_to_f64(i32 signext %a) nounwind { ; RV64ID-LABEL: sitofp_sext_i32_to_f64: ; RV64ID: # %bb.0: -; RV64ID-NEXT: fcvt.d.l ft0, a0 +; RV64ID-NEXT: fcvt.d.w ft0, a0 ; RV64ID-NEXT: fmv.x.d a0, ft0 ; RV64ID-NEXT: ret %1 = sitofp i32 %a to double diff --git a/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll b/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll index 13e4724..b3eafb1 100644 --- a/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll +++ b/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll @@ -169,7 +169,7 @@ define float @sitofp_aext_i32_to_f32(i32 %a) nounwind { define float @sitofp_sext_i32_to_f32(i32 signext %a) nounwind { ; RV64IF-LABEL: sitofp_sext_i32_to_f32: ; RV64IF: # %bb.0: -; RV64IF-NEXT: fcvt.s.l ft0, a0 +; RV64IF-NEXT: fcvt.s.w ft0, a0 ; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: ret %1 = sitofp i32 %a to float diff --git a/llvm/test/CodeGen/RISCV/rv64f-half-convert.ll b/llvm/test/CodeGen/RISCV/rv64f-half-convert.ll index 28b8ad5..620d24f 100644 --- a/llvm/test/CodeGen/RISCV/rv64f-half-convert.ll +++ b/llvm/test/CodeGen/RISCV/rv64f-half-convert.ll @@ -155,7 +155,7 @@ define half @sitofp_aext_i32_to_f16(i32 %a) nounwind { define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind { ; RV64IZFH-LABEL: sitofp_sext_i32_to_f16: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: fcvt.h.l fa0, a0 +; RV64IZFH-NEXT: fcvt.h.w fa0, a0 ; RV64IZFH-NEXT: ret %1 = sitofp i32 %a to half ret half %1 -- 2.7.4