From 03bca4a8c1f25d743a6f0bc7dfe49028faedf2a6 Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Fri, 14 May 2021 08:37:04 -0700 Subject: [PATCH] drm/i915/adl_p: Enable/disable loadgen sharing Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz. For all other modes, we can enable loadgen sharing feature. BSpec: 55359 Cc: Imre Deak Signed-off-by: Mika Kahola Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-13-matthew.d.roper@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index b0ea081..eccbdd4 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1459,6 +1459,14 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); val &= ~DKL_TX_DP20BITMODE; intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); + + if ((intel_crtc_has_dp_encoder(crtc_state) && + crtc_state->port_clock == 162000) || + (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && + crtc_state->port_clock == 594000)) + val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE; + else + val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE; } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c01de83..1ec0f0a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10825,6 +10825,7 @@ enum skl_power_gate { _DKL_TX_DPCNTL1) #define _DKL_TX_DPCNTL2 0x2C8 +#define DKL_TX_LOADGEN_SHARING_PMD_DISABLE REG_BIT(12) #define DKL_TX_DP20BITMODE (1 << 2) #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ _DKL_PHY1_BASE, \ -- 2.7.4