From 03a8d2f8ecdbfd531d712e4b0ca0b66c091405db Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Mon, 29 Feb 2016 16:06:38 +0000 Subject: [PATCH] [mips] Range check uimm20 and fixed a bug this revealed. Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231 --- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 3 ++ .../Target/Mips/InstPrinter/MipsInstPrinter.cpp | 27 +++++----- llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h | 4 +- llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 4 +- llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 18 ------- llvm/lib/Target/Mips/MipsAsmPrinter.h | 2 - llvm/lib/Target/Mips/MipsInstrInfo.td | 57 +++++++++++----------- llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 18 +++---- .../MC/Disassembler/Mips/micromips64r6/valid.txt | 6 +-- llvm/test/MC/Mips/micromips/invalid-wrong-error.s | 12 +++++ llvm/test/MC/Mips/mips-control-instructions.s | 6 --- llvm/test/MC/Mips/mips1/valid.s | 2 + llvm/test/MC/Mips/mips2/valid.s | 2 + llvm/test/MC/Mips/mips3/valid.s | 2 + llvm/test/MC/Mips/mips32/valid.s | 2 + llvm/test/MC/Mips/mips32r2/invalid.s | 4 ++ llvm/test/MC/Mips/mips32r2/valid.s | 2 + llvm/test/MC/Mips/mips32r3/valid.s | 2 + llvm/test/MC/Mips/mips32r5/valid.s | 2 + llvm/test/MC/Mips/mips32r6/valid.s | 2 + llvm/test/MC/Mips/mips4/valid.s | 2 + llvm/test/MC/Mips/mips5/valid.s | 2 + llvm/test/MC/Mips/mips64/valid.s | 2 + llvm/test/MC/Mips/mips64extins.ll | 6 +-- llvm/test/MC/Mips/mips64r2/valid.s | 2 + llvm/test/MC/Mips/mips64r3/valid.s | 2 + llvm/test/MC/Mips/mips64r5/valid.s | 2 + llvm/test/MC/Mips/mips64r6/valid.s | 2 + 28 files changed, 109 insertions(+), 88 deletions(-) create mode 100644 llvm/test/MC/Mips/micromips/invalid-wrong-error.s diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index b848a68..22ed0d1 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3776,6 +3776,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_UImm16_Relaxed: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 16-bit unsigned immediate"); + case Match_UImm20_0: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 20-bit unsigned immediate"); } llvm_unreachable("Implement any new match types added!"); diff --git a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp index a7b7d2e..f2ef0b2 100644 --- a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -203,22 +203,19 @@ void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, printExpr(Op.getExpr(), &MAI, O); } -void MipsInstPrinter::printUnsignedImm(const MCInst *MI, int opNum, - raw_ostream &O) { +template +void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) { const MCOperand &MO = MI->getOperand(opNum); - if (MO.isImm()) - O << (unsigned short int)MO.getImm(); - else - printOperand(MI, opNum, O); -} + if (MO.isImm()) { + uint64_t Imm = MO.getImm(); + Imm -= Offset; + Imm &= (1 << Bits) - 1; + Imm += Offset; + O << Imm; + return; + } -void MipsInstPrinter::printUnsignedImm8(const MCInst *MI, int opNum, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(opNum); - if (MO.isImm()) - O << (unsigned short int)(unsigned char)MO.getImm(); - else - printOperand(MI, opNum, O); + printOperand(MI, opNum, O); } void MipsInstPrinter:: @@ -343,7 +340,7 @@ void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) { if (MI->getOperand(i).isReg()) printRegName(O, MI->getOperand(i).getReg()); else - printUnsignedImm(MI, i, O); + printUImm<16>(MI, i, O); } } diff --git a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h index 0e61ea6..4a76b5a 100644 --- a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h +++ b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h @@ -93,8 +93,8 @@ public: private: void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O); - void printUnsignedImm8(const MCInst *MI, int opNum, raw_ostream &O); + template + void printUImm(const MCInst *MI, int opNum, raw_ostream &O); void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O); void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O); diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 6c0de02..0519bf4 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -891,7 +891,7 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Control Instructions def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; - def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM; + def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10>, SYS_FM_MM; def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM; def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>; def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>; @@ -944,7 +944,7 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>; def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>; - def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM; + def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10>, SDBBP_FM_MM; def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>; } diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 9575293..cfb9e5c 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -620,24 +620,6 @@ void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, if (closeP) O << ")"; } -void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum, - raw_ostream &O) { - const MachineOperand &MO = MI->getOperand(opNum); - if (MO.isImm()) - O << (unsigned short int)MO.getImm(); - else - printOperand(MI, opNum, O); -} - -void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum, - raw_ostream &O) { - const MachineOperand &MO = MI->getOperand(opNum); - if (MO.isImm()) - O << (unsigned short int)(unsigned char)MO.getImm(); - else - printOperand(MI, opNum, O); -} - void MipsAsmPrinter:: printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { // Load/Store memory operands -- imm($reg) diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h index a7f3304..f30141f 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.h +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -134,8 +134,6 @@ public: unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override; void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); - void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); - void printUnsignedImm8(const MachineInstr *MI, int opNum, raw_ostream &O); void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O); void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index ea4fa50..a6949fa 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -422,8 +422,10 @@ class UImmAsmOperandClass Supers = []> let DiagnosticType = "UImm" # Bits; } +def ConstantUImm20AsmOperandClass + : ConstantUImmAsmOperandClass<20, []>; def UImm16RelaxedAsmOperandClass - : UImmAsmOperandClass<16, []> { + : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> { let Name = "UImm16_Relaxed"; let PredicateMethod = "isAnyImm<16>"; let DiagnosticType = "UImm16_Relaxed"; @@ -541,70 +543,67 @@ def simm18_lsl3 : Operand { def simm20 : Operand; def simm32 : Operand; -def uimm20 : Operand { -} - def simm16_64 : Operand { let DecoderMethod = "DecodeSimm16"; } // Zero def uimmz : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<0>"; let ParserMatchClass = ConstantImmzAsmOperandClass; } // size operand of ins instruction def uimm_range_2_64 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<6, 2>"; let EncoderMethod = "getSizeInsEncoding"; let DecoderMethod = "DecodeInsSize"; let ParserMatchClass = ConstantUImm5_Range2_64AsmOperandClass; } // Unsigned Operands -foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10} in +foreach I = {1, 2, 3, 4, 5, 6, 7, 8, 10, 20} in def uimm # I : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<" # I # ">"; let ParserMatchClass = !cast("ConstantUImm" # I # "AsmOperandClass"); } def uimm2_plus1 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<2, 1>"; let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>"; let DecoderMethod = "DecodeUImmWithOffset<2, 1>"; let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass; } def uimm5_plus1 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<5, 1>"; let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass; } def uimm5_plus32 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<5, 32>"; let ParserMatchClass = ConstantUImm5Plus32AsmOperandClass; } def uimm5_plus33 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<5, 33>"; let EncoderMethod = "getUImmWithOffsetEncoding<5, 1>"; let DecoderMethod = "DecodeUImmWithOffset<5, 1>"; let ParserMatchClass = ConstantUImm5Plus33AsmOperandClass; } def uimm5_inssize_plus1 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<6>"; let ParserMatchClass = ConstantUImm5Plus1AsmOperandClass; let EncoderMethod = "getSizeInsEncoding"; let DecoderMethod = "DecodeInsSize"; } def uimm5_plus32_normalize : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<5>"; let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; } @@ -615,40 +614,40 @@ def uimm5_lsl2 : Operand { } def uimm5_plus32_normalize_64 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<5>"; let ParserMatchClass = ConstantUImm5Plus32NormalizeAsmOperandClass; } foreach I = {16} in def uimm # I : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<16>"; let ParserMatchClass = !cast("UImm" # I # "AsmOperandClass"); } // Like uimm16_64 but coerces simm16 to uimm16. def uimm16_relaxed : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<16>"; let ParserMatchClass = !cast("UImm16RelaxedAsmOperandClass"); } foreach I = {5} in def uimm # I # _64 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<5>"; let ParserMatchClass = !cast("ConstantUImm" # I # "AsmOperandClass"); } def uimm16_64 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<16>"; let ParserMatchClass = !cast("UImm16AsmOperandClass"); } // Like uimm16_64 but coerces simm16 to uimm16. def uimm16_64_relaxed : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<16>"; let ParserMatchClass = !cast("UImm16RelaxedAsmOperandClass"); } @@ -656,14 +655,14 @@ def uimm16_64_relaxed : Operand { // Like uimm5 but reports a less confusing error for 32-63 when // an instruction alias permits that. def uimm5_report_uimm6 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<5>"; let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; } // Like uimm5_64 but reports a less confusing error for 32-63 when // an instruction alias permits that. def uimm5_64_report_uimm6 : Operand { - let PrintMethod = "printUnsignedImm"; + let PrintMethod = "printUImm<5>"; let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass; } @@ -1135,8 +1134,8 @@ class BAL_BR_Pseudo : } // Syscall -class SYS_FT : - InstSE<(outs), (ins uimm20:$code_), +class SYS_FT : + InstSE<(outs), (ins ImmOp:$code_), !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>; // Break class BRK_FT : @@ -1332,11 +1331,11 @@ class SCBase : } class MFC3OP : - InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel), + InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel), !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; class MTC3OP : - InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel), + InstSE<(outs RO:$rd), (ins RD:$rt, uimm3:$sel), !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>; class TrapBase @@ -1571,10 +1570,12 @@ def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, let AdditionalPredicates = [NotInMicroMips] in { def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>; +def SYSCALL : MMRel, SYS_FT<"syscall", uimm20>, SYS_FM<0xc>; } -def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; def TRAP : TrapBase; -def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; +let AdditionalPredicates = [NotInMicroMips] in { +def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20>, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; +} let AdditionalPredicates = [NotInMicroMips] in { def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32; diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index eacfcec..5e4a21f 100644 --- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -71,41 +71,41 @@ def immZExt6Ptr : ImmLeaf(Imm);}]>; // Operands def uimm4_ptr : Operand { - let PrintMethod = "printUnsignedImm8"; + let PrintMethod = "printUImm<8>"; } def uimm6_ptr : Operand { - let PrintMethod = "printUnsignedImm8"; + let PrintMethod = "printUImm<8>"; } def simm5 : Operand; def vsplat_uimm1 : Operand { - let PrintMethod = "printUnsignedImm8"; + let PrintMethod = "printUImm<8>"; } def vsplat_uimm2 : Operand { - let PrintMethod = "printUnsignedImm8"; + let PrintMethod = "printUImm<8>"; } def vsplat_uimm3 : Operand { - let PrintMethod = "printUnsignedImm8"; + let PrintMethod = "printUImm<8>"; } def vsplat_uimm4 : Operand { - let PrintMethod = "printUnsignedImm8"; + let PrintMethod = "printUImm<8>"; } def vsplat_uimm5 : Operand { - let PrintMethod = "printUnsignedImm8"; + let PrintMethod = "printUImm<8>"; } def vsplat_uimm6 : Operand { - let PrintMethod = "printUnsignedImm8"; + let PrintMethod = "printUImm<8>"; } def vsplat_uimm8 : Operand { - let PrintMethod = "printUnsignedImm8"; + let PrintMethod = "printUImm<8>"; } def vsplat_simm5 : Operand; diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt index c3f9775..fb8284d 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -25,8 +25,8 @@ 0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4 0x42 0x03 0x00 0x04 # CHECK: dati $3, 4 0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7 -0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 7 -0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 3, 7 +0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39 +0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7 0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5 0x58 0x64 0x29 0x18 # CHECK: ddiv $3, $4, $5 0x58 0x64 0x29 0x58 # CHECK: dmod $3, $4, $5 @@ -171,6 +171,6 @@ 0x00 0x0f 0x47 0x7c # CHECK: di $15 0x00 0x00 0x43 0x7c # CHECK: tlbinv 0x00 0x00 0x53 0x7c # CHECK: tlbinvf -0x58 0x82 0x20 0x34 # CHECK: dinsu $4, $2, 0, 5 +0x58 0x82 0x20 0x34 # CHECK: dinsu $4, $2, 32, 5 0x58 0x82 0x38 0xc4 # CHECK: dinsm $4, $2, 3, 5 0x58 0x82 0x38 0xcc # CHECK: dins $4, $2, 3, 5 diff --git a/llvm/test/MC/Mips/micromips/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips/invalid-wrong-error.s new file mode 100644 index 0000000..36edaa6 --- /dev/null +++ b/llvm/test/MC/Mips/micromips/invalid-wrong-error.s @@ -0,0 +1,12 @@ +# Instructions that are correctly rejected but emit a wrong or misleading error. +# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1 +# RUN: FileCheck %s < %t1 + + # The 20-bit immediate supported by the standard encodings cause us to emit + # the diagnostic for the 20-bit form. This isn't exactly wrong but it is + # misleading. Ideally, we'd emit every way to achieve a valid match instead + # of picking only one. + sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate + sdbbp 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate + syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips-control-instructions.s b/llvm/test/MC/Mips/mips-control-instructions.s index 47da8cc..03b8ed2 100644 --- a/llvm/test/MC/Mips/mips-control-instructions.s +++ b/llvm/test/MC/Mips/mips-control-instructions.s @@ -6,8 +6,6 @@ # CHECK32: break # encoding: [0x00,0x00,0x00,0x0d] # CHECK32: break 7 # encoding: [0x00,0x07,0x00,0x0d] # CHECK32: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] -# CHECK32: syscall # encoding: [0x00,0x00,0x00,0x0c] -# CHECK32: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] # CHECK32: eret # encoding: [0x42,0x00,0x00,0x18] # CHECK32: deret # encoding: [0x42,0x00,0x00,0x1f] # CHECK32: di # encoding: [0x41,0x60,0x60,0x00] @@ -39,8 +37,6 @@ # CHECK64: break # encoding: [0x00,0x00,0x00,0x0d] # CHECK64: break 7 # encoding: [0x00,0x07,0x00,0x0d] # CHECK64: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] -# CHECK64: syscall # encoding: [0x00,0x00,0x00,0x0c] -# CHECK64: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] # CHECK64: eret # encoding: [0x42,0x00,0x00,0x18] # CHECK64: deret # encoding: [0x42,0x00,0x00,0x1f] # CHECK64: di # encoding: [0x41,0x60,0x60,0x00] @@ -72,8 +68,6 @@ break break 7 break 7,5 - syscall - syscall 0x3454 eret deret di diff --git a/llvm/test/MC/Mips/mips1/valid.s b/llvm/test/MC/Mips/mips1/valid.s index 2a4de30..702e399 100644 --- a/llvm/test/MC/Mips/mips1/valid.s +++ b/llvm/test/MC/Mips/mips1/valid.s @@ -117,6 +117,8 @@ a: swc3 $10,-32265($k0) swl $15,13694($s3) swr $s1,-26590($14) + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] diff --git a/llvm/test/MC/Mips/mips2/valid.s b/llvm/test/MC/Mips/mips2/valid.s index 700a691..a6a3b1c 100644 --- a/llvm/test/MC/Mips/mips2/valid.s +++ b/llvm/test/MC/Mips/mips2/valid.s @@ -146,6 +146,8 @@ a: swl $15,13694($s3) swr $s1,-26590($14) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips3/valid.s b/llvm/test/MC/Mips/mips3/valid.s index a8a3c04..56b0654a 100644 --- a/llvm/test/MC/Mips/mips3/valid.s +++ b/llvm/test/MC/Mips/mips3/valid.s @@ -210,6 +210,8 @@ a: swl $15,13694($s3) swr $s1,-26590($14) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips32/valid.s b/llvm/test/MC/Mips/mips32/valid.s index cddd9e8..6328e56 100644 --- a/llvm/test/MC/Mips/mips32/valid.s +++ b/llvm/test/MC/Mips/mips32/valid.s @@ -176,6 +176,8 @@ a: swr $s1,-26590($14) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips32r2/invalid.s b/llvm/test/MC/Mips/mips32r2/invalid.s index 9eb9fff..6254a9a 100644 --- a/llvm/test/MC/Mips/mips32r2/invalid.s +++ b/llvm/test/MC/Mips/mips32r2/invalid.s @@ -24,12 +24,16 @@ ori $2, $3, 65536 # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + sdbbp -1 # CHECK: :[[@LINE]]:15: error: expected 20-bit unsigned immediate + sdbbp 1048576 # CHECK: :[[@LINE]]:15: error: expected 20-bit unsigned immediate sll $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate sll $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate srl $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate srl $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate sra $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate sra $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate + syscall -1 # CHECK: :[[@LINE]]:17: error: expected 20-bit unsigned immediate + syscall 1048576 # CHECK: :[[@LINE]]:17: error: expected 20-bit unsigned immediate rotr $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate rotr $2, $3, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate xori $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate diff --git a/llvm/test/MC/Mips/mips32r2/valid.s b/llvm/test/MC/Mips/mips32r2/valid.s index 858da4a..70d5043 100644 --- a/llvm/test/MC/Mips/mips32r2/valid.s +++ b/llvm/test/MC/Mips/mips32r2/valid.s @@ -213,6 +213,8 @@ a: swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips32r3/valid.s b/llvm/test/MC/Mips/mips32r3/valid.s index 2aab512..9408c94 100644 --- a/llvm/test/MC/Mips/mips32r3/valid.s +++ b/llvm/test/MC/Mips/mips32r3/valid.s @@ -213,6 +213,8 @@ a: swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips32r5/valid.s b/llvm/test/MC/Mips/mips32r5/valid.s index 8948030..5fbdfc7 100644 --- a/llvm/test/MC/Mips/mips32r5/valid.s +++ b/llvm/test/MC/Mips/mips32r5/valid.s @@ -214,6 +214,8 @@ a: swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s index e4786d0..ad96a3f 100644 --- a/llvm/test/MC/Mips/mips32r6/valid.s +++ b/llvm/test/MC/Mips/mips32r6/valid.s @@ -177,6 +177,8 @@ a: sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s index 12b5ec8..625453d 100644 --- a/llvm/test/MC/Mips/mips4/valid.s +++ b/llvm/test/MC/Mips/mips4/valid.s @@ -239,6 +239,8 @@ a: swr $s1,-26590($14) swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips5/valid.s b/llvm/test/MC/Mips/mips5/valid.s index a3f3f05..272bef3 100644 --- a/llvm/test/MC/Mips/mips5/valid.s +++ b/llvm/test/MC/Mips/mips5/valid.s @@ -241,6 +241,8 @@ a: swr $s1,-26590($14) swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips64/valid.s b/llvm/test/MC/Mips/mips64/valid.s index f03ae7a..173945b 100644 --- a/llvm/test/MC/Mips/mips64/valid.s +++ b/llvm/test/MC/Mips/mips64/valid.s @@ -260,6 +260,8 @@ a: swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips64extins.ll b/llvm/test/MC/Mips/mips64extins.ll index 093bc87..4521bfb 100644 --- a/llvm/test/MC/Mips/mips64extins.ll +++ b/llvm/test/MC/Mips/mips64extins.ll @@ -12,7 +12,7 @@ entry: define i64 @dextu(i64 %i) nounwind readnone { entry: -; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 2, 6 +; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6 %shr = lshr i64 %i, 34 %and = and i64 %shr, 63 ret i64 %and @@ -20,7 +20,7 @@ entry: define i64 @dextm(i64 %i) nounwind readnone { entry: -; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 2 +; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34 %shr = lshr i64 %i, 5 %and = and i64 %shr, 17179869183 ret i64 %and @@ -48,7 +48,7 @@ entry: define i64 @dinsu(i64 %i, i64 %j) nounwind readnone { entry: -; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 8, 13 +; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 %shl4 = shl i64 %j, 40 %and = and i64 %shl4, 9006099743113216 %and5 = and i64 %i, -9006099743113217 diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s index 815e6f0..a7af903 100644 --- a/llvm/test/MC/Mips/mips64r2/valid.s +++ b/llvm/test/MC/Mips/mips64r2/valid.s @@ -286,6 +286,8 @@ a: swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s index 397d247..1c8edba 100644 --- a/llvm/test/MC/Mips/mips64r3/valid.s +++ b/llvm/test/MC/Mips/mips64r3/valid.s @@ -286,6 +286,8 @@ a: swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s index 3468216..1c4f838 100644 --- a/llvm/test/MC/Mips/mips64r5/valid.s +++ b/llvm/test/MC/Mips/mips64r5/valid.s @@ -287,6 +287,8 @@ a: swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s index cbe3e82..e5564f5 100644 --- a/llvm/test/MC/Mips/mips64r6/valid.s +++ b/llvm/test/MC/Mips/mips64r6/valid.s @@ -204,6 +204,8 @@ a: swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] + syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c] teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] -- 2.7.4