From 0390d892f6d1aad4050ac5d3235d50c306b0fde3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=EC=98=A4=ED=98=95=EC=84=9D/=EB=8F=99=EC=9E=91=EC=A0=9C?= =?utf8?q?=EC=96=B4Lab=28SR=29/Staff=20Engineer/=EC=82=BC=EC=84=B1?= =?utf8?q?=EC=A0=84=EC=9E=90?= Date: Tue, 6 Nov 2018 11:48:23 +0900 Subject: [PATCH] Introduce registerSubTensorInfo (#3474) Introduce registerTensorInfo to register subtensor information (not used yet) Backend allocator will use this info for allocation Signed-off-by: Hyeongseok Oh --- runtimes/neurun/src/backend/acl_cl/TensorBuilder.cc | 11 ++++++++++- runtimes/neurun/src/backend/acl_cl/TensorBuilder.h | 9 +++++++++ runtimes/neurun/src/backend/cpu/TensorBuilder.cc | 7 +++++++ runtimes/neurun/src/backend/cpu/TensorBuilder.h | 9 +++++++++ runtimes/neurun/src/backend/interface/ITensorBuilder.h | 8 +++++++- 5 files changed, 42 insertions(+), 2 deletions(-) diff --git a/runtimes/neurun/src/backend/acl_cl/TensorBuilder.cc b/runtimes/neurun/src/backend/acl_cl/TensorBuilder.cc index b86c545..4ad7c36 100644 --- a/runtimes/neurun/src/backend/acl_cl/TensorBuilder.cc +++ b/runtimes/neurun/src/backend/acl_cl/TensorBuilder.cc @@ -34,7 +34,7 @@ TensorBuilder::TensorBuilder() // DO NOTHING } -void TensorBuilder::registerTensorInfo(const ::neurun::graph::operand::Index &ind, +void TensorBuilder::registerTensorInfo(const graph::operand::Index &ind, const ::arm_compute::TensorInfo &info) { assert(_tensors.size() == 0); @@ -42,6 +42,14 @@ void TensorBuilder::registerTensorInfo(const ::neurun::graph::operand::Index &in _tensor_info_map.insert({ind, info}); } +void TensorBuilder::registerSubTensorInfo(const graph::operand::Index &ind, + const backend::operand::SubTensorInfo &info) +{ + assert(_tensors.size() == 0); + + _subtensor_info_map.insert({ind, info}); +} + void TensorBuilder::notifyFirstUse(const graph::operand::Index &) { // DO NOTHING @@ -58,6 +66,7 @@ void TensorBuilder::prepare(void) // TODO Handle SubTensor(subsumption) // Currently this TensorBuilder does not have subsumption info yet + assert(_subtensor_info_map.size() == 0); for (auto &entry : _tensor_info_map) { diff --git a/runtimes/neurun/src/backend/acl_cl/TensorBuilder.h b/runtimes/neurun/src/backend/acl_cl/TensorBuilder.h index 1a1a984..307e827 100644 --- a/runtimes/neurun/src/backend/acl_cl/TensorBuilder.h +++ b/runtimes/neurun/src/backend/acl_cl/TensorBuilder.h @@ -42,6 +42,14 @@ public: */ virtual void registerTensorInfo(const graph::operand::Index &ind, const ::arm_compute::TensorInfo &info) override; + /** + * @brief Register subtensor information to allocate on ACL-CL backend + * @param[in] ind Operand index + * @param[in] info Tensor information + */ + virtual void registerSubTensorInfo(const graph::operand::Index &ind, + const backend::operand::SubTensorInfo &info) override; + virtual void notifyFirstUse(const graph::operand::Index &) override; virtual void notifyLastUse(const graph::operand::Index &) override; @@ -58,6 +66,7 @@ public: private: std::unordered_map _tensor_info_map; + std::unordered_map _subtensor_info_map; std::unordered_map> _tensors; }; diff --git a/runtimes/neurun/src/backend/cpu/TensorBuilder.cc b/runtimes/neurun/src/backend/cpu/TensorBuilder.cc index 6a71704..526d46a 100644 --- a/runtimes/neurun/src/backend/cpu/TensorBuilder.cc +++ b/runtimes/neurun/src/backend/cpu/TensorBuilder.cc @@ -43,6 +43,13 @@ void TensorBuilder::registerTensorInfo(const graph::operand::Index &ind, _tensor_info_map.insert({ind, info}); } +void TensorBuilder::registerSubTensorInfo(const graph::operand::Index &, + const backend::operand::SubTensorInfo &) +{ + // Not supported yet + assert(false); +} + void TensorBuilder::notifyFirstUse(const graph::operand::Index &ind) { assert(_tensor_info_map.find(ind) != _tensor_info_map.end()); diff --git a/runtimes/neurun/src/backend/cpu/TensorBuilder.h b/runtimes/neurun/src/backend/cpu/TensorBuilder.h index 168ee6e..e03a514 100644 --- a/runtimes/neurun/src/backend/cpu/TensorBuilder.h +++ b/runtimes/neurun/src/backend/cpu/TensorBuilder.h @@ -43,8 +43,17 @@ public: */ virtual void registerTensorInfo(const graph::operand::Index &ind, const ::arm_compute::TensorInfo &info) override; + /** + * @brief Register subtensor information to allocate on CPU backend + * @param[in] ind Operand index + * @param[in] info Tensor information + */ + virtual void registerSubTensorInfo(const graph::operand::Index &ind, + const backend::operand::SubTensorInfo &info) override; + virtual void notifyFirstUse(const graph::operand::Index &) override; virtual void notifyLastUse(const graph::operand::Index &) override; + virtual void prepare(void) override; virtual void allocate(void) override; diff --git a/runtimes/neurun/src/backend/interface/ITensorBuilder.h b/runtimes/neurun/src/backend/interface/ITensorBuilder.h index bd8c407..d195994 100644 --- a/runtimes/neurun/src/backend/interface/ITensorBuilder.h +++ b/runtimes/neurun/src/backend/interface/ITensorBuilder.h @@ -22,6 +22,7 @@ #include "graph/operand/Index.h" #include "operand/IObject.h" +#include "backend/common/operand/SubTensorInfo.h" namespace neurun { @@ -40,10 +41,15 @@ struct ITensorBuilder */ virtual void registerTensorInfo(const graph::operand::Index &, const ::arm_compute::TensorInfo &) = 0; + /** + * @brief Register subtensor information to allocate on backend + */ + virtual void registerSubTensorInfo(const graph::operand::Index &, + const backend::operand::SubTensorInfo &) = 0; + virtual void notifyFirstUse(const graph::operand::Index &) = 0; virtual void notifyLastUse(const graph::operand::Index &) = 0; - // TODO Add an interface for adding subsumption info virtual void prepare(void) = 0; virtual void allocate(void) = 0; -- 2.7.4