From 038d24f90cc57d92172a736977a7cb5e024fe6bb Mon Sep 17 00:00:00 2001
From: Richard Osborne <richard@xmos.com>
Date: Sun, 27 Jan 2013 22:28:30 +0000
Subject: [PATCH] [XCore] Add missing l2rus instructions.

These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173634
---
 llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 6 ++++++
 llvm/lib/Target/XCore/XCoreInstrInfo.td                  | 9 ++++++++-
 llvm/test/MC/Disassembler/XCore/xcore.txt                | 6 ++++++
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
index a94f5b9..c995a9c 100644
--- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
+++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
@@ -449,6 +449,12 @@ DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
   case 0x12c:
     Inst.setOpcode(XCore::ASHR_l2rus);
     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+  case 0x12d:
+    Inst.setOpcode(XCore::OUTPW_l2rus);
+    return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
+  case 0x12e:
+    Inst.setOpcode(XCore::INPW_l2rus);
+    return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
   case 0x13c:
     Inst.setOpcode(XCore::LDAWF_l2rus);
     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td
index 613f9cb..befc096 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.td
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td
@@ -451,7 +451,6 @@ def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
                              (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
                                               GRRegs:$src3))]>;
 
-// TODO inpw, outpw
 let mayStore=1 in {
 def ST16_l3r : _FL3R<0b100001100, (outs),
                      (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
@@ -462,6 +461,14 @@ def ST8_l3r : _FL3R<0b100011100, (outs),
                     "st8 $val, $addr[$offset]", []>;
 }
 
+def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a),
+                             (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c",
+                             []>;
+
+def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs),
+                              (ins GRRegs:$a, GRRegs:$b, i32imm:$c),
+                              "outpw res[$b], $a, $c", []>;
+
 // Four operand long
 let Constraints = "$e = $a,$f = $b" in {
 def MACCU_l4r : _FL4RSrcDstSrcDst<
diff --git a/llvm/test/MC/Disassembler/XCore/xcore.txt b/llvm/test/MC/Disassembler/XCore/xcore.txt
index 21b053b..f1ec31d 100644
--- a/llvm/test/MC/Disassembler/XCore/xcore.txt
+++ b/llvm/test/MC/Disassembler/XCore/xcore.txt
@@ -403,6 +403,12 @@
 # CHECK: ldaw r8, r2[-9]
 0x09 0xfd 0xec 0xa7
 
+# CHECK: inpw r6, res[r1], 8
+0xe4 0xfc 0xee 0x97
+
+# CHECK: outpw res[r3], r0, 2
+0x0e 0xf8 0xed 0x97
+
 # ru6 / lru6 instructions
 
 # CHECK: bt r6, -5
-- 
2.7.4