From 0321bd64e6d4291731b6655e76081a3713428edc Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Fri, 5 Nov 2021 09:53:35 +0000 Subject: [PATCH] Revert "[TwoAddressInstructionPass] Update existing physreg live intervals" This reverts commit ec0e1e88d24fadb2cb22f431d66b22ee1b01cd43. It was pushed by mistake. --- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 16 ++++------------ llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll | 1 - llvm/test/CodeGen/Thumb/emergency-spill-slot.ll | 1 - llvm/test/CodeGen/X86/inline-asm-A-constraint.ll | 1 - 4 files changed, 4 insertions(+), 15 deletions(-) diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index ca7d7e9..fdd2bc6 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1539,23 +1539,15 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI, if (LIS) { LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot(); - SlotIndex endIdx = - LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber); if (RegA.isVirtual()) { LiveInterval &LI = LIS->getInterval(RegA); VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator()); - LI.addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI)); + SlotIndex endIdx = + LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber); + LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI)); for (auto &S : LI.subranges()) { VNI = S.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator()); - S.addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI)); - } - } else { - for (MCRegUnitIterator Unit(RegA, TRI); Unit.isValid(); ++Unit) { - if (LiveRange *LR = LIS->getCachedRegUnit(*Unit)) { - VNInfo *VNI = - LR->getNextValue(LastCopyIdx, LIS->getVNInfoAllocator()); - LR->addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI)); - } + S.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI)); } } } diff --git a/llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll b/llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll index 61e2872..8ae9f70 100644 --- a/llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll +++ b/llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll @@ -1,5 +1,4 @@ ; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 < %s | FileCheck %s -; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 -early-live-intervals < %s | FileCheck %s %struct.twofloat = type { float, float } %struct.twodouble = type { double, double } diff --git a/llvm/test/CodeGen/Thumb/emergency-spill-slot.ll b/llvm/test/CodeGen/Thumb/emergency-spill-slot.ll index 5661c82..f61390c 100644 --- a/llvm/test/CodeGen/Thumb/emergency-spill-slot.ll +++ b/llvm/test/CodeGen/Thumb/emergency-spill-slot.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s | FileCheck %s -; RUN: llc -early-live-intervals < %s | FileCheck %s target triple = "thumbv6m-unknown-unknown-eabi" define void @vla_emergency_spill(i32 %n) { diff --git a/llvm/test/CodeGen/X86/inline-asm-A-constraint.ll b/llvm/test/CodeGen/X86/inline-asm-A-constraint.ll index f07a13c..d8e4447 100644 --- a/llvm/test/CodeGen/X86/inline-asm-A-constraint.ll +++ b/llvm/test/CodeGen/X86/inline-asm-A-constraint.ll @@ -1,5 +1,4 @@ ; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s -; RUN: llc -mtriple=x86_64-- -early-live-intervals < %s | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64--" -- 2.7.4