From 0306b5ef07ecfa8ab949e989faa14f1eeb1ca4de Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha <ahmed.bougacha@gmail.com>
Date: Tue, 16 Aug 2016 14:02:42 +0000
Subject: [PATCH] [AArch64][GlobalISel] Select p0 G_FRAME_INDEX.

And mark it as legal.

llvm-svn: 278802
---
 .../lib/CodeGen/GlobalISel/InstructionSelector.cpp |  4 ++--
 .../Target/AArch64/AArch64InstructionSelector.cpp  | 18 +++++++++++++++
 .../lib/Target/AArch64/AArch64MachineLegalizer.cpp |  2 ++
 .../AArch64/GlobalISel/arm64-instructionselect.mir | 27 ++++++++++++++++++++++
 4 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
index 5cb7e18..d508d1e 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
@@ -32,8 +32,8 @@ bool InstructionSelector::constrainSelectedInstRegOperands(
   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
     MachineOperand &MO = I.getOperand(OpI);
 
-    // There's nothing to be done on immediates.
-    if (MO.isImm())
+    // There's nothing to be done on immediates and frame indexes.
+    if (MO.isImm() || MO.isFI())
       continue;
 
     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 367fa00..d12c7e1 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -133,6 +133,24 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
     return true;
   }
 
+  case TargetOpcode::G_FRAME_INDEX: {
+    // allocas and G_FRAME_INDEX are only supported in addrspace(0).
+    if (I.getType() != LLT::pointer(0)) {
+      DEBUG(dbgs() << "G_FRAME_INDEX pointer has type: " << I.getType()
+                   << ", expected: " << LLT::pointer(0) << '\n');
+      return false;
+    }
+
+    I.setDesc(TII.get(AArch64::ADDXri));
+    I.removeTypes();
+
+    // MOs for a #0 shifted immediate.
+    I.addOperand(MachineOperand::CreateImm(0));
+    I.addOperand(MachineOperand::CreateImm(0));
+
+    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+  }
+
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE: {
     LLT MemTy = I.getType(0);
diff --git a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
index 02be3bf..fc73215 100644
--- a/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MachineLegalizer.cpp
@@ -49,5 +49,7 @@ AArch64MachineLegalizer::AArch64MachineLegalizer() {
 
   setAction(G_BR, LLT::unsized(), Legal);
 
+  setAction(G_FRAME_INDEX, LLT::pointer(0), Legal);
+
   computeTables();
 }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
index cee9fcd..f28940b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
@@ -30,6 +30,11 @@
   define void @store_s64_gpr(i64* %addr) { ret void }
   define void @store_s32_gpr(i32* %addr) { ret void }
 
+  define void @frame_index() {
+    %ptr0 = alloca i64
+    ret void
+  }
+
   define void @selected_property() { ret void }
 
 ...
@@ -422,6 +427,28 @@ body:             |
 ...
 
 ---
+# CHECK-LABEL: name: frame_index
+name:            frame_index
+isSSA:           true
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK-NEXT:  - { id: 0, class: gpr64sp }
+registers:
+  - { id: 0, class: gpr }
+
+stack:
+  - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
+
+# CHECK:  body:
+# CHECK: %0 = ADDXri %stack.0.ptr0, 0, 0
+body:             |
+  bb.0:
+    %0(64) = G_FRAME_INDEX p0  %stack.0.ptr0
+...
+
+---
 # Check that we set the "selected" property.
 # CHECK-LABEL: name: selected_property
 # CHECK: legalized: true
-- 
2.7.4