From 030323259f46bb8f9087bbb6f07641d5e8f30d5a Mon Sep 17 00:00:00 2001 From: mwahab Date: Thu, 26 Nov 2015 13:50:47 +0000 Subject: [PATCH] [AArch64] Add sqrdmah, sqrdmsh instructions. * config/aarch64/aarch64-simd.md (aarch64_sqmovun): Fix some white-space. (aarch64_qmovun): Likewise. (aarch64_sqrdmlh): New. (aarch64_sqrdmlh_lane): New. (aarch64_sqrdmlh_laneq): New. * config/aarch64/iterators.md (UNSPEC_SQRDMLAH): New. (UNSPEC_SQRDMLSH): New. (SQRDMLH_AS): New. (rdma_as): New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@230959 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 13 ++++++ gcc/config/aarch64/aarch64-simd.md | 94 +++++++++++++++++++++++++++++++++++++- gcc/config/aarch64/iterators.md | 6 +++ 3 files changed, 111 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c626a6c..6c0d4d8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2015-11-26 Matthew Wahab + + * config/aarch64/aarch64-simd.md + (aarch64_sqmovun): Fix some white-space. + (aarch64_qmovun): Likewise. + (aarch64_sqrdmlh): New. + (aarch64_sqrdmlh_lane): New. + (aarch64_sqrdmlh_laneq): New. + * config/aarch64/iterators.md (UNSPEC_SQRDMLAH): New. + (UNSPEC_SQRDMLSH): New. + (SQRDMLH_AS): New. + (rdma_as): New. + 2015-11-26 Richard Biener PR tree-optimization/66721 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 79be6be..7910484 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -3081,7 +3081,7 @@ "TARGET_SIMD" "sqxtun\\t%0, %1" [(set_attr "type" "neon_sat_shift_imm_narrow_q")] - ) +) ;; sqmovn and uqmovn @@ -3092,7 +3092,7 @@ "TARGET_SIMD" "qxtn\\t%0, %1" [(set_attr "type" "neon_sat_shift_imm_narrow_q")] - ) +) ;; q @@ -3180,6 +3180,96 @@ [(set_attr "type" "neon_sat_mul__scalar")] ) +;; sqrdml[as]h. + +(define_insn "aarch64_sqrdmlh" + [(set (match_operand:VSDQ_HSI 0 "register_operand" "=w") + (unspec:VSDQ_HSI + [(match_operand:VSDQ_HSI 1 "register_operand" "0") + (match_operand:VSDQ_HSI 2 "register_operand" "w") + (match_operand:VSDQ_HSI 3 "register_operand" "w")] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + "sqrdmlh\\t%0, %2, %3" + [(set_attr "type" "neon_sat_mla__long")] +) + +;; sqrdml[as]h_lane. + +(define_insn "aarch64_sqrdmlh_lane" + [(set (match_operand:VDQHS 0 "register_operand" "=w") + (unspec:VDQHS + [(match_operand:VDQHS 1 "register_operand" "0") + (match_operand:VDQHS 2 "register_operand" "w") + (vec_select: + (match_operand: 3 "register_operand" "w") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); + return + "sqrdmlh\\t%0., %2., %3.[%4]"; + } + [(set_attr "type" "neon_sat_mla__scalar_long")] +) + +(define_insn "aarch64_sqrdmlh_lane" + [(set (match_operand:SD_HSI 0 "register_operand" "=w") + (unspec:SD_HSI + [(match_operand:SD_HSI 1 "register_operand" "0") + (match_operand:SD_HSI 2 "register_operand" "w") + (vec_select: + (match_operand: 3 "register_operand" "w") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); + return + "sqrdmlh\\t%0, %2, %3.[%4]"; + } + [(set_attr "type" "neon_sat_mla__scalar_long")] +) + +;; sqrdml[as]h_laneq. + +(define_insn "aarch64_sqrdmlh_laneq" + [(set (match_operand:VDQHS 0 "register_operand" "=w") + (unspec:VDQHS + [(match_operand:VDQHS 1 "register_operand" "0") + (match_operand:VDQHS 2 "register_operand" "w") + (vec_select: + (match_operand: 3 "register_operand" "w") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); + return + "sqrdmlh\\t%0., %2., %3.[%4]"; + } + [(set_attr "type" "neon_sat_mla__scalar_long")] +) + +(define_insn "aarch64_sqrdmlh_laneq" + [(set (match_operand:SD_HSI 0 "register_operand" "=w") + (unspec:SD_HSI + [(match_operand:SD_HSI 1 "register_operand" "0") + (match_operand:SD_HSI 2 "register_operand" "w") + (vec_select: + (match_operand: 3 "register_operand" "w") + (parallel [(match_operand:SI 4 "immediate_operand" "i")]))] + SQRDMLH_AS))] + "TARGET_SIMD_RDMA" + { + operands[4] = GEN_INT (ENDIAN_LANE_N (mode, INTVAL (operands[4]))); + return + "sqrdmlh\\t%0, %2, %3.[%4]"; + } + [(set_attr "type" "neon_sat_mla__scalar_long")] +) + ;; vqdml[sa]l (define_insn "aarch64_sqdmll" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d6a57f6..9343c9c 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -304,6 +304,8 @@ UNSPEC_PMULL2 ; Used in aarch64-simd.md. UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. UNSPEC_VEC_SHR ; Used in aarch64-simd.md. + UNSPEC_SQRDMLAH ; Used in aarch64-simd.md. + UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. ]) ;; ------------------------------------------------------------------ @@ -975,6 +977,8 @@ UNSPEC_SQSHRN UNSPEC_UQSHRN UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) +(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH]) + (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 UNSPEC_TRN1 UNSPEC_TRN2 UNSPEC_UZP1 UNSPEC_UZP2]) @@ -1149,3 +1153,5 @@ (UNSPEC_SHA1M "m")]) (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) + +(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")]) -- 2.7.4