From 03006fd3c43d81106d9b29a4b602e18836434614 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 19 Jul 2016 16:27:56 +0000 Subject: [PATCH] AMDGPU: Only use legal inline immediates with kill pseudo Only if the value is negative or positive is what matters, so use a constant that doesn't require an instruction to materialize. These should really just emit the write exec directly, but for stick with the kill pseudo-terminator. llvm-svn: 275988 --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 + llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 5 +++++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 9 +++++++-- llvm/lib/Target/AMDGPU/SIInstructions.td | 2 +- 5 files changed, 15 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index e24f54e..a69e669 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -2834,6 +2834,7 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(BUILD_VERTICAL_VECTOR) NODE_NAME_CASE(CONST_DATA_PTR) NODE_NAME_CASE(PC_ADD_REL_OFFSET) + NODE_NAME_CASE(KILL) case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break; NODE_NAME_CASE(SENDMSG) NODE_NAME_CASE(INTERP_MOV) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index f937694..071390b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -303,6 +303,7 @@ enum NodeType : unsigned { INTERP_P1, INTERP_P2, PC_ADD_REL_OFFSET, + KILL, FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE, STORE_MSKOR, LOAD_CONSTANT, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td index cf087b7..85675c8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td @@ -40,6 +40,8 @@ def AMDGPUFmasOp : SDTypeProfile<1, 4, [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>] >; +def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>; + //===----------------------------------------------------------------------===// // AMDGPU DAG Nodes // @@ -246,6 +248,9 @@ def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2", SDTypeProfile<1, 4, [SDTCisFP<0>]>, [SDNPInGlue]>; +def AMDGPUkill : SDNode<"AMDGPUISD::KILL", AMDGPUKillSDT, + [SDNPHasChain, SDNPSideEffect]>; + //===----------------------------------------------------------------------===// // Flow Control Profile Types //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 7da2e08..a2c4e6a 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2290,12 +2290,17 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, Op->getVTList(), Ops, VT, MMO); } case AMDGPUIntrinsic::AMDGPU_kill: { - if (const ConstantFPSDNode *K = dyn_cast(Op.getOperand(2))) { + SDValue Src = Op.getOperand(2); + if (const ConstantFPSDNode *K = dyn_cast(Src)) { if (!K->isNegative()) return Chain; + + SDValue NegOne = DAG.getTargetConstant(FloatToBits(-1.0f), DL, MVT::i32); + return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, NegOne); } - return Op; + SDValue Cast = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Src); + return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, Cast); } default: return SDValue(); diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index a648506..f1e8c23 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1996,7 +1996,7 @@ def SI_END_CF : PseudoInstSI < let Uses = [EXEC], Defs = [EXEC,VCC] in { def SI_KILL : PseudoInstSI < (outs), (ins VSrc_32:$src), - [(int_AMDGPU_kill f32:$src)]> { + [(AMDGPUkill i32:$src)]> { let isConvergent = 1; let usesCustomInserter = 1; } -- 2.7.4