From 02ebad900db4ef1ac42cbfb41b433919a4c857a2 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Kristian=20H=C3=B8gsberg?= Date: Wed, 4 Jul 2012 23:09:14 -0400 Subject: [PATCH] intel: Add offset field to miptree MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This lets us specify an offset into the bo where the miptree starts, which will let us set up a texture for a single plane in a planar buffer. Signed-off-by: Kristian Høgsberg Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i915/i915_texstate.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +++-- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 5 +++-- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 1 + src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 4 ++++ src/mesa/drivers/dri/intel/intel_tex_image.c | 9 ++++++--- 6 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index fd63a69..9e6d3b1 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -165,7 +165,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) drm_intel_bo_reference(intelObj->mt->region->bo); i915->state.tex_buffer[unit] = intelObj->mt->region->bo; - i915->state.tex_offset[unit] = 0; /* Always the origin of the miptree */ + i915->state.tex_offset[unit] = intelObj->mt->offset; format = translate_texture_format(firstImage->TexFormat, sampler->DepthMode); diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 26e65af..04ae6b2 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -736,7 +736,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) sampler->sRGBDecode) << BRW_SURFACE_FORMAT_SHIFT)); - surf[1] = intelObj->mt->region->bo->offset; /* reloc */ + surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT | (width - 1) << BRW_SURFACE_WIDTH_SHIFT | @@ -754,7 +754,8 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[surf_index] + 4, - intelObj->mt->region->bo, 0, + intelObj->mt->region->bo, + intelObj->mt->offset, I915_GEM_DOMAIN_SAMPLER, 0); } diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index d34bf53..557f36f 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -273,7 +273,8 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) * - render_cache_read_write (exists on gen6 but ignored here) */ - surf->ss1.base_addr = intelObj->mt->region->bo->offset; /* reloc */ + surf->ss1.base_addr = + intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ surf->ss2.width = width - 1; surf->ss2.height = height - 1; @@ -303,7 +304,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[surf_index] + offsetof(struct gen7_surface_state, ss1), - intelObj->mt->region->bo, 0, + intelObj->mt->region->bo, intelObj->mt->offset, I915_GEM_DOMAIN_SAMPLER, 0); gen7_check_surface_setup(surf, false /* is_render_target */); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 7018c37..41d337f 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -233,6 +233,7 @@ intel_miptree_create(struct intel_context *intel, mt->total_width, mt->total_height, expect_accelerated_upload); + mt->offset = 0; if (!mt->region) { intel_miptree_release(&mt); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h index 5c57e02..564c6a4 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h @@ -210,6 +210,10 @@ struct intel_mipmap_tree */ struct intel_region *region; + /* Offset into region bo where miptree starts: + */ + uint32_t offset; + /** * \brief HiZ miptree * diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 6e7e7018..0caa2e2 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -242,7 +242,8 @@ intel_set_texture_image_region(struct gl_context *ctx, struct intel_region *region, GLenum target, GLenum internalFormat, - gl_format format) + gl_format format, + uint32_t offset) { struct intel_context *intel = intel_context(ctx); struct intel_texture_image *intel_image = intel_texture_image(image); @@ -261,6 +262,7 @@ intel_set_texture_image_region(struct gl_context *ctx, if (intel_image->mt == NULL) return; + intel_image->mt->offset = offset; intel_image->base.RowStride = region->pitch; /* Immediately validate the image to the object. */ @@ -316,7 +318,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, _mesa_lock_texture(&intel->ctx, texObj); texImage = _mesa_get_tex_image(ctx, texObj, target, level); intel_set_texture_image_region(ctx, texImage, rb->mt->region, target, - internalFormat, texFormat); + internalFormat, texFormat, 0); _mesa_unlock_texture(&intel->ctx, texObj); } @@ -347,7 +349,8 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target, return; intel_set_texture_image_region(ctx, texImage, image->region, - target, image->internal_format, image->format); + target, image->internal_format, + image->format, 0); } #endif -- 2.7.4