From 02daec00a28ac6563dc986b53a9af20b7c1cef4c Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 2 Apr 2018 01:12:32 +0000 Subject: [PATCH] [X86] Make sure all the classes declare in the Haswell scheduler model are prefixed with HW. The tablegen files all share a namespace so we shouldn't use a generic names in a specific scheduler model. llvm-svn: 328955 --- llvm/lib/Target/X86/X86SchedHaswell.td | 132 ++++++++++++++++----------------- 1 file changed, 66 insertions(+), 66 deletions(-) diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 33d6aa9..8ab64f0 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -282,31 +282,31 @@ def : WriteRes; //-- Specific Scheduling Models --// // Starting with P0. -def WriteP0 : SchedWriteRes<[HWPort0]>; +def HWWriteP0 : SchedWriteRes<[HWPort0]>; -def WriteP01 : SchedWriteRes<[HWPort01]>; +def HWWriteP01 : SchedWriteRes<[HWPort01]>; -def Write2P01 : SchedWriteRes<[HWPort01]> { +def HWWrite2P01 : SchedWriteRes<[HWPort01]> { let NumMicroOps = 2; } -def Write3P01 : SchedWriteRes<[HWPort01]> { +def HWWrite3P01 : SchedWriteRes<[HWPort01]> { let NumMicroOps = 3; } -def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { +def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { let NumMicroOps = 2; } -def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { +def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { let NumMicroOps = 3; let ResourceCycles = [2, 1]; } // Starting with P1. -def WriteP1 : SchedWriteRes<[HWPort1]>; +def HWWriteP1 : SchedWriteRes<[HWPort1]>; -def Write2P1 : SchedWriteRes<[HWPort1]> { +def HWWrite2P1 : SchedWriteRes<[HWPort1]> { let NumMicroOps = 2; let ResourceCycles = [2]; } @@ -324,217 +324,217 @@ def Write2P1 : SchedWriteRes<[HWPort1]> { //-- Move instructions --// // XLAT. -def WriteXLAT : SchedWriteRes<[]> { +def HWWriteXLAT : SchedWriteRes<[]> { let Latency = 7; let NumMicroOps = 3; } -def : InstRW<[WriteXLAT], (instregex "XLAT")>; +def : InstRW<[HWWriteXLAT], (instregex "XLAT")>; // PUSHA. -def WritePushA : SchedWriteRes<[]> { +def HWWritePushA : SchedWriteRes<[]> { let NumMicroOps = 19; } -def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>; +def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>; // POPA. -def WritePopA : SchedWriteRes<[]> { +def HWWritePopA : SchedWriteRes<[]> { let NumMicroOps = 18; } -def : InstRW<[WritePopA], (instregex "POPA(16|32)")>; +def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>; //-- Arithmetic instructions --// // DIV. // r8. -def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { +def HWWriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { let Latency = 22; let NumMicroOps = 9; } -def : InstRW<[WriteDiv8], (instregex "DIV8r")>; +def : InstRW<[HWWriteDiv8], (instregex "DIV8r")>; // IDIV. // r8. -def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { +def HWWriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> { let Latency = 23; let NumMicroOps = 9; } -def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>; +def : InstRW<[HWWriteIDiv8], (instregex "IDIV8r")>; // BT. // m,r. -def WriteBTmr : SchedWriteRes<[]> { +def HWWriteBTmr : SchedWriteRes<[]> { let NumMicroOps = 10; } -def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>; +def : InstRW<[HWWriteBTmr], (instregex "BT(16|32|64)mr")>; // BTR BTS BTC. // m,r. -def WriteBTRSCmr : SchedWriteRes<[]> { +def HWWriteBTRSCmr : SchedWriteRes<[]> { let NumMicroOps = 11; } -def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>; +def : InstRW<[HWWriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>; //-- Control transfer instructions --// // CALL. // i. -def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { +def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { let NumMicroOps = 4; let ResourceCycles = [1, 2, 1]; } -def : InstRW<[WriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>; +def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>; // BOUND. // r,m. -def WriteBOUND : SchedWriteRes<[]> { +def HWWriteBOUND : SchedWriteRes<[]> { let NumMicroOps = 15; } -def : InstRW<[WriteBOUND], (instregex "BOUNDS(16|32)rm")>; +def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>; // INTO. -def WriteINTO : SchedWriteRes<[]> { +def HWWriteINTO : SchedWriteRes<[]> { let NumMicroOps = 4; } -def : InstRW<[WriteINTO], (instregex "INTO")>; +def : InstRW<[HWWriteINTO], (instregex "INTO")>; //-- String instructions --// // LODSB/W. -def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>; +def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>; // LODSD/Q. -def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>; +def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>; // MOVS. -def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> { +def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> { let Latency = 4; let NumMicroOps = 5; let ResourceCycles = [2, 1, 2]; } -def : InstRW<[WriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; +def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; // CMPS. -def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> { +def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> { let Latency = 4; let NumMicroOps = 5; let ResourceCycles = [2, 3]; } -def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>; +def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>; //-- Other --// // RDPMC.f -def WriteRDPMC : SchedWriteRes<[]> { +def HWWriteRDPMC : SchedWriteRes<[]> { let NumMicroOps = 34; } -def : InstRW<[WriteRDPMC], (instregex "RDPMC")>; +def : InstRW<[HWWriteRDPMC], (instregex "RDPMC")>; // RDRAND. -def WriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { +def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { let NumMicroOps = 17; let ResourceCycles = [1, 16]; } -def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>; +def : InstRW<[HWWriteRDRAND], (instregex "RDRAND(16|32|64)r")>; //=== Floating Point x87 Instructions ===// //-- Move instructions --// // FLD. // m80. -def : InstRW<[WriteP01], (instregex "LD_Frr")>; +def : InstRW<[HWWriteP01], (instregex "LD_Frr")>; // FBLD. // m80. -def WriteFBLD : SchedWriteRes<[]> { +def HWWriteFBLD : SchedWriteRes<[]> { let Latency = 47; let NumMicroOps = 43; } -def : InstRW<[WriteFBLD], (instregex "FBLDm")>; +def : InstRW<[HWWriteFBLD], (instregex "FBLDm")>; // FST(P). // r. -def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>; +def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>; // FLDZ. -def : InstRW<[WriteP01], (instregex "LD_F0")>; +def : InstRW<[HWWriteP01], (instregex "LD_F0")>; // FLDPI FLDL2E etc. -def : InstRW<[Write2P01], (instregex "FLDPI", "FLDL2(T|E)", "FLDL(G|N)2")>; +def : InstRW<[HWWrite2P01], (instregex "FLDPI", "FLDL2(T|E)", "FLDL(G|N)2")>; // FFREE. -def : InstRW<[WriteP01], (instregex "FFREE")>; +def : InstRW<[HWWriteP01], (instregex "FFREE")>; // FNSAVE. -def WriteFNSAVE : SchedWriteRes<[]> { +def HWWriteFNSAVE : SchedWriteRes<[]> { let NumMicroOps = 147; } -def : InstRW<[WriteFNSAVE], (instregex "FSAVEm")>; +def : InstRW<[HWWriteFNSAVE], (instregex "FSAVEm")>; // FRSTOR. -def WriteFRSTOR : SchedWriteRes<[]> { +def HWWriteFRSTOR : SchedWriteRes<[]> { let NumMicroOps = 90; } -def : InstRW<[WriteFRSTOR], (instregex "FRSTORm")>; +def : InstRW<[HWWriteFRSTOR], (instregex "FRSTORm")>; //-- Arithmetic instructions --// // FABS. -def : InstRW<[WriteP0], (instregex "ABS_F")>; +def : InstRW<[HWWriteP0], (instregex "ABS_F")>; // FCHS. -def : InstRW<[WriteP0], (instregex "CHS_F")>; +def : InstRW<[HWWriteP0], (instregex "CHS_F")>; // FCOMPP FUCOMPP. // r. -def : InstRW<[Write2P01], (instregex "FCOMPP", "UCOM_FPPr")>; +def : InstRW<[HWWrite2P01], (instregex "FCOMPP", "UCOM_FPPr")>; // FCOMI(P) FUCOMI(P). // m. -def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr", - "UCOM_FIPr")>; +def : InstRW<[HWWrite3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr", + "UCOM_FIPr")>; // FTST. -def : InstRW<[WriteP1], (instregex "TST_F")>; +def : InstRW<[HWWriteP1], (instregex "TST_F")>; // FXAM. -def : InstRW<[Write2P1], (instregex "FXAM")>; +def : InstRW<[HWWrite2P1], (instregex "FXAM")>; // FPREM. -def WriteFPREM : SchedWriteRes<[]> { +def HWWriteFPREM : SchedWriteRes<[]> { let Latency = 19; let NumMicroOps = 28; } -def : InstRW<[WriteFPREM], (instrs FPREM)>; +def : InstRW<[HWWriteFPREM], (instrs FPREM)>; // FPREM1. -def WriteFPREM1 : SchedWriteRes<[]> { +def HWWriteFPREM1 : SchedWriteRes<[]> { let Latency = 27; let NumMicroOps = 41; } -def : InstRW<[WriteFPREM1], (instrs FPREM1)>; +def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>; // FRNDINT. -def WriteFRNDINT : SchedWriteRes<[]> { +def HWWriteFRNDINT : SchedWriteRes<[]> { let Latency = 11; let NumMicroOps = 17; } -def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>; +def : InstRW<[HWWriteFRNDINT], (instregex "FRNDINT")>; //-- Math instructions --// // FSCALE. -def WriteFSCALE : SchedWriteRes<[]> { +def HWWriteFSCALE : SchedWriteRes<[]> { let Latency = 75; // 49-125 let NumMicroOps = 50; // 25-75 } -def : InstRW<[WriteFSCALE], (instregex "FSCALE")>; +def : InstRW<[HWWriteFSCALE], (instregex "FSCALE")>; // FXTRACT. -def WriteFXTRACT : SchedWriteRes<[]> { +def HWWriteFXTRACT : SchedWriteRes<[]> { let Latency = 15; let NumMicroOps = 17; } -def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>; +def : InstRW<[HWWriteFXTRACT], (instregex "FXTRACT")>; //////////////////////////////////////////////////////////////////////////////// // Horizontal add/sub instructions. -- 2.7.4