From 025c1587a29b8320306a79d35029d69382d63364 Mon Sep 17 00:00:00 2001
From: Shengchen Kan <shengchen.kan@intel.com>
Date: Thu, 18 May 2023 18:30:54 +0800
Subject: [PATCH] [X86][MC] Move encoding optimization for VCMP to
 X86::optimizeInstFromVEX3ToVEX2, NFCI

This is a follow-up for c13ed1cc7578
---
 .../X86/MCTargetDesc/X86EncodingOptimization.cpp   | 19 ++++++++++++++++++
 llvm/lib/Target/X86/X86MCInstLower.cpp             | 23 ----------------------
 2 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
index 6b44356..b398bf0 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
@@ -48,6 +48,25 @@ bool X86::optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc) {
     OpIdx2 = 2;
     break;
   }
+  case X86::VCMPPDrri:
+  case X86::VCMPPDYrri:
+  case X86::VCMPPSrri:
+  case X86::VCMPPSYrri:
+  case X86::VCMPSDrr:
+  case X86::VCMPSSrr: {
+    switch (MI.getOperand(3).getImm() & 0x7) {
+    default:
+      return false;
+    case 0x00: // EQUAL
+    case 0x03: // UNORDERED
+    case 0x04: // NOT EQUAL
+    case 0x07: // ORDERED
+      OpIdx1 = 1;
+      OpIdx2 = 2;
+      break;
+    }
+    break;
+  }
     // Commute operands to get a smaller encoding by using VEX.R instead of
     // VEX.B if one of the registers is extended, but other isn't.
     FROM_TO(VMOVZPQILo2PQIrr, VMOVPQI2QIrr, 0, 1)
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index db5bf15..7bb05c4 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -584,29 +584,6 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
     SimplifyShortImmForm(OutMI, NewOpc);
     break;
   }
-  case X86::VCMPPDrri:
-  case X86::VCMPPDYrri:
-  case X86::VCMPPSrri:
-  case X86::VCMPPSYrri:
-  case X86::VCMPSDrr:
-  case X86::VCMPSSrr: {
-    // Swap the operands if it will enable a 2 byte VEX encoding.
-    // FIXME: Change the immediate to improve opportunities?
-    if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()) &&
-        X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
-      unsigned Imm = MI->getOperand(3).getImm() & 0x7;
-      switch (Imm) {
-      default: break;
-      case 0x00: // EQUAL
-      case 0x03: // UNORDERED
-      case 0x04: // NOT EQUAL
-      case 0x07: // ORDERED
-        std::swap(OutMI.getOperand(1), OutMI.getOperand(2));
-        break;
-      }
-    }
-    break;
-  }
   case X86::MASKMOVDQU:
   case X86::VMASKMOVDQU:
     if (In64BitMode)
-- 
2.7.4