From 0211290630956106543146d6844b8c9f6450b2ea Mon Sep 17 00:00:00 2001
From: Zhao halley <halley.zhao@intel.com>
Date: Thu, 17 May 2012 15:39:43 +0800
Subject: [PATCH] add YV12 to YUY2 conversion

---
 src/i965_post_processing.c                     | 60 +++++++++++++++++++++++++-
 src/i965_post_processing.h                     |  3 +-
 src/shaders/post_processing/gen5_6/Makefile.am |  3 ++
 3 files changed, 64 insertions(+), 2 deletions(-)

diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c
index 0debdd9..0109292 100755
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -95,6 +95,10 @@ static const uint32_t pp_nv12_load_save_pa_gen5[][4] = {
 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5"
 };
 
+static const uint32_t pp_pl3_load_save_pa_gen5[][4] = {
+#include "shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5"
+};
+
 static VAStatus pp_null_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
                                    const struct i965_surface *src_surface,
                                    const VARectangle *src_rect,
@@ -259,6 +263,18 @@ static struct pp_module pp_modules_gen5[] = {
         pp_plx_load_save_plx_initialize,
     },
 
+    {
+        {
+            "PL3_PA module",
+            PP_PL3_LOAD_SAVE_PA,
+            pp_pl3_load_save_pa_gen5,
+            sizeof(pp_pl3_load_save_pa_gen5),
+            NULL,
+        },
+    
+        pp_plx_load_save_plx_initialize,
+    },
+
 };
 
 static const uint32_t pp_null_gen6[][4] = {
@@ -301,6 +317,10 @@ static const uint32_t pp_nv12_load_save_pa_gen6[][4] = {
 #include "shaders/post_processing/gen5_6/nv12_load_save_pa.g6b"
 };
 
+static const uint32_t pp_pl3_load_save_pa_gen6[][4] = {
+#include "shaders/post_processing/gen5_6/pl3_load_save_pa.g6b"
+};
+
 static struct pp_module pp_modules_gen6[] = {
     {
         {
@@ -421,6 +441,17 @@ static struct pp_module pp_modules_gen6[] = {
         pp_plx_load_save_plx_initialize,
     },
     
+    {
+        {
+            "PL3_PA module",
+            PP_PL3_LOAD_SAVE_PA,
+            pp_pl3_load_save_pa_gen6,
+            sizeof(pp_pl3_load_save_pa_gen6),
+            NULL,
+        },
+    
+        pp_plx_load_save_plx_initialize,
+    },
     
 };
 
@@ -459,6 +490,8 @@ static const uint32_t pp_nv12_dn_gen7[][4] = {
 };
 static const uint32_t pp_nv12_load_save_pa_gen7[][4] = {
 };
+static const uint32_t pp_pl3_load_save_pa_gen7[][4] = {
+};
 
 static VAStatus gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
                                            const struct i965_surface *src_surface,
@@ -598,6 +631,18 @@ static struct pp_module pp_modules_gen7[] = {
     
         pp_plx_load_save_plx_initialize,
     },
+
+    {
+        {
+            "PL3_PA module",
+            PP_PL3_LOAD_SAVE_PA,
+            pp_pl3_load_save_pa_gen7,
+            sizeof(pp_pl3_load_save_pa_gen7),
+            NULL,
+        },
+    
+        pp_plx_load_save_plx_initialize,
+    },
     
 };
 
@@ -3818,7 +3863,8 @@ i965_image_pl3_processing(VADriverContextP ctx,
                                       dst_rect,
                                       PP_PL3_LOAD_SAVE_N12,
                                       NULL);
-    } else {
+    } else if (fourcc == VA_FOURCC('I', 'M', 'C', '1') || 
+               fourcc == VA_FOURCC('I', 'M', 'C', '3')) {
         i965_post_processing_internal(ctx, i965->pp_context,
                                       src_surface,
                                       src_rect,
@@ -3826,6 +3872,18 @@ i965_image_pl3_processing(VADriverContextP ctx,
                                       dst_rect,
                                       PP_PL3_LOAD_SAVE_PL3,
                                       NULL);
+    } else if (fourcc == VA_FOURCC('Y', 'U', 'Y', '2')) {
+        i965_post_processing_internal(ctx, i965->pp_context,
+                                      src_surface,
+                                      src_rect,
+                                      dst_surface,
+                                      dst_rect,
+                                      PP_PL3_LOAD_SAVE_PA,
+                                      NULL);
+
+    }
+    else {
+        assert(0);
     }
 
     intel_batchbuffer_flush(pp_context->batch);
diff --git a/src/i965_post_processing.h b/src/i965_post_processing.h
index 65112be..4b8f606 100755
--- a/src/i965_post_processing.h
+++ b/src/i965_post_processing.h
@@ -48,9 +48,10 @@ enum
     PP_NV12_DNDI,
     PP_NV12_DN,
     PP_NV12_LOAD_SAVE_PA,
+    PP_PL3_LOAD_SAVE_PA,
 };
 
-#define NUM_PP_MODULES                  10
+#define NUM_PP_MODULES                  11
 
 struct i965_post_processing_context;
 
diff --git a/src/shaders/post_processing/gen5_6/Makefile.am b/src/shaders/post_processing/gen5_6/Makefile.am
index 102e9d8..002f1b0 100755
--- a/src/shaders/post_processing/gen5_6/Makefile.am
+++ b/src/shaders/post_processing/gen5_6/Makefile.am
@@ -17,6 +17,7 @@ INTEL_PP_G4B_GEN5 = \
 	pl3_load_save_nv12.g4b.gen5             \
 	pl3_load_save_pl3.g4b.gen5              \
 	nv12_load_save_pa.g4b.gen5				\
+	pl3_load_save_pa.g4b.gen5				\
 	$(NULL)
 
 INTEL_PP_G6B = \
@@ -29,6 +30,7 @@ INTEL_PP_G6B = \
 	pl3_load_save_nv12.g6b          	\
 	pl3_load_save_pl3.g6b           	\
 	nv12_load_save_pa.g6b				\
+	pl3_load_save_pa.g6b				\
 	$(NULL)
 
 INTEL_PP_ASM = \
@@ -41,6 +43,7 @@ INTEL_PP_ASM = \
 	pl3_load_save_nv12.asm          	\
 	pl3_load_save_pl3.asm           	\
 	nv12_load_save_pa.asm				\
+	pl3_load_save_pa.asm				\
 	$(NULL)
 
 INTEL_PP_ASM += \
-- 
2.7.4