From 0191a97d391802a2dceb367f11b6fbe2affcb9d0 Mon Sep 17 00:00:00 2001 From: Bruce Forstall Date: Mon, 1 May 2017 18:49:13 -0700 Subject: [PATCH] Refactor GT_NEG/GT_NOT Commit migrated from https://github.com/dotnet/coreclr/commit/0c9f07fffb14476d904e0fad3bbfec8071c4ad4d --- src/coreclr/src/jit/codegenarm.cpp | 75 ++++++++++++++++++++---------------- src/coreclr/src/jit/codegenarm64.cpp | 61 ++++++++++++++++------------- src/coreclr/src/jit/codegenlinear.h | 2 + 3 files changed, 79 insertions(+), 59 deletions(-) diff --git a/src/coreclr/src/jit/codegenarm.cpp b/src/coreclr/src/jit/codegenarm.cpp index 1eaf9ff..5892757 100644 --- a/src/coreclr/src/jit/codegenarm.cpp +++ b/src/coreclr/src/jit/codegenarm.cpp @@ -355,34 +355,8 @@ void CodeGen::genCodeForTreeNode(GenTreePtr treeNode) break; case GT_NOT: - assert(!varTypeIsFloating(targetType)); - - __fallthrough; - case GT_NEG: - { - instruction ins = genGetInsForOper(treeNode->OperGet(), targetType); - - // The arithmetic node must be sitting in a register (since it's not contained) - assert(!treeNode->isContained()); - // The dst can only be a register. - assert(targetReg != REG_NA); - - GenTreePtr operand = treeNode->gtGetOp1(); - assert(!operand->isContained()); - // The src must be a register. - regNumber operandReg = genConsumeReg(operand); - - if (ins == INS_vneg) - { - getEmitter()->emitIns_R_R(ins, emitTypeSize(treeNode), targetReg, operandReg); - } - else - { - getEmitter()->emitIns_R_R_I(ins, emitTypeSize(treeNode), targetReg, operandReg, 0); - } - } - genProduceReg(treeNode); + genCodeForNegNot(treeNode); break; case GT_OR: @@ -488,14 +462,10 @@ void CodeGen::genCodeForTreeNode(GenTreePtr treeNode) break; case GT_LEA: - { // if we are here, it is the case where there is an LEA that cannot // be folded into a parent instruction - GenTreeAddrMode* lea = treeNode->AsAddrMode(); - genLeaInstruction(lea); - } - // genLeaInstruction calls genProduceReg() - break; + genLeaInstruction(treeNode->AsAddrMode()); + break; case GT_IND: genConsumeAddress(treeNode->AsIndir()->Addr()); @@ -1238,6 +1208,45 @@ void CodeGen::genCodeForStoreBlk(GenTreeBlk* blkOp) } //------------------------------------------------------------------------ +// genCodeForNegNot: Produce code for a GT_NEG/GT_NOT node. +// +// Arguments: +// tree - the node +// +void CodeGen::genCodeForNegNot(GenTree* tree) +{ + assert(tree->OperIs(GT_NEG, GT_NOT)); + + var_types targetType = tree->TypeGet(); + + assert(!tree->OperIs(GT_NOT) || !varTypeIsFloating(targetType)); + + regNumber targetReg = tree->gtRegNum; + instruction ins = genGetInsForOper(tree->OperGet(), targetType); + + // The arithmetic node must be sitting in a register (since it's not contained) + assert(!tree->isContained()); + // The dst can only be a register. + assert(targetReg != REG_NA); + + GenTreePtr operand = tree->gtGetOp1(); + assert(!operand->isContained()); + // The src must be a register. + regNumber operandReg = genConsumeReg(operand); + + if (ins == INS_vneg) + { + getEmitter()->emitIns_R_R(ins, emitTypeSize(tree), targetReg, operandReg); + } + else + { + getEmitter()->emitIns_R_R_I(ins, emitTypeSize(tree), targetReg, operandReg, 0); + } + + genProduceReg(tree); +} + +//------------------------------------------------------------------------ // genCodeForShiftLong: Generates the code sequence for a GenTree node that // represents a three operand bit shift or rotate operation (<>Lo). // diff --git a/src/coreclr/src/jit/codegenarm64.cpp b/src/coreclr/src/jit/codegenarm64.cpp index 6a9619a..4ab3df6 100644 --- a/src/coreclr/src/jit/codegenarm64.cpp +++ b/src/coreclr/src/jit/codegenarm64.cpp @@ -2082,27 +2082,8 @@ void CodeGen::genCodeForTreeNode(GenTreePtr treeNode) break; case GT_NOT: - assert(!varTypeIsFloating(targetType)); - - __fallthrough; - case GT_NEG: - { - instruction ins = genGetInsForOper(treeNode->OperGet(), targetType); - - // The arithmetic node must be sitting in a register (since it's not contained) - assert(!treeNode->isContained()); - // The dst can only be a register. - assert(targetReg != REG_NA); - - GenTreePtr operand = treeNode->gtGetOp1(); - assert(!operand->isContained()); - // The src must be a register. - regNumber operandReg = genConsumeReg(operand); - - getEmitter()->emitIns_R_R(ins, emitTypeSize(treeNode), targetReg, operandReg); - } - genProduceReg(treeNode); + genCodeForNegNot(treeNode); break; case GT_DIV: @@ -2297,14 +2278,10 @@ void CodeGen::genCodeForTreeNode(GenTreePtr treeNode) break; case GT_LEA: - { // if we are here, it is the case where there is an LEA that cannot // be folded into a parent instruction - GenTreeAddrMode* lea = treeNode->AsAddrMode(); - genLeaInstruction(lea); - } - // genLeaInstruction calls genProduceReg() - break; + genLeaInstruction(treeNode->AsAddrMode()); + break; case GT_IND: genConsumeAddress(treeNode->AsIndir()->Addr()); @@ -2906,6 +2883,38 @@ BAILOUT: genProduceReg(tree); } +//------------------------------------------------------------------------ +// genCodeForNegNot: Produce code for a GT_NEG/GT_NOT node. +// +// Arguments: +// tree - the node +// +void CodeGen::genCodeForNegNot(GenTree* tree) +{ + assert(tree->OperIs(GT_NEG, GT_NOT)); + + var_types targetType = tree->TypeGet(); + + assert(!tree->OperIs(GT_NOT) || !varTypeIsFloating(targetType)); + + regNumber targetReg = tree->gtRegNum; + instruction ins = genGetInsForOper(tree->OperGet(), targetType); + + // The arithmetic node must be sitting in a register (since it's not contained) + assert(!tree->isContained()); + // The dst can only be a register. + assert(targetReg != REG_NA); + + GenTreePtr operand = tree->gtGetOp1(); + assert(!operand->isContained()); + // The src must be a register. + regNumber operandReg = genConsumeReg(operand); + + getEmitter()->emitIns_R_R(ins, emitTypeSize(tree), targetReg, operandReg); + + genProduceReg(tree); +} + // Generate code for InitBlk by performing a loop unroll // Preconditions: // a) Both the size and fill byte value are integer constants. diff --git a/src/coreclr/src/jit/codegenlinear.h b/src/coreclr/src/jit/codegenlinear.h index 57a46c3..d0281a0 100644 --- a/src/coreclr/src/jit/codegenlinear.h +++ b/src/coreclr/src/jit/codegenlinear.h @@ -173,6 +173,8 @@ void genCodeForShiftLong(GenTreePtr tree); void genCodeForShiftRMW(GenTreeStoreInd* storeInd); #endif // _TARGET_XARCH_ +void genCodeForNegNot(GenTree* tree); + void genCodeForLclVar(GenTreeLclVar* tree); void genCodeForLclFld(GenTreeLclFld* tree); -- 2.7.4