From 01825afad772f1d6c268d813026dad2e5303a4f5 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 21 Jul 2014 14:01:08 +0000 Subject: [PATCH] R600/SI: Use a custom encoding method for simm16 in SOPP branch instructions This allows us to explicitly define the type of fixup that is needed, so we can distinguish this from future fixup types. llvm-svn: 213527 --- .../Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp | 17 +++++++++++++ .../Target/R600/MCTargetDesc/AMDGPUFixupKinds.h | 28 +++++++++++++++++++++ .../Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h | 6 +++++ .../Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | 29 ++++++++++++++++------ llvm/lib/Target/R600/SIInstrInfo.td | 9 +++++++ llvm/lib/Target/R600/SIInstructions.td | 14 +++++------ 6 files changed, 89 insertions(+), 14 deletions(-) create mode 100644 llvm/lib/Target/R600/MCTargetDesc/AMDGPUFixupKinds.h diff --git a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp index 489cec7..f822871 100644 --- a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -9,9 +9,11 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/AMDGPUMCTargetDesc.h" +#include "MCTargetDesc/AMDGPUFixupKinds.h" #include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAssembler.h" +#include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/TargetRegistry.h" @@ -58,6 +60,8 @@ public: bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override { return true; } + + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; }; } //End anonymous namespace @@ -78,6 +82,19 @@ void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, *Dst = (Value - 4) / 4; } +const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo( + MCFixupKind Kind) const { + const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = { + // name offset bits flags + { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel } + }; + + if (Kind < FirstTargetFixupKind) + return MCAsmBackend::getFixupKindInfo(Kind); + + return Infos[Kind - FirstTargetFixupKind]; +} + //===----------------------------------------------------------------------===// // ELFAMDGPUAsmBackend class //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUFixupKinds.h b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUFixupKinds.h new file mode 100644 index 0000000..ef64b40 --- /dev/null +++ b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUFixupKinds.h @@ -0,0 +1,28 @@ +//===-- AMDGPUFixupKinds.h - AMDGPU Specific Fixup Entries ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_AMDGPUFIXUPKINDS_H +#define LLVM_AMDGPUFIXUPKINDS_H + +#include "llvm/MC/MCFixup.h" + +namespace llvm { +namespace AMDGPU { +enum Fixups { + /// 16-bit PC relative fixup for SOPP branch instructions. + fixup_si_sopp_br = FirstTargetFixupKind, + + // Marker + LastTargetFixupKind, + NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind +}; +} +} + +#endif // LLVM_AMDGPUFIXUPKINDS_H diff --git a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h index 6a5cd67..d5e432d 100644 --- a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h +++ b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h @@ -37,6 +37,12 @@ public: const MCSubtargetInfo &STI) const { return 0; } + + virtual unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + return 0; + } }; } // End namespace llvm diff --git a/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index ee02111..5e674d6 100644 --- a/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -15,6 +15,7 @@ #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUMCCodeEmitter.h" +#include "MCTargetDesc/AMDGPUFixupKinds.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCFixup.h" @@ -62,6 +63,12 @@ public: uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const override; + + /// \brief Use a fixup to encode the simm16 field for SOPP branch + /// instructions. + unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const override; }; } // End anonymous namespace @@ -169,20 +176,28 @@ void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, } } -uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, - const MCOperand &MO, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const { - if (MO.isReg()) - return MRI.getEncodingValue(MO.getReg()); +unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); if (MO.isExpr()) { const MCExpr *Expr = MO.getExpr(); - MCFixupKind Kind = MCFixupKind(FK_PCRel_4); + MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br; Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc())); return 0; } + return getMachineOpValue(MI, MO, Fixups, STI); +} + +uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, + const MCOperand &MO, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + if (MO.isReg()) + return MRI.getEncodingValue(MO.getReg()); + // Figure out the operand number, needed for isSrcOperand check unsigned OpNo = 0; for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) { diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index 774c9d1..7093db6 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -142,10 +142,19 @@ class SGPRImm : PatLeaf; +//===----------------------------------------------------------------------===// +// Custom Operands +//===----------------------------------------------------------------------===// + def FRAMEri32 : Operand { let MIOperandInfo = (ops i32:$ptr, i32imm:$index); } +def sopp_brtarget : Operand { + let EncoderMethod = "getSOPPBrEncoding"; + let OperandType = "OPERAND_PCREL"; +} + //===----------------------------------------------------------------------===// // Complex patterns //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index 4294243..7663b2e 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -378,42 +378,42 @@ def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", let isBranch = 1 in { def S_BRANCH : SOPP < - 0x00000002, (ins brtarget:$simm16), "S_BRANCH $simm16", + 0x00000002, (ins sopp_brtarget:$simm16), "S_BRANCH $simm16", [(br bb:$simm16)]> { let isBarrier = 1; } let DisableEncoding = "$scc" in { def S_CBRANCH_SCC0 : SOPP < - 0x00000004, (ins brtarget:$simm16, SCCReg:$scc), + 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc), "S_CBRANCH_SCC0 $simm16", [] >; def S_CBRANCH_SCC1 : SOPP < - 0x00000005, (ins brtarget:$simm16, SCCReg:$scc), + 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc), "S_CBRANCH_SCC1 $simm16", [] >; } // End DisableEncoding = "$scc" def S_CBRANCH_VCCZ : SOPP < - 0x00000006, (ins brtarget:$simm16, VCCReg:$vcc), + 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc), "S_CBRANCH_VCCZ $simm16", [] >; def S_CBRANCH_VCCNZ : SOPP < - 0x00000007, (ins brtarget:$simm16, VCCReg:$vcc), + 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc), "S_CBRANCH_VCCNZ $simm16", [] >; let DisableEncoding = "$exec" in { def S_CBRANCH_EXECZ : SOPP < - 0x00000008, (ins brtarget:$simm16, EXECReg:$exec), + 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec), "S_CBRANCH_EXECZ $simm16", [] >; def S_CBRANCH_EXECNZ : SOPP < - 0x00000009, (ins brtarget:$simm16, EXECReg:$exec), + 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec), "S_CBRANCH_EXECNZ $simm16", [] >; -- 2.7.4