From 01577df7793e949ed8d31cb18c931fbbe7ef00d0 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Tue, 16 Dec 2008 12:03:41 +0000 Subject: [PATCH] re PR target/37436 (arm-cross-g++. internal compiler error: in extract_insn, at recog.c:1990) PR target/37436 * arm.c (arm_legitimate_index): Only accept addresses that are in canonical form. * predicates.md (arm_reg_or_extendqisi_mem_op): New predicate. * arm.md (extendqihi2): Use arm_reg_or_extendqisi_mem_op predicate for operand1. (extendqisi2): Likewise. (arm_extendqisi, arm_extendqisi_v6): Use arm_extendqisi_mem_op predicate for operand1. From-SVN: r142778 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/arm/arm.c | 1 + gcc/config/arm/arm.md | 11 ++++++----- gcc/config/arm/predicates.md | 4 ++++ 4 files changed, 23 insertions(+), 5 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8fe6a69..c941cd2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2008-12-16 Richard Earnshaw + + PR target/37436 + * arm.c (arm_legitimate_index): Only accept addresses that are in + canonical form. + * predicates.md (arm_reg_or_extendqisi_mem_op): New predicate. + * arm.md (extendqihi2): Use arm_reg_or_extendqisi_mem_op predicate + for operand1. + (extendqisi2): Likewise. + (arm_extendqisi, arm_extendqisi_v6): Use arm_extendqisi_mem_op + predicate for operand1. + 2008-12-15 Adam Nemet * config/mips/mips.c (mips_output_conditional_branch): Assert that diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 497564a..46aa238 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -3844,6 +3844,7 @@ arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer, rtx xop1 = XEXP (x, 1); return ((arm_address_register_rtx_p (xop0, strict_p) + && GET_CODE(xop1) == CONST_INT && arm_legitimate_index_p (mode, xop1, outer, strict_p)) || (arm_address_register_rtx_p (xop1, strict_p) && arm_legitimate_index_p (mode, xop0, outer, strict_p))); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b60ba83..96e2f3b 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4299,7 +4299,7 @@ (define_expand "extendqihi2" [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "general_operand" "") + (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "") (const_int 24))) (set (match_operand:HI 0 "s_register_operand" "") (ashiftrt:SI (match_dup 2) @@ -4324,7 +4324,7 @@ (define_insn "*arm_extendqihi_insn" [(set (match_operand:HI 0 "s_register_operand" "=r") - (sign_extend:HI (match_operand:QI 1 "memory_operand" "Uq")))] + (sign_extend:HI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))] "TARGET_ARM && arm_arch4" "ldr%(sb%)\\t%0, %1" [(set_attr "type" "load_byte") @@ -4335,7 +4335,7 @@ (define_expand "extendqisi2" [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "general_operand" "") + (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "") (const_int 24))) (set (match_operand:SI 0 "s_register_operand" "") (ashiftrt:SI (match_dup 2) @@ -4367,7 +4367,7 @@ (define_insn "*arm_extendqisi" [(set (match_operand:SI 0 "s_register_operand" "=r") - (sign_extend:SI (match_operand:QI 1 "memory_operand" "Uq")))] + (sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))] "TARGET_ARM && arm_arch4 && !arm_arch6" "ldr%(sb%)\\t%0, %1" [(set_attr "type" "load_byte") @@ -4378,7 +4378,8 @@ (define_insn "*arm_extendqisi_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uq")))] + (sign_extend:SI + (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))] "TARGET_ARM && arm_arch6" "@ sxtb%?\\t%0, %1 diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 388790d..48e697f 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -234,6 +234,10 @@ (match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0)"))) +(define_special_predicate "arm_reg_or_extendqisi_mem_op" + (ior (match_operand 0 "arm_extendqisi_mem_op") + (match_operand 0 "s_register_operand"))) + (define_predicate "power_of_two_operand" (match_code "const_int") { -- 2.7.4