From 00eef4f7c384456e0df8f855b99eab384a213c23 Mon Sep 17 00:00:00 2001 From: Jun Ma Date: Fri, 10 Mar 2023 09:00:15 +0800 Subject: [PATCH] [SelectionDAG] Fix mismatched truncate when combine BUILD_VECTOR with EXTRACT_SUBVECTOR Just use correct type for truncation. Fixes PR59625 Differential Revision: https://reviews.llvm.org/D145757 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- llvm/test/CodeGen/WebAssembly/pr59625.ll | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/WebAssembly/pr59625.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 245be4a..4ab490d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -23525,7 +23525,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { if (NumElems == 1) { SDValue Src = V->getOperand(IdxVal); if (EltVT != Src.getValueType()) - Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), InVT, Src); + Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Src); return DAG.getBitcast(NVT, Src); } diff --git a/llvm/test/CodeGen/WebAssembly/pr59625.ll b/llvm/test/CodeGen/WebAssembly/pr59625.ll new file mode 100644 index 0000000..4c3d922 --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/pr59625.ll @@ -0,0 +1,18 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc < %s -mtriple=wasm32-- -mattr=+simd128 | FileCheck --check-prefix=CHECK %s +; RUN: llc < %s -mtriple=wasm64-- -mattr=+simd128 | FileCheck --check-prefix=CHECK %s + +define <1 x i16> @f(<1 x i16> %0) { +; CHECK-LABEL: f: +; CHECK: .functype f (v128) -> (v128) +; CHECK-NEXT: # %bb.0: # %BB +; CHECK-NEXT: v128.const 0, 0, 0, 0, 0, 0, 0, 0 +; CHECK-NEXT: # fallthrough-return +BB: + %B2 = srem <1 x i16> %0, %0 + br label %BB1 + +BB1: ; preds = %BB + %B = urem <1 x i16> %B2, + ret <1 x i16> %B +} -- 2.7.4