From 00b8a212ea2132fb68e42488317392346e169035 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Mon, 13 Feb 2023 17:17:46 +0100 Subject: [PATCH] i386: Relax extract location operand mode requirements [PR108516] MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Combine pass simplifies zero-extend of a zero-extract to: Trying 16 -> 6: 16: r86:QI#0=zero_extract(r87:HI,0x8,0x8) REG_DEAD r87:HI 6: r84:SI=zero_extend(r86:QI) REG_DEAD r86:QI Failed to match this instruction: (set (reg:SI 84 [ s.e2 ]) (zero_extract:SI (reg:HI 87) (const_int 8 [0x8]) (const_int 8 [0x8]))) which fails instruction recognision. The pattern is valid, since there is no requirement on the mode of the location operand. The patch relaxes location operand mode requirements of *extzv and *extv insn patterns to allow all supported integer modes. The patch also adds support for a related sign-extend from zero-extracted operand. 2023-02-13 Uroš Bizjak gcc/ChangeLog: PR target/108516 * config/i386/predicates.md (extr_register_operand): New special predicate. * config/i386/i386.md (*extv): Use extr_register_operand as operand 1 predicate. (*exzv): Ditto. (*extendqi_ext_1): New insn pattern. gcc/testsuite/ChangeLog: PR target/108516 * gcc.target/i386/pr108516-1.c: New test. * gcc.target/i386/pr108516-2.c: Ditto. --- gcc/config/i386/i386.md | 17 +++++++++++++++-- gcc/config/i386/predicates.md | 8 ++++++++ gcc/testsuite/gcc.target/i386/pr108516-1.c | 19 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr108516-2.c | 19 +++++++++++++++++++ 4 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr108516-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr108516-2.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index e62dd07..5a946be 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3159,7 +3159,7 @@ (define_insn "*extv" [(set (match_operand:SWI24 0 "register_operand" "=R") - (sign_extract:SWI24 (match_operand:SWI24 1 "register_operand" "Q") + (sign_extract:SWI24 (match_operand 1 "extr_register_operand" "Q") (const_int 8) (const_int 8)))] "" @@ -3202,7 +3202,7 @@ (define_insn "*extzv" [(set (match_operand:SWI248 0 "register_operand" "=R") - (zero_extract:SWI248 (match_operand:SWI248 1 "register_operand" "Q") + (zero_extract:SWI248 (match_operand 1 "extr_register_operand" "Q") (const_int 8) (const_int 8)))] "" @@ -4777,6 +4777,19 @@ (if_then_else (eq_attr "prefix_0f" "0") (const_string "0") (const_string "1")))]) + +(define_insn "*extendqi_ext_1" + [(set (match_operand:SWI24 0 "register_operand" "=R") + (sign_extend:SWI24 + (subreg:QI + (zero_extract:SWI248 + (match_operand:SWI248 1 "register_operand" "Q") + (const_int 8) + (const_int 8)) 0)))] + "" + "movs{b|x}\t{%h1, %0|%0, %h1}" + [(set_attr "type" "imovx") + (set_attr "mode" "")]) ;; Conversions between float and double. diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index ec1785c..cca64f0 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -92,6 +92,14 @@ (and (match_code "reg") (match_test "MASK_REGNO_P (REGNO (op))"))) +;; Match a DI, SI or HImode register operand for extract op. +(define_special_predicate "extr_register_operand" + (and (match_operand 0 "register_operand") + (ior (and (match_test "TARGET_64BIT") + (match_test "GET_MODE (op) == DImode")) + (match_test "GET_MODE (op) == SImode") + (match_test "GET_MODE (op) == HImode")))) + ;; Match a DI, SI, HI or QImode nonimmediate_operand. (define_special_predicate "int_nonimmediate_operand" (and (match_operand 0 "nonimmediate_operand") diff --git a/gcc/testsuite/gcc.target/i386/pr108516-1.c b/gcc/testsuite/gcc.target/i386/pr108516-1.c new file mode 100644 index 0000000..d5344ef --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr108516-1.c @@ -0,0 +1,19 @@ +/* PR target/108516 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -dp" } */ +/* { dg-additional-options "-mregparm=1" { target ia32 } } */ + +struct S +{ + unsigned char e1; + unsigned char e2; + unsigned char e3; +}; + +unsigned int +f2 (struct S s) +{ + return s.e2; +} + +/* { dg-final { scan-assembler-not "\\*zero_extend" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr108516-2.c b/gcc/testsuite/gcc.target/i386/pr108516-2.c new file mode 100644 index 0000000..3e709e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr108516-2.c @@ -0,0 +1,19 @@ +/* PR target/108516 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -dp" } */ +/* { dg-additional-options "-mregparm=1" { target ia32 } } */ + +struct S +{ + signed char e1; + signed char e2; + signed char e3; +}; + +int +f2 (struct S s) +{ + return s.e2; +} + +/* { dg-final { scan-assembler-not "\\*extzv" } } */ -- 2.7.4