From 00adc1e105734a2a3982191863cff482676cad7d Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 26 Jan 2016 21:39:25 +0000 Subject: [PATCH] [X86] Add support for zeroed shuffle elements to getShuffleScalarElt Enable handling of SM_SentinelZero shuffle elements to getShuffleScalarElt. Improves VZEXT_LOAD matches in EltsFromConsecutiveLoads. llvm-svn: 258865 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 8 ++++++-- llvm/test/CodeGen/X86/insertps-combine.ll | 20 ++++++++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index cb5a8b3..749e578 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -5135,16 +5135,20 @@ static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, // Recurse into target specific vector shuffles to find scalars. if (isTargetShuffle(Opcode)) { MVT ShufVT = V.getSimpleValueType(); + MVT ShufSVT = ShufVT.getVectorElementType(); int NumElems = (int)ShufVT.getVectorNumElements(); SmallVector ShuffleMask; bool IsUnary; - if (!getTargetShuffleMask(N, ShufVT, false, ShuffleMask, IsUnary)) + if (!getTargetShuffleMask(N, ShufVT, true, ShuffleMask, IsUnary)) return SDValue(); int Elt = ShuffleMask[Index]; + if (Elt == SM_SentinelZero) + return ShufSVT.isInteger() ? DAG.getConstant(0, SDLoc(N), ShufSVT) + : DAG.getConstantFP(+0.0, SDLoc(N), ShufSVT); if (Elt == SM_SentinelUndef) - return DAG.getUNDEF(ShufVT.getVectorElementType()); + return DAG.getUNDEF(ShufSVT); assert(0 <= Elt && Elt < (2*NumElems) && "Shuffle index out of range"); SDValue NewV = (Elt < NumElems) ? N->getOperand(0) : N->getOperand(1); diff --git a/llvm/test/CodeGen/X86/insertps-combine.ll b/llvm/test/CodeGen/X86/insertps-combine.ll index 54b5fe4..fa18ca6 100644 --- a/llvm/test/CodeGen/X86/insertps-combine.ll +++ b/llvm/test/CodeGen/X86/insertps-combine.ll @@ -130,6 +130,26 @@ define <4 x float> @insertps_undef_input1(<4 x float> %a0, <4 x float> %a1) { ret <4 x float> %res2 } +define <4 x float> @consecutive_load_insertps_04zz(float* %p) { +; SSE-LABEL: consecutive_load_insertps_04zz: +; SSE: # BB#0: +; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero +; SSE-NEXT: retq +; +; AVX-LABEL: consecutive_load_insertps_04zz: +; AVX: # BB#0: +; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero +; AVX-NEXT: retq + %p0 = getelementptr inbounds float, float* %p, i64 1 + %p1 = getelementptr inbounds float, float* %p, i64 2 + %s0 = load float, float* %p0 + %s1 = load float, float* %p1 + %v0 = insertelement <4 x float> undef, float %s0, i32 0 + %v1 = insertelement <4 x float> undef, float %s1, i32 0 + %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v0, <4 x float> %v1, i8 28) + ret <4 x float> %res +} + define float @extract_zero_insertps_z0z7(<4 x float> %a0, <4 x float> %a1) { ; SSE-LABEL: extract_zero_insertps_z0z7: ; SSE: # BB#0: -- 2.7.4