From 00926c30be083dae76d04c209751d03102bd7fed Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Wed, 28 Dec 2022 16:32:44 +0800 Subject: [PATCH] [RISCV] Fix typos in RISCVUsage.rst Fix typos `riscv-toolchai-convention` --> `riscv-toolchain-convention` Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D140717 --- llvm/docs/RISCVUsage.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index c5f947a..522988f 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -158,10 +158,10 @@ It is our intention to follow the naming conventions described in `riscv-non-isa The current vendor extensions supported are: ``XVentanaCondOps`` - LLVM implements `version 1.0.0 of the VTx-family custom instructions specification `_ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchai-convention document linked above. These instructions are only available for riscv64 at this time. + LLVM implements `version 1.0.0 of the VTx-family custom instructions specification `_ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time. ``XTHeadVdot`` - LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification `_ by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchai-convention document linked above. + LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification `_ by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above. Specification Documents -- 2.7.4