From 0069ac9e6eb2ad5793be473cdd98a89c9d017998 Mon Sep 17 00:00:00 2001 From: Jesse Natalie Date: Mon, 9 Jan 2023 16:46:14 -0800 Subject: [PATCH] dzn: Disable depth when the rasterizer is disabled due to no position output D3D considers the rasterizer enabled if there's a pixel shader *or* if depth is enabled, since you can do depth-only rendering. After parsing shaders, if we find that there was supposed to be a pixel shader, but we removed it because there was no output position, disable depth too. Also, store this info in the cache, since we might not even load the nir shaders if we'd seen this pipeline before. Fixes dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics Part-of: --- src/microsoft/vulkan/dzn_pipeline.c | 38 +++++++++++++++++++++++++++++++------ src/microsoft/vulkan/dzn_private.h | 2 ++ 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/src/microsoft/vulkan/dzn_pipeline.c b/src/microsoft/vulkan/dzn_pipeline.c index 404ee5e..b38dd06 100644 --- a/src/microsoft/vulkan/dzn_pipeline.c +++ b/src/microsoft/vulkan/dzn_pipeline.c @@ -531,7 +531,8 @@ dzn_pipeline_cache_add_dxil_shader(struct vk_pipeline_cache *cache, } struct dzn_cached_gfx_pipeline_header { - uint32_t stages; + uint32_t stages : 31; + uint32_t rast_disabled_from_missing_position : 1; uint32_t input_count; }; @@ -598,6 +599,8 @@ dzn_pipeline_cache_lookup_gfx_pipeline(struct dzn_graphics_pipeline *pipeline, offset += SHA1_DIGEST_LENGTH; } + pipeline->rast_disabled_from_missing_position = info->rast_disabled_from_missing_position; + *cache_hit = true; vk_pipeline_cache_object_unref(cache_obj); @@ -637,6 +640,7 @@ dzn_pipeline_cache_add_gfx_pipeline(struct dzn_graphics_pipeline *pipeline, info->input_count = vertex_input_count; info->stages = stages; + info->rast_disabled_from_missing_position = pipeline->rast_disabled_from_missing_position; offset = ALIGN_POT(offset + sizeof(*info), alignof(D3D12_INPUT_ELEMENT_DESC)); @@ -911,10 +915,6 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, /* Last step: translate NIR shaders into DXIL modules */ u_foreach_bit(stage, active_stage_mask) { - /* Cache hit, we can skip the compilation. */ - if (pipeline->templates.shaders[stage].bc) - continue; - gl_shader_stage prev_stage = util_last_bit(active_stage_mask & BITFIELD_MASK(stage)) - 1; uint32_t prev_stage_output_clip_size = 0; @@ -923,12 +923,20 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, * write the position. */ if (prev_stage == MESA_SHADER_NONE || - !(pipeline->templates.shaders[prev_stage].nir->info.outputs_written & VARYING_BIT_POS)) + !(pipeline->templates.shaders[prev_stage].nir->info.outputs_written & VARYING_BIT_POS)) { + pipeline->rast_disabled_from_missing_position = true; + /* Clear a cache hit if there was one. */ + pipeline->templates.shaders[stage].bc = NULL; continue; + } } else if (prev_stage != MESA_SHADER_NONE) { prev_stage_output_clip_size = pipeline->templates.shaders[prev_stage].nir->info.clip_distance_array_size; } + /* Cache hit, we can skip the compilation. */ + if (pipeline->templates.shaders[stage].bc) + continue; + D3D12_SHADER_BYTECODE *slot = dzn_pipeline_get_gfx_shader_slot(out, stage); @@ -1660,6 +1668,8 @@ dzn_graphics_pipeline_create(struct dzn_device *device, const VkAllocationCallbacks *pAllocator, VkPipeline *out) { + struct dzn_physical_device *pdev = + container_of(device->vk.physical, struct dzn_physical_device, vk); const VkPipelineRenderingCreateInfo *ri = (const VkPipelineRenderingCreateInfo *) vk_find_struct_const(pCreateInfo, PIPELINE_RENDERING_CREATE_INFO); VK_FROM_HANDLE(vk_pipeline_cache, pcache, cache); @@ -1796,6 +1806,22 @@ dzn_graphics_pipeline_create(struct dzn_device *device, if (ret != VK_SUCCESS) goto out; + /* If we have no position output from a pre-rasterizer stage, we need to make sure that + * depth is disabled, to fully disable the rasterizer. We can only know this after compiling + * or loading the shaders. + */ + if (pipeline->rast_disabled_from_missing_position) { + if (pdev->options14.IndependentFrontAndBackStencilRefMaskSupported) { + D3D12_DEPTH_STENCIL_DESC2 *ds = dzn_graphics_pipeline_get_desc(pipeline, pipeline->templates.stream_buf, ds); + if (ds) + ds->DepthEnable = ds->StencilEnable = false; + } else { + D3D12_DEPTH_STENCIL_DESC1 *ds = dzn_graphics_pipeline_get_desc(pipeline, pipeline->templates.stream_buf, ds); + if (ds) + ds->DepthEnable = ds->StencilEnable = false; + } + } + if (!pipeline->variants) { hres = ID3D12Device4_CreatePipelineState(device->dev, stream_desc, &IID_ID3D12PipelineState, diff --git a/src/microsoft/vulkan/dzn_private.h b/src/microsoft/vulkan/dzn_private.h index 6999d24..08d85c6 100644 --- a/src/microsoft/vulkan/dzn_private.h +++ b/src/microsoft/vulkan/dzn_private.h @@ -866,6 +866,8 @@ struct dzn_graphics_pipeline { float constants[4]; } blend; + bool rast_disabled_from_missing_position; + struct { uintptr_t stream_buf[MAX_GFX_PIPELINE_STATE_STREAM_SIZE / sizeof(uintptr_t)]; D3D12_PIPELINE_STATE_STREAM_DESC stream_desc; -- 2.7.4