Kyungmin Park [Fri, 9 Oct 2009 08:52:26 +0000 (17:52 +0900)]
s5pc110: Detect Limo Real at suspend by H1 group
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Fri, 9 Oct 2009 08:30:25 +0000 (17:30 +0900)]
s5pc110: Fix Limo Real detection
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Fri, 9 Oct 2009 08:30:12 +0000 (17:30 +0900)]
s5pc110: aquila: Setup power down status
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Fri, 9 Oct 2009 04:27:10 +0000 (13:27 +0900)]
s5pc110: aquila: Fix Limo Real board detection after suspend
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Thu, 8 Oct 2009 23:41:23 +0000 (08:41 +0900)]
s5pc110: aquila: Remove unnecessary check
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Thu, 8 Oct 2009 11:27:28 +0000 (20:27 +0900)]
s5pc110: aqulia: set AP_PS_HOLD high
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Thu, 8 Oct 2009 10:19:12 +0000 (19:19 +0900)]
s5pc110: use gpio style operation
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Thu, 8 Oct 2009 07:06:56 +0000 (16:06 +0900)]
s5pc110: Set high AP_PS_HOLD pin
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Thu, 8 Oct 2009 02:28:28 +0000 (11:28 +0900)]
s5pc110: aquila: Fix wrong display debug message
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Thu, 8 Oct 2009 02:20:31 +0000 (11:20 +0900)]
s5pc110: aquila: Register based sleep & PMIC LDO command support
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Wed, 7 Oct 2009 02:12:36 +0000 (11:12 +0900)]
s5pc110: sleep command support to test sleep
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Wed, 7 Oct 2009 00:47:18 +0000 (09:47 +0900)]
s5pc110: universal: Delete unnecessary 2k & 4k IPL binary
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Minkyu Kang [Wed, 7 Oct 2009 00:33:38 +0000 (09:33 +0900)]
s5pc1xx: universal: use the correct name
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Minkyu Kang [Tue, 6 Oct 2009 12:17:05 +0000 (21:17 +0900)]
s5pc110: mmc: code clean
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Minkyu Kang [Tue, 6 Oct 2009 12:11:43 +0000 (21:11 +0900)]
s5pc110: support the SD/MMC Controller
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Kyungmin Park [Tue, 6 Oct 2009 10:37:37 +0000 (19:37 +0900)]
Merge branch 'master' of git://git.denx.de/u-boot
Conflicts:
Makefile
onenand_ipl/onenand_ipl.h
onenand_ipl/onenand_read.c
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Tue, 6 Oct 2009 10:32:12 +0000 (19:32 +0900)]
s5pc110: Remove non-exist powerdown setting at Group H
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Tue, 6 Oct 2009 08:08:50 +0000 (17:08 +0900)]
s5pc110: aquila: Disable H group powerdown modes
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Jaehoon Chung [Tue, 6 Oct 2009 07:54:00 +0000 (16:54 +0900)]
s5pc110: aquila: set usbdown button (volumedown & camera)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Ben Warren [Mon, 5 Oct 2009 07:02:51 +0000 (00:02 -0700)]
Add information about return values of xxx_eth_register() in documentation
As discussed on mailing list, <0 indicates failure, >=0 indicates number
of interfaces found.
Also added blurb about private data
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Mike Frysinger [Wed, 9 Sep 2009 18:41:22 +0000 (14:41 -0400)]
document network driver framework
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Prafulla Wadaskar [Wed, 9 Sep 2009 10:29:19 +0000 (15:59 +0530)]
net: kirkwood_egiga.c: fixed build warning
if link up detection code is disabled through config option, it gives build warning.
This patch fixes the same
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Ben Warren [Mon, 5 Oct 2009 05:37:03 +0000 (22:37 -0700)]
Convert SMC91111 Ethernet driver to CONFIG_NET_MULTI API
All in-tree boards that use this controller have CONFIG_NET_MULTI
added
Also:
- changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111
- cleaned up line lengths
- modified all boards that override weak function in this driver
- modified all eeprom standalone apps to work with new driver
- updated blackfin standalone EEPROM app after testing
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Prafulla Wadaskar [Mon, 21 Sep 2009 14:58:18 +0000 (20:28 +0530)]
net: phy: mv88e61xx.c : fixed build warning
following build warning was observed
mv88e61xx.c: In function ‘mv88e61xx_busychk’:
mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules
This patch fixes the same
Patch tested for rd6281a board build
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
James Clough [Thu, 10 Sep 2009 07:11:50 +0000 (09:11 +0200)]
net: Fix problem with 405EZ ethernet interrupt
On 405EZ the RX-/TX-interrupts are coalesced into one IRQ bit in the
UIC. We need to acknowledge the RX-/TX-interrupts in the
SDR0_ICINTSTAT reg as well.
This problem was introduced with commit
d1631fe1 [ppc4xx: Consolidate PPC4xx UIC defines]
Signed-off-by: James Clough <james@rtetc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Mike Frysinger [Wed, 2 Sep 2009 08:18:55 +0000 (04:18 -0400)]
net: add random_port() prototype
The random_port() is meant to be used by other net code, but without a
prototype, we get fun warnings like:
dns.c: In function 'DnsSend':
dns.c:89: warning: implicit declaration of function 'random_port'
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Wolfgang Denk [Sat, 3 Oct 2009 21:40:35 +0000 (23:40 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Wolfgang Denk [Sat, 3 Oct 2009 21:38:55 +0000 (23:38 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-blackfin
Matthias Fuchs [Wed, 30 Sep 2009 09:55:04 +0000 (11:55 +0200)]
ppc4xx: Add SDRAM detection for PMC440 boards
This patch adds support to detect the amount of DDR2 SDRAM
on PMC440 modules. Detection is done by probing through
a list of available and supported hardware configurations
from 1GByte down to 256MB.
The static TLB entry is replaced by dynamically created entries.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Mon, 28 Sep 2009 15:33:45 +0000 (17:33 +0200)]
ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.
Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.
Tested on Kilauea (no ECC) and Katmai (with and without ECC).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
Felix Radensky [Sun, 27 Sep 2009 21:56:12 +0000 (23:56 +0200)]
ppc4xx: Reorganize DDR2 ECC handling
Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Wolfgang Denk [Wed, 30 Sep 2009 21:39:36 +0000 (23:39 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Wolfgang Denk [Wed, 30 Sep 2009 21:34:36 +0000 (23:34 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
Wolfgang Denk [Wed, 30 Sep 2009 21:28:18 +0000 (23:28 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-ubi
Wolfgang Denk [Wed, 30 Sep 2009 21:26:59 +0000 (23:26 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
Wolfgang Denk [Wed, 30 Sep 2009 21:24:10 +0000 (23:24 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c
Wolfgang Denk [Wed, 30 Sep 2009 21:22:46 +0000 (23:22 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
Wolfgang Denk [Wed, 30 Sep 2009 21:16:49 +0000 (23:16 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-fdt
Mike Frysinger [Wed, 30 Sep 2009 07:09:16 +0000 (03:09 -0400)]
Blackfin: update default console= settings
The Linux kernel has changed the way it numbers serial ports, so update
the default command line to match it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger [Mon, 21 Sep 2009 22:04:49 +0000 (18:04 -0400)]
Blackfin: bf533-ezkit: update env location
The u-boot image has outgrown the current space and overflowed into the
env sector. So move the env to the next available sector (we've already
allocated the first few sectors anyways for u-boot).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Kumar Gala [Wed, 30 Sep 2009 13:39:44 +0000 (08:39 -0500)]
ppc/85xx: get_law_entry isn't used in CONFIG_NAND_SPL
Don't include get_law_entry as part of the NAND_SPL build since the
code isnt used.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Wed, 23 Sep 2009 07:20:39 +0000 (15:20 +0800)]
Add README.mpc8536ds
Add boot from NAND/eSDHC/eSPI description
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Wed, 23 Sep 2009 07:20:38 +0000 (15:20 +0800)]
On-chip ROM boot: MPC8536DS support
The MPC8536E is capable of booting from the on-chip ROM - boot from
eSDHC and boot from eSPI. When power on, the porcessor excutes the
ROM code to initialize the eSPI/eSDHC controller, and loads the mian
U-Boot image from the memory device that interfaced to the controller,
such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
L2SRAM, then boot from it.
The memory device should contain a specific data structure with control
word and config word at the fixed address. The config word direct the
process how to config the memory device, and the control word direct
the processor where to find the image on the memory device, or where
copy the main image to. The user can use any method to store the data
structure to the memory device, only if store it on the assigned address.
The on-chip ROM code will map the whole 4GB address space by setting
entry0 in the TLB1, so the main image need to switch to Address space 1
to disable this mapping and map the address space again.
This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Wed, 23 Sep 2009 07:20:37 +0000 (15:20 +0800)]
NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.
This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Wed, 23 Sep 2009 07:19:32 +0000 (15:19 +0800)]
mpc8536: fix board config file line length
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Fri, 25 Sep 2009 15:14:11 +0000 (11:14 -0400)]
sbc8548: reclaim wasted sector in boot flash
By nature of being based off the MPC8548CDS board, this
board inherited an ENV_SIZE setting of 256k. But since
it has a smaller flash device (8MB soldered on), it has
a native sector size of 128k, and hence the ENV_SIZE was
causing 2 sectors to be used for the environment.
By removing the unused sector, we can push TEXT_BASE up
closer to the end of address space and reclaim that
sector for any other application. This also fixes the
mismatch between TEXT_BASE and MONITOR_LEN reported by
Kumar earlier.
Since this board also supports the ability to boot off
the 64MB SODIMM flash, this change is forward looking
with that in mind; i.e. the settings for MONITOR_LEN
and ENV_SIZE will work when the 512k sectors of the
SODIMM flash are used for alternate boot in the future.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kyungmin Park [Wed, 30 Sep 2009 10:54:06 +0000 (19:54 +0900)]
s5pc110: aquila: Apply Power Down mode values
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Wed, 30 Sep 2009 08:34:25 +0000 (17:34 +0900)]
s5pc110: Detect TA or USB
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Wed, 30 Sep 2009 04:42:15 +0000 (13:42 +0900)]
s5pc110: aquila: Set power down mode registers
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Wed, 30 Sep 2009 02:02:36 +0000 (11:02 +0900)]
s5pc110: Fix wrong GPIO offsets
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kumar Gala [Tue, 29 Sep 2009 02:38:00 +0000 (21:38 -0500)]
ppc/85xx: Clean up immap_85xx.h
* Converted all white space to tabs
* Converted all types to u8/u16/u32
* Reduce lines to fit in 80 columns
* Renamed MPC85xx_{Q,B}MAN -> FSL_CORENET_{Q,B}MAN
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kyungmin Park [Tue, 29 Sep 2009 01:20:26 +0000 (10:20 +0900)]
s5pc110: Handle revision fancy more
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Kyungmin Park [Tue, 29 Sep 2009 00:59:16 +0000 (09:59 +0900)]
s5pc110: aquila: Can configure EPLL 50MHz
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Scott Wood [Mon, 28 Sep 2009 21:33:18 +0000 (16:33 -0500)]
NAND: davinci: Fix warnings when 4-bit ECC not used
I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Kyungmin Park [Tue, 22 Sep 2009 00:05:00 +0000 (09:05 +0900)]
Refactor OneNAND IPL code
Refactoring the OneNAND IPL code
and some minor fixed:
- Remove unnecessary header file
- Fix wrong access at read interrupt
- The recent OneNAND has 4KiB pagesize
Also Board can override OneNAND IPL image
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Shinya Kuribayashi [Sat, 12 Sep 2009 09:01:40 +0000 (18:01 +0900)]
MIPS: VCT: Remove read_spareram reference
The commit
ecad289fc6bd9d89ef4d5093cc7b6fd712fd0d29 (OneNAND: Remove
unused read_spareram and add unlock_all as kernel does) forgot to remove
a local reference to read_spareram in board/micronas/vct/ebi_onenand.c,
which causes the following build failure when configured with OneNAND:
ebi_onenand.c: In function 'onenand_board_init':
ebi_onenand.c:196: error: 'struct onenand_chip' has no member named 'read_spareram'
make[1]: *** [ebi_onenand.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [board/micronas/vct/libvct.a] Error 2
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Simon Kagstrom [Fri, 25 Sep 2009 12:05:57 +0000 (14:05 +0200)]
ubifs: Correct dereferencing of files-after-symlinks
Files in directories which are symlinked to were not dereferenced
correctly in last commit. E.g., with a symlink
/boot/lnk -> /boot/real_dir
loading
/boot/lnk/uImage
will fail. This patch fixes that by simply seeing to it that the target
base directory has a slash after it.
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Kyungmin Park [Mon, 28 Sep 2009 10:53:52 +0000 (19:53 +0900)]
s5pc110: aquila: Set XCLKOUT as 20MHz
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Stefan Roese [Thu, 24 Sep 2009 12:10:30 +0000 (14:10 +0200)]
ppc4xx: Remove mtsdram0() marcos and use common mtsdram() instead
Additionally some whitespace coding style fixes.
Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Thu, 24 Sep 2009 11:59:57 +0000 (13:59 +0200)]
ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).
Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Thu, 24 Sep 2009 07:55:50 +0000 (09:55 +0200)]
ppc4xx: Convert PPC4xx UIC defines from lower case to upper case
The latest PPC4xx register cleanup patch missed the UIC defines.
This patch now changes lower case UIC defines to upper case.
Signed-off-by: Stefan Roese <sr@denx.de>
Joakim Tjernlund [Tue, 22 Sep 2009 11:40:44 +0000 (13:40 +0200)]
fsl_i2c: Do not generate STOP after read.
__i2c_read always ends with a STOP condition thereby releasing
the bus. It is cleaner to do the STOP magic in i2c_read(), like
i2c_write() does. This may also help future multimaster systems which
wants to hold on to the bus until all transactions are finished.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Joakim Tjernlund [Thu, 17 Sep 2009 09:07:17 +0000 (11:07 +0200)]
fsl_i2c: Impl. AN2919, rev 5 to calculate FDR/DFSR
The latest AN2919 has changed the way FDR/DFSR should be calculated.
Update the driver according to spec. However, Condition 2
is not accounted for as it is not clear how to do so.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Wolfgang Grandegger <wg@grandegger.com>
Joakim Tjernlund [Thu, 17 Sep 2009 09:07:16 +0000 (11:07 +0200)]
fsl_i2c: Add CONFIG_FSL_I2C_CUSTOM_{DFSR/FDR}
Some boards need a higher DFSR value than the spec currently
recommends so give these boards the means to define there own.
For completeness, add CONFIG_FSL_I2C_CUSTOM_FDR too.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Joakim Tjernlund [Thu, 17 Sep 2009 09:07:15 +0000 (11:07 +0200)]
fsl_i2c: Wait for STOP condition to propagate
After issuing a STOP one must wait until the STOP has completed
on the bus before doing something new to the controller.
Also add an extra read of SR as the manual mentions doing that
is a good idea.
Remove surplus write of CR just before a write, isn't required and
could potentially disturb the I2C bus.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Kim Phillips [Fri, 25 Sep 2009 23:19:44 +0000 (18:19 -0500)]
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields
some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.
Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS_<registername>_<bitfield> assignments in the board
config file.
also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.
also start to use i/o accessors.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Paul Gortmaker [Mon, 21 Sep 2009 21:44:51 +0000 (17:44 -0400)]
sbc8349: tidy up Makefile to use new configuration script.
Commit
804d83a5 allows us to move all the configuration
variation tweaks out of the top level Makefile and down
into the board config header. This takes advantage of
that for the sbc8349 board.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov [Wed, 16 Sep 2009 19:22:08 +0000 (23:22 +0400)]
mpc83xx: mpc8360emds: Add QE USB device tree fixups
With this patch we can change QE USB mode without need to hand-edit
the device tree.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov [Wed, 16 Sep 2009 19:21:59 +0000 (23:21 +0400)]
mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUs
This patch fixes various ethernet issues with gigabit links handling
in U-Boot. The workarounds originally implemented by Kim Phillips for
Linux kernel.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov [Wed, 16 Sep 2009 19:21:57 +0000 (23:21 +0400)]
mpc83xx: mpc8360emds: Don't use LBC SDRAM when DDR is available
Since commit
5c2ff323a94e27e481f70c44838d43fcd844dd46 ("mpc8360emds:
rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux.
Though, it appears that QE Ethernet in Gigabit mode can't transmit
large packets when it tries to work with a data in LBC SDRAM (memtest
didn't discover any issues, is LBC SDRAM just too slow?).
With this patch we can still use the board without DDR memory, but
if DDR is available, we don't use LBC SDRAM.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov [Wed, 16 Sep 2009 19:21:55 +0000 (23:21 +0400)]
net: uec: Fix uccf.h and uec.h headers to include headers they depend on
Headers should include headers containing prototypes and defines they
depend on, don't assume that they're included by somebody else.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov [Wed, 16 Sep 2009 19:21:53 +0000 (23:21 +0400)]
net: uec_phy: Implement TXID and RXID RGMII modes for Marvell PHYs
This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Wolfgang Denk [Fri, 25 Sep 2009 12:16:00 +0000 (14:16 +0200)]
mpc5121ads: fix breakage introduced when reordering elpida_mddrc_config[]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Ken MacLeod [Fri, 11 Sep 2009 20:16:18 +0000 (15:16 -0500)]
cmd_fdt.c: fix parse of byte streams and strings
Commit
4abd844d8e extended the fdt command parser to handle property
strings which are split across multiple arguments but it was broken for
byte streams and strings.
Byte stream parsing:
* Fixes where it would terminate early or go into an endless loop.
* Fixes a 0x00 being inserted into the data if there is a space after
'[' or a separate argument.
* Fixes dereferencing the argument pointer after the last argument.
* Checks for bad characters.
String parsing:
* Treat multiple arguments as a string list. This fixes an issue where
only the last argument was stored.
Signed-off-by: Ken MacLeod <ken@bitsko.slc.ut.us>
Heiko Schocher [Wed, 23 Sep 2009 05:56:08 +0000 (07:56 +0200)]
mucmc52, uc101: delete ata@3a00 node, if no CF card is detected
U-Boot can detect if an IDE device is present or not.
If not, and this new config option is activated, U-Boot
removes the ATA node from the DTS before booting Linux,
so the Linux IDE driver does not probe the device and
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.
Signed-off-by: Heiko Schocher <hs@denx.de>
Heiko Schocher [Wed, 23 Sep 2009 05:56:04 +0000 (07:56 +0200)]
mpc5200, mucmc52, uc101: config cleanup
- As these boards are similiar, collect common config options
in manroland/common.h and manroland/mpc52xx-common.h
for mpc5200 specific common options for this manufacturer.
- add OF support
- update default environment
Signed-off-by: Heiko Schocher <hs@denx.de>
Minor edit of commit message.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk [Thu, 24 Sep 2009 22:57:49 +0000 (00:57 +0200)]
Fix "ppc/85xx: Clean up use of LAWAR defines" breakage
Commit
002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_
defines were only enabled for the 83xx platform, but they are also
needed on MPC512x system. Enabling these for E300 systems seems thus
more appropriate.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Martha M Stan [Mon, 21 Sep 2009 18:08:00 +0000 (14:08 -0400)]
Add Elpida Memory Configuration to mpc5121ads Boards
Signed-off-by: Martha M Stan <mmarx@silicontkx.com>
Minor coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Martha M Stan [Mon, 21 Sep 2009 18:07:14 +0000 (14:07 -0400)]
mpc512x: Streamlined fixed_sdram() init sequence.
Signed-off-by: Martha M Stan <mmarx@silicontkx.com>
Minor cleanup:
Re-ordered default_mddrc_config[] to have matching indices.
This allows to use the same index "N" for source and target fields;
before, we had code like this
out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]);
which always looked like a copy & paste error because 2 != 3.
Also, use NULL when meaning a null pointer.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk [Thu, 24 Sep 2009 21:40:25 +0000 (23:40 +0200)]
Merge branch 'master' of /home/wd/git/u-boot/custodians
Kumar Gala [Thu, 19 Mar 2009 07:46:19 +0000 (02:46 -0500)]
ppc/p4080: Determine various chip frequencies on CoreNet platforms
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms. Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks. We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 17 Sep 2009 06:52:37 +0000 (01:52 -0500)]
ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms
the core not longer controls the enabling of the timebase. We now need
to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 19 Mar 2009 07:39:17 +0000 (02:39 -0500)]
ppc/p4080: Add various p4080 related defines (and p4040)
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 17 Sep 2009 06:44:39 +0000 (01:44 -0500)]
ppc/p4080: CoreNet platfrom style secondary core release
The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style. Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 17 Sep 2009 06:44:00 +0000 (01:44 -0500)]
ppc/p4080: CoreNet platfrom style CCSRBAR setting
On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Kumar Gala [Thu, 19 Mar 2009 07:32:23 +0000 (02:32 -0500)]
ppc/p4080: Add support for CoreNet style platform LAWs
On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address. Also, the target IDs
on CoreNet platforms have been completely re-assigned.
Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet style boot release code since it will need
to determine what the target ID should be set to for boot window
translation.
Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use
it elsewhere.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 16 Sep 2009 14:43:12 +0000 (09:43 -0500)]
ppc/p4080: Add p4080 platform immap definitions
The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform. We reuse the 85xx immap and just add new definitions for
local access and global utils. The global utils is now broken into
global utils, clocking and run control/power management.
The offsets from CCSR for a number of blocks have also changed. We
introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of
platform from the new p4080 platform. We don't use QoirQ as there are
products (like p2020) that are PQ3 based platforms but have the QoirQ
name.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 22 Sep 2009 20:45:44 +0000 (15:45 -0500)]
ppc/85xx: Fix enabling of L2 cache
We need to flash invalidate the locks in addition to the cache
before we enable.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Vivek Mahajan [Tue, 22 Sep 2009 07:18:27 +0000 (12:48 +0530)]
85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ
The code assumed names where just numbers and always prefixed 'mpc'.
However newer QorIQ don't follow the mpc naming scheme.
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Tue, 22 Sep 2009 06:53:21 +0000 (14:53 +0800)]
ppc/85xx: add cpu init config file for boot from NAND
When boot from NAND, the NAND flash must be connected to br/or0.
Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to
it.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Tue, 22 Sep 2009 06:53:34 +0000 (14:53 +0800)]
immap_85xx: add porpllsr's plat ratio definition
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Tue, 22 Sep 2009 06:53:10 +0000 (14:53 +0800)]
ppc/85xx: add ld script file for boot from NAND
The first stage 4K image uses a seperate ld script file to
generate 4K image. This patch moves it to the cpu/mpc85xx/*
to make it avaliable for 85xx platform.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Peter Tyser [Tue, 22 Sep 2009 04:09:28 +0000 (23:09 -0500)]
mpc8610hpcd: Use common 86xx fdt fixup code
Using the common 86xx fdt fixups removes some board-specific code and
should make the mpc8610hpcd easier to maintain in the long run.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 21:19:17 +0000 (17:19 -0400)]
sbc85x0: tidy up Makefile to use new configuration script.
Commit
804d83a5 allows us to move all the configuration
variation tweaks out of the top level Makefile and down
into the boards config header. This takes advantage of
that for the sbc8540/sbc8560 boards.
There were a couple of cheezy comments pointing at incorrect
files, or files that don't exist, so I've cleaned those up too.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 00:36:06 +0000 (20:36 -0400)]
sbc8548: allow enabling PCI via a make config option
Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CONFIG_SYS_NS16550_CLK too, which was
not real user friendly,
This adds the typical PCI and clock speed make targets to the
toplevel Makefile in accordance with what is being done with
other boards (i.e. using the "-t" to mkconfig).
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 00:36:05 +0000 (20:36 -0400)]
sbc8548: update PCI/PCI-e support code
The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile. This re-syncs it to match
the latest codebase and makes use of the new shared PCI functions
to reduce board duplication.
It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.
Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 00:36:01 +0000 (20:36 -0400)]
fsl_pci: create a SET_STD_PCI_INFO() helper wrapper
Recycle the recently added PCI-e wrapper used to reduce board
duplication of code by creating a similar version for plain PCI.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 00:36:04 +0000 (20:36 -0400)]
sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 00:36:03 +0000 (20:36 -0400)]
sbc8548: use I/O accessors
Sweep throught the board specific file and replace the various
register proddings with the equivalent I/O accessors.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 00:36:02 +0000 (20:36 -0400)]
sbc8548: remove eTSEC3/4 voltage hack
With only eTSEC1 and 2 being brought out to RJ-45 connectors, we
aren't interested in the eTSEC3/4 voltage hack on this board
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>