Fabian Bieler [Sat, 20 Apr 2013 17:40:11 +0000 (19:40 +0200)]
mesa/st: Don't copy propagate from swizzles.
Do not propagate a copy if source and destination are identical.
Otherwise code like
MOV TEMP[0].xyzw, TEMP[0].wzyx
MOV TEMP[1].xyzw, TEMP[0].xyzw
is changed to
MOV TEMP[0].xyzw, TEMP[0].wzyx
MOV TEMP[1].xyzw, TEMP[0].wzyx
This fixes Piglit test shaders/glsl-copy-propagation-self-2 for gallium drivers.
NOTE: This is a candidate for the stable branches.
Signed-off-by: Fabian Bieler <fabianbieler@fastmail.fm>
Reviewed-by: Brian Paul <brianp@vmware.com>
Eric Anholt [Tue, 7 May 2013 03:44:21 +0000 (20:44 -0700)]
i965: Fix hangs on HSW since the gen6 blorp fix.
The constant packets for gen6 are too small for gen7, and while IVB seems
happy with them HSW blows up. Fix it by emitting the correct packets on
gen7, for all stages.
v2: Include the packets instead of just skipping them.
NOTE: This is a candidate for the stable branches.
Reviewed-and-tested-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chad Versace [Mon, 6 May 2013 14:41:11 +0000 (07:41 -0700)]
egl/android: Fix error condition for EGL_ANDROID_image_native_buffer
Emit EGL_BAD_CONTEXT if the user passes a context to
eglCreateImageKHR(type=EGL_ANDROID_image_native_buffer).
From the EGL_ANDROID_image_native_buffer spec:
* If <target> is EGL_NATIVE_BUFFER_ANDROID and <ctx> is not
EGL_NO_CONTEXT, the error EGL_BAD_CONTEXT is generated.
Note: This is a candidate for the stable branches.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Stéphane Marchesin [Sat, 4 May 2013 21:06:12 +0000 (14:06 -0700)]
i915: Use Y tiling for textures
This basically reverts commit
2acc7193743199701f8f6d1877a59ece0ec4fa5b.
With the previous change, we're not batchbuffer limited any
longer. So we actually start seeing a performance difference
between X and Y tiling. X tiling is funny because it is
faster for screen-aligned quads but slower in games. So let's
use Y tiling which is 10% faster overall.
Stéphane Marchesin [Sun, 5 May 2013 01:59:35 +0000 (18:59 -0700)]
i915g: Optimize batchbuffer sizes
Now that we don't throttle at every batchbuffer, we can shrink
the size of batchbuffers to achieve early flushing. This gives
a significant speed boost in a lot of games (on the order of
20%).
Stéphane Marchesin [Sun, 11 Nov 2012 10:10:29 +0000 (02:10 -0800)]
i915g: Add more PIPE_CAP_* support
Chia-I Wu [Wed, 8 May 2013 03:32:22 +0000 (11:32 +0800)]
ilo: remove our own type inference
tgsi_opcode_infer_{src,dst}_type() works just fine.
Chia-I Wu [Wed, 8 May 2013 03:07:27 +0000 (11:07 +0800)]
ilo: use tgsi_util_get_texture_coord_dim()
And remove toy_tgsi_get_texture_coord_dim().
Chia-I Wu [Sat, 4 May 2013 10:06:39 +0000 (18:06 +0800)]
tgsi: fix operand type of TGSI_OPCODE_NOT
It should be TGSI_TYPE_UNSIGNED, not TGSI_TYPE_FLOAT.
Fixed also gallivm not_emit_cpu() to use uint build context.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Chia-I Wu [Sat, 4 May 2013 09:54:16 +0000 (17:54 +0800)]
tgsi: refactor tgsi_opcode_infer_src_type()
Call tgsi_opcode_infer_type() from tgsi_opcode_infer_src_type().
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Chia-I Wu [Sat, 4 May 2013 05:27:59 +0000 (13:27 +0800)]
tgsi: refactor tgsi_opcode_infer_dst_type()
Move the body of tgsi_opcode_infer_dst_type() to a new helper function,
tgsi_opcode_infer_type(), and call the helper function from
tgsi_opcode_infer_dst_type(). The diff looks complicated simply because the
code is moved around.
A following commit will make tgsi_opcode_infer_src_type() call
tgsi_opcode_infer_type().
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Chia-I Wu [Sat, 4 May 2013 01:44:39 +0000 (09:44 +0800)]
tgsi: reorder opcodes in opcode type inference
Reorder opcodes by their assigned numbers. This makes it easier to see the
differences between tgsi_opcode_infer_src_type() and
tgsi_opcode_infer_dst_type().
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Chia-I Wu [Tue, 7 May 2013 06:50:02 +0000 (14:50 +0800)]
tgsi: clean up exec_tex()
Make use of tgsi_util_get_texture_coord_dim() to replace the big switch table.
There is a subtle difference with this change. When TXP is used with an array
texture, the layer is now also projected. This behavior matches the TGSI doc.
Since GLSL does not allow TXP on an array texture, I am not sure which
behavior is correct or preferred.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Chia-I Wu [Tue, 7 May 2013 07:32:35 +0000 (15:32 +0800)]
tgsi: add tgsi_util_get_texture_coord_dim()
This util function returns the dimension of the texture coordinates for a
texture target, and the location of the shadow reference value.
For example, when the texture target is TGSI_TEXTURE_SHADOW2D, the dimension
of the texture coordinates is 2, and the location of the ref value is 2
(that is, the Z channel).
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Bryan Cain [Tue, 7 May 2013 21:57:17 +0000 (16:57 -0500)]
nv50: initialize kick_notify callback in nv50_create
Fixes infinite loop on startup in Portal and Left 4 Dead 2.
NOTE: This is a candidate for the 9.0 and 9.1 branches.
Eric Anholt [Mon, 6 May 2013 21:14:39 +0000 (14:14 -0700)]
i965: Use Y-tiled blits to untile for cached mappings of miptrees.
Fixes a regression in firefox's unaccelerated compositing path for WebGL
with the introduction of Y tiling.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64213
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Mon, 6 May 2013 21:12:56 +0000 (14:12 -0700)]
i965: Add support for Y-tiled blits on gen6+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Mon, 6 May 2013 22:24:12 +0000 (15:24 -0700)]
i965: Count occlusion query samples for CopyPixels using the 2D engine.
We accidentally "fixed" the piglit test for this when introducing Y
tiling, since this path stopped being executed. In reenabling this path
for Y tiling, we ended up regressing it again, so just fix it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59439
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Robert Bragg [Fri, 10 Feb 2012 16:59:31 +0000 (16:59 +0000)]
egl/wayland: Implement EGL_EXT_swap_buffers_with_damage
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Robert Bragg [Thu, 25 Apr 2013 12:41:42 +0000 (13:41 +0100)]
egl: Add extension infrastructure for EGL_EXT_swap_buffers_with_damage
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Robert Bragg [Thu, 25 Apr 2013 12:31:33 +0000 (13:31 +0100)]
egl: Update to revision 21254 of eglext.h
This pulls in EGL_EXT_swap_buffers_with_damage.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Roland Scheidegger [Fri, 3 May 2013 21:32:23 +0000 (23:32 +0200)]
gallium: more tgsi documentation updates
Adds the remaining integer opcodes, and some opcodes are moved to more
appropriate places, along with getting rid of the (already nearly empty)
ps_2_x section. Though the CAP bits for some of these are still a bit in
the air so the documentation isn't quite as watertight as is desirable.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Vinson Lee [Sun, 5 May 2013 19:51:42 +0000 (12:51 -0700)]
ilo: Add missing break statement in aos_tex TGSI_OPCODE_TEX2 case.
Fixes "Missing break in switch" defect reported by Coverity.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Vadim Girlin [Sun, 5 May 2013 02:03:14 +0000 (06:03 +0400)]
r600g/sb: optimize some cases for CNDxx instructions
We can replace CNDxx with MOV (and possibly eliminate after
propagation) in following cases:
If src1 is equal to src2 in CNDxx instruction then the result doesn't
depend on condition and we can replace the instruction with
"MOV dst, src1".
If src0 is const then we can evaluate the condition at compile time and
also replace it with MOV.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Sat, 4 May 2013 18:05:43 +0000 (22:05 +0400)]
r600g/sb: fix memory leaks
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Sun, 5 May 2013 02:01:20 +0000 (06:01 +0400)]
r600g/sb: fix kcache handling on r6xx
Use the same limit for kcache constants in alu group on r6xx as on other
chips (two const pairs). Relaxing this will require additional checks to
make sure that all 4 consts in the group come from 2 kcache sets (clause
limit), probably without noticeable improvements of shader performance.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Eric Anholt [Mon, 22 Apr 2013 18:18:08 +0000 (11:18 -0700)]
intel: Remove renderbuffer delete setup from texture wrapping.
This is already set by intel_new_renderbuffer().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Mon, 22 Apr 2013 18:04:21 +0000 (11:04 -0700)]
mesa: Make Mesa core set up wrapped texture renderbuffer state.
Everyone was doing effectively the same thing, except for some funky code
reuse in Intel, and swrast mistakenly recomputing _BaseFormat instead of
using the texture's _BaseFormat. swrast's sRGB handling is left in place,
though it should be done by using _mesa_get_render_format() at render time
instead (as-is, it will miss updates to GL_FRAMEBUFFER_SRGB).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Mon, 22 Apr 2013 18:07:59 +0000 (11:07 -0700)]
intel: Simplify renderbuffer-for-texture width setup.
We're looking for the logical width of our level, which is what
image->Width2/Height2 is. The previous code relied on MSAA textures being
only level 0.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Mon, 22 Apr 2013 17:38:41 +0000 (10:38 -0700)]
mesa: Make core Mesa allocate the texture renderbuffer wrapper.
Every driver did the same thing.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 30 Apr 2013 18:15:05 +0000 (11:15 -0700)]
i965: Use brw_blorp_blit_miptrees() for CopyTexSubImage().
Now that depth resolves are handled there, we don't need to make the
temporary renderbuffer.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 30 Apr 2013 17:48:09 +0000 (10:48 -0700)]
i965: Move blorp resolve setup into brw_blorp_blit_miptrees().
There was some comment about trying to avoid marking resolves in
updownsample, but if the downsample is never actually rendered to, then
the required resolve tracked in the downsample will never be executed, so
who cares?
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tom Stellard [Mon, 6 May 2013 16:58:56 +0000 (09:58 -0700)]
gallivm: Fix build for LLVM < 3.3
The C API versions of the LLVM multithreaded functions were added in
LLVM 3.3.
Tom Stellard [Fri, 3 May 2013 20:10:29 +0000 (13:10 -0700)]
r600g/llvm: Parse config values in register / value pairs
Rather than relying on a predetermined order for the config values.
Tom Stellard [Fri, 3 May 2013 18:38:50 +0000 (11:38 -0700)]
r600g/llvm: Don't feed LLVM output through r600_bytecode_build()
The LLVM backend emits raw ISA now, so we can just its output
unmodified.
Tom Stellard [Fri, 3 May 2013 18:15:55 +0000 (11:15 -0700)]
r600g/llvm: Don't emit CALL_FS for vertex shaders
The LLVM backend takes care of this now.
Matt Turner [Thu, 11 Apr 2013 22:49:32 +0000 (15:49 -0700)]
i965: Lower bitfieldInsert.
v2: Only lower bitfieldInsert to BFM+BFI (and don't lower
bitfieldExtract at all) since three-source instructions are now
usable in the vertex shader.
v3: Lower bitfield_insert in the same pass with everything else, since
it doesn't produce any instructions to be lowered (the other two
lowering passes that were in a previous iteration of this series
emitted subtractions which needed to be lowered).
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
Matt Turner [Thu, 18 Apr 2013 01:57:58 +0000 (18:57 -0700)]
i965/vs: Add support for bit instructions.
v2: Rebase on LRP addition.
Use fix_3src_operand() when emitting BFE and BFI2.
Add BFE and BFI2 to is_3src_inst check in
brw_vec4_copy_propagation.cpp.
Subtract result of FBH from 31 (unless an error) to convert
MSB counts to LSB counts
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Wed, 10 Apr 2013 02:22:34 +0000 (19:22 -0700)]
i965/fs: Add support for bit instructions.
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.
v2: Subtract result of FBH from 31 (unless an error) to convert
MSB counts to LSB counts.
v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref
channel_expressions) from appearing multiple times in the IR.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
Matt Turner [Wed, 10 Apr 2013 00:56:19 +0000 (17:56 -0700)]
i965: Add support for emitting and disassembling bit instructions.
Specifically
bfe - for bitfieldExtract()
bfi1 and bfi2 - for bitfieldInsert()
bfrev - for bitfieldReverse()
cbit - for bitCount()
fbh - for findMSB()
fbl - for findLSB()
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Sun, 21 Apr 2013 04:41:15 +0000 (21:41 -0700)]
i965: Print the correct dst and shared-src types for 3-src instructions.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Wed, 17 Apr 2013 19:23:54 +0000 (12:23 -0700)]
i965/gen7: Set src/dst types for 3-src instructions.
Also update asserts to allow BFE and BFI2, which take (unsigned)
doubleword arguments.
v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well.
Assert that src2.type (instead of src0.type) matches dest.type since
it's the primary argument and src0 and src1 might correctly have
different types.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
Matt Turner [Wed, 17 Apr 2013 18:52:00 +0000 (11:52 -0700)]
i965: Add 3-src destination and shared-source type macros.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Wed, 17 Apr 2013 18:32:04 +0000 (11:32 -0700)]
i965: Add Gen7+ fields to brw_instruction and add comments.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Wed, 10 Apr 2013 05:43:05 +0000 (22:43 -0700)]
glsl: Add a pass to lower bitfield-insert into bfm+bfi.
i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement
bitfieldInsert() from ARB_gpu_shader5.
v2: Add ir_binop_bfm and ir_triop_bfi to st_glsl_to_tgsi.cpp.
Remove spurious temporary assignment and dereference.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Sun, 21 Apr 2013 19:33:59 +0000 (12:33 -0700)]
glsl: Add constant evaluation of bit built-ins.
v2: Order bits from LSB end (31 - count) for ir_unop_find_msb.
v3: Add ir_triop_bitfield_extract as an exception to the op[0]->type ==
op[1]->type assertion in ir_constant_expression.cpp.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
Matt Turner [Wed, 10 Apr 2013 00:45:12 +0000 (17:45 -0700)]
glsl: Add support for new bit built-ins in ARB_gpu_shader5.
v2: Move use of ir_binop_bfm and ir_triop_bfi to a later patch.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Tue, 9 Apr 2013 23:03:15 +0000 (16:03 -0700)]
glsl: Add new bit built-ins IR and prototypes from ARB_gpu_shader5.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Tue, 9 Apr 2013 23:43:14 +0000 (16:43 -0700)]
glsl: Rework ir_reader to handle expressions with four operands.
Needed to support the bitfieldInsert() built-in added by
ARB_gpu_shader5.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Tue, 9 Apr 2013 23:01:38 +0000 (16:01 -0700)]
mesa: Add infrastructure for ARB_gpu_shader5.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Tom Stellard [Wed, 24 Apr 2013 03:14:01 +0000 (20:14 -0700)]
radeon/llvm: Always build libradeonllvm as static
This library is very small, so there is not much to gain from building
it as a shared library. Also, when linking statically with LLVM, a
shared libradeonllvm exports LLVM symbols and creates problems when
used with other shared objects that also link statically to LLVM.
Reviewed-by: Mathias.Froehlich@web.de
Tom Stellard [Tue, 2 Apr 2013 17:42:50 +0000 (10:42 -0700)]
radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA v2
The LLVM C API is considered stable and should never change, so it
is much more desirable to use than the LLVM C++ API, which is constantly in
flux.
v2:
- Split target initialization and lookup into separate functions
Reviewed-by: Mathias.Froehlich@web.de
Tom Stellard [Tue, 30 Apr 2013 14:38:03 +0000 (07:38 -0700)]
gallivm: Move LLVMStartMultithreaded() static initializer into gallivm
This does not solve all of the problems with using LLVM in a
multithreaded enivronment, but it should help in some cases.
Reviewed-by: Mathias.Froehlich@web.de
Tom Stellard [Thu, 2 May 2013 22:25:53 +0000 (18:25 -0400)]
radeon/llvm: Don't use the global context when parsing LLVM IR
This leads to crashes when multiple threads try to compile compute
shaders in the same time.
Fixes a crash in bfgminer when using more than one thread.
Eric Anholt [Thu, 25 Apr 2013 19:06:23 +0000 (12:06 -0700)]
i965: Remove GL_ARB_color_buffer_float from GL core contexts.
Of the 3 controls in the extension, one was kept in GL core and the other
two were explicitly deprecated and the reasonable default behavior was
encoded in the spec. By not exposing the extension, we avoid shader
recompiles when switching between float and unorm color buffers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tom Stellard [Mon, 29 Apr 2013 20:10:09 +0000 (13:10 -0700)]
r600g/llvm: Update radeon family mappings for LLVM backend
New processors were added to the backend to distinguish between
GPUs with and without vertex caches.
Chia-I Wu [Fri, 3 May 2013 07:44:10 +0000 (15:44 +0800)]
android: libsync is needed on Android 4.2+ for any driver
Add libsync not only for MESA_BUILD_CLASSIC, but also for MESA_BUILD_GALLIUM.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Chia-I Wu [Fri, 3 May 2013 07:44:09 +0000 (15:44 +0800)]
android: add ilo to the build system
It can be selected with
BOARD_GPU_DRIVERS := ilo
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Anholt [Fri, 3 May 2013 20:17:56 +0000 (13:17 -0700)]
glsl: Flip around "if" statements with empty "then" blocks.
This cleans up some funny-looking code in some unigine shaders I was
looking at. Also slightly helps on planeshift and a few shaders in an
upcoming Valve release.
total instructions in shared programs: 1653715 -> 1653587 (-0.01%)
instructions in affected programs: 16550 -> 16422 (-0.77%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Chia-I Wu [Sun, 5 May 2013 06:13:39 +0000 (14:13 +0800)]
ilo: correctly set return types of sampler messages
Correctly set the types of the temporaries. We do not want type conversions
when moving the results to the final destinations.
Vincent Lejeune [Tue, 30 Apr 2013 13:58:00 +0000 (15:58 +0200)]
r600g/llvm: Undefines unrequired texture coord values
This is a port of "r600g:mask unused source components for SAMPLE"
patch from Vadim Girlin.
Maarten Lankhorst [Sat, 4 May 2013 18:56:02 +0000 (20:56 +0200)]
nvc0: fixup video decoding with 2D_ARRAY
Signed-off-by: Maarten Lankhorst <m.b.lankhorst@gmail.com>
Chia-I Wu [Thu, 2 May 2013 08:25:15 +0000 (16:25 +0800)]
gallium: fix type of flags in pipe_context::flush()
It should be unsigned, not enum pipe_flush_flags.
Fixed a build error:
src/gallium/state_trackers/egl/android/native_android.cpp:426:29: error:
invalid conversion from 'int' to 'pipe_flush_flags' [-fpermissive]
v2: replace all occurrences of enum pipe_flush_flags by unsigned
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
[olv: document the parameter now that the type is unsigned]
Eric Anholt [Tue, 23 Apr 2013 20:58:31 +0000 (13:58 -0700)]
i965: Enable fast clears on non-8x4-aligned sizes.
Improves glb2.7 performance at a misaligned size by 2.3% +/- 0.7% (n=11).
The workaround was to avoid bad primitive/surface sizes, but that's worked
around as of
a14dc4f92cdad6177d83f051a088a66e31a973bc. (One might note
that pre-gen7 we don't know that the right half of an 8x4 at the right
edge is actually our pixels, but we're already clobbering those pixels for
depth resolves anyway and more work would be required to avoid that).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: add comments, const qualifiers
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
mesa: whitespace, formatting fixes, etc in api_arrayelt.c
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: use new no-op ArrayElement in _mesa_noop_vtxfmt_init()
As we do for the other commands which can appear between glBegin/End.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
mesa: change ctx->Driver.NeedFlush to GLbitfield and update comment
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
mesa; change ctx->Driver.SaveNeedFlush to boolean, and document it.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: update comments for vbo_save_NotifyBegin()
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: implement primitive merging for glBegin/End sequences
A surprising number of apps and benchmarks have poor code like this:
glBegin(GL_LINE_STRIP);
glVertex(v1);
glVertex(v2);
glEnd();
// Possibly some no-op state changes here
glBegin(GL_LINE_STRIP);
glVertex(v3);
glVertex(v4);
glEnd();
// repeat many, many times.
The above sequence can be converted into:
glBegin(GL_LINES);
glVertex(v1);
glVertex(v2);
glVertex(v3);
glVertex(v4);
glEnd();
Similarly for GL_POINTS, GL_TRIANGLES, etc.
Merging was already implemented for GL_QUADS in the display list code.
Now other prim types are handled and it's also done for immediate mode.
In one case:
before after
-----------------------------------------------
number of st_draw_vbo() calls: 141 45
number of _mesa_prims issued: 7520 632
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Sat, 4 May 2013 01:00:07 +0000 (19:00 -0600)]
vbo: create a few utility functions for merging primitives
To be used by following commit.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Zack Rusin [Fri, 3 May 2013 03:38:28 +0000 (23:38 -0400)]
draw/pt: adjust overflow calculations
gallium lies. buffer_size is not actually buffer_size but available
size, which is 'buffer_size - buffer_offset' so by adding buffer
offset we'd incorrectly compute overflow.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Zack Rusin [Thu, 2 May 2013 07:47:07 +0000 (03:47 -0400)]
tgsi/ureg: make the dst register match the src indirection
In ureg src registers could have an indirect register that was
either a temp or an addr register, while dst registers allowed
only addr. That made moving between them a little difficult so
make them behave the same way and allow temp's and addr registers
as indirect files for both (tgsi supports it, just ureg didn't).
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Fri, 3 May 2013 19:34:12 +0000 (21:34 +0200)]
gallium: tgsi documentation updates and clarification for integer opcodes.
A lot of them were missing. Others were moved from the Compute ISA
to a new Integer ISA section as that seemed more appropriate.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Wed, 1 May 2013 15:54:08 +0000 (17:54 +0200)]
llvmpipe: get rid of depth swizzling.
Eliminating this we no longer need to copy between linear and swizzled layout.
This is probably not quite ideal since it's a bit more work for now, could do
some optimizations by moving depth testing outside the fragment shader loop
(but tricky for early depth test as we don't have neither the mask nor the
interpolated z in the right order handy).
The large amount of tile/untile code is no longer needed will be deleted
in next commit.
No piglit regressions.
v2: change a forgotten LAYOUT_NONE to LAYOUT_LINEAR.
v3: fix (bogus) uninitialized variable warnings, add comments, fix a bad type
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Lauri Kasanen [Fri, 3 May 2013 13:55:49 +0000 (16:55 +0300)]
r600g: Correctly initialize the shader key, v2
Assigning a struct only copies the members - any padding is left as is.
Thus this code:
struct foo_t foo;
foo = bar;
leaves the padding of foo intact, ie uninitialized random garbage.
This patch fixes constant shader recompiles by initializing the struct
to zero. For completeness, memcpy is used to copy the key to the shader
struct.
NOTE: This is a candidate for the stable branches.
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Lauri Kasanen [Fri, 3 May 2013 08:48:53 +0000 (11:48 +0300)]
st/xvmc/tests: Fix build failure, v2
v2: Removed extra libs as requested by Matt Turner.
Signed-off-by: Lauri Kasanen <cand@gmx.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Andreas Boll [Fri, 3 May 2013 09:41:00 +0000 (11:41 +0200)]
scons: remove nouveau build
One build system for linux/unix only drivers should be enough.
Additionally the nouveau target was disabled anyway.
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Andreas Boll [Fri, 3 May 2013 09:33:35 +0000 (11:33 +0200)]
scons: remove radeon build
One build system for linux/unix only drivers should be enough.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48694
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Alex Deucher [Fri, 3 May 2013 13:56:31 +0000 (09:56 -0400)]
r600g: don't emit surface_sync after FLUSH_AND_INV_EVENT
It shouldn't be needed since the FLUSH_AND_INV_EVENT has already
made sure the destination caches are flushed. Additionally,
we didn't previously emit the surface_sync until this commit:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=
e5e4c07e7964a3258ed02b530bcdc24c0650204b
Emitting them together causes hangs in compute on cayman/TN
and hangs in Heaven on evergreen.
Note: this patch is a candidate for the 9.1 branch, but requires:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=
156bcca62c9f4e79e78929f72bc085757f36a65a
as well.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vadim Girlin [Fri, 3 May 2013 12:53:27 +0000 (16:53 +0400)]
r600g/sb: zero-initialize bytecode structs
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Fri, 3 May 2013 09:01:31 +0000 (13:01 +0400)]
r600g/sb: fix constant propagation in gvn pass
Fixes the bug that prevented propagation of literals in some cases.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Thu, 2 May 2013 15:36:52 +0000 (19:36 +0400)]
r600g/sb: don't run unnecessary passes
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Thu, 2 May 2013 06:36:18 +0000 (10:36 +0400)]
r600g/sb: silence warnings with gcc 4.8
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Thu, 2 May 2013 03:53:00 +0000 (07:53 +0400)]
r600g/sb: fix handling of interference sets in post_scheduler
post_scheduler clears interference set for reallocatable values when
the value becomes live first time, and then updates it to take into
account modified order of operations, but this was not handled properly
if the value appears first time as a source in copy operation.
Fixes issues with webgl demo: http://madebyevan.com/webgl-water/
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Thu, 2 May 2013 03:56:32 +0000 (07:56 +0400)]
r600g/sb: fix allocation of indirectly addressed input arrays
Some inputs may be preloaded into predefined GPRs,
so we can't reallocate arrays with such inputs.
Fixes issues with webgl demo: http://oos.moxiecode.com/js_webgl/snake/
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Wed, 1 May 2013 17:33:33 +0000 (21:33 +0400)]
r600g/sb: use hex instead of binary constants
This should fix build issues with GCC < 4.3
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Vadim Girlin [Fri, 3 May 2013 08:01:20 +0000 (12:01 +0400)]
r600g: use old shader disassembler by default
New disassembler is not completely isolated yet from further processing
in r600g/sb that is not required for printing the dump, so it has higher
probability to fail in case of any unexpected features in the bytecode.
This patch adds "sbdisasm" flag for R600_DEBUG that allows to use new
disassembler in r600g/sb for shader dumps when shader optimization
is not enabled.
If shader optimization is enabled, new disassembler is used by default.
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Christian König [Thu, 2 May 2013 14:19:41 +0000 (16:19 +0200)]
radeon/uvd: enable interlaced buffers by default
Kills tilling on UVD buffers, but we currently don't really need that.
Signed-off-by: Christian König <christian.koenig@amd.com>
Christian König [Thu, 2 May 2013 14:02:05 +0000 (16:02 +0200)]
vl/idct: fix for commit
7d2f2a0c890b1993532a45c8c392c28950ddc06e
We still need the option for handling 3D textures as well.
Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=64143
Signed-off-by: Christian König <christian.koenig@amd.com>
Christian König [Thu, 2 May 2013 13:42:24 +0000 (15:42 +0200)]
vl/buffers: fix typo in function name
Signed-off-by: Christian König <christian.koenig@amd.com>
Christian König [Wed, 1 May 2013 12:33:49 +0000 (14:33 +0200)]
radeon/uvd: fix some MPEG4 artifacts
Still not perfect, but a step in the right direction.
Signed-off-by: Christian König <christian.koenig@amd.com>
José Fonseca [Fri, 3 May 2013 07:35:17 +0000 (08:35 +0100)]
draw: Update for u_assembled_primitive -> u_assembled_prim rename.
Mesa build is too complex to rely on successful builds. On refactorings
it is always a good idea to use git grep to prevent missing cases:
$ git grep u_assembled_primitive
src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c: u_assembled_primitive(in_prim);
Chia-I Wu [Thu, 2 May 2013 08:13:28 +0000 (16:13 +0800)]
st/egl: fix bulid errors on Android 4.2
The differences from the previous releases that affect st/egl are
- logging macros are prefixed with an 'A'
- dequeueBuffer() and enqueueBuffer() require an additoinal argument for
fence fd, acquired from libsync
Additionally, include gralloc_drm.h with extern "C".
Chia-I Wu [Thu, 2 May 2013 06:32:30 +0000 (14:32 +0800)]
ilo: use u_reduced_prims_for_vertices()
We do not need our own prim_count() anymore.
Chia-I Wu [Thu, 2 May 2013 06:28:12 +0000 (14:28 +0800)]
util/prim: add u_reduced_prims_for_vertices()
The function returns the number of reduced/tessellated primitives for the
given vertex count.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
Chia-I Wu [Thu, 2 May 2013 06:12:27 +0000 (14:12 +0800)]
util/prim: assorted fixes for u_decomposed_prims_for_vertices()
Switch to '>=' for comparisons, and it becomes obvious that the comparison for
PIPE_PRIM_QUAD_STRIP was wrong.
Add minimum vertex count check for PIPE_PRIM_LINE_LOOP. Return 1 for
PIPE_PRIM_POLYGON with 3 vertices.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
Chia-I Wu [Thu, 2 May 2013 05:49:30 +0000 (13:49 +0800)]
util/prim: use vertex count info in u_validate_pipe_prim()
As a side effect, primitives with adjacency are now correctly validated.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>
Chia-I Wu [Thu, 2 May 2013 05:46:21 +0000 (13:46 +0800)]
util/prim: fix the name of the include guard
It should be U_PRIM_H, not U_BLIT_H.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Zack Rusin <zackr@vmware.com>