Sanjay Patel [Thu, 13 Jan 2022 15:45:31 +0000 (10:45 -0500)]
[PowerPC] add RUN lines for both endians to test; NFC
The load narrowing transform works for both targets,
so we might as well test both with simple examples
like this.
Jan Svoboda [Thu, 13 Jan 2022 15:29:10 +0000 (16:29 +0100)]
Revert "[clang][lex] Keep references to `DirectoryLookup` objects up-to-date"
This reverts commit
8503c688. This patch causes some issues with `#include_next`: https://github.com/llvm/llvm-project/issues/53161
Simon Pilgrim [Thu, 13 Jan 2022 15:25:13 +0000 (15:25 +0000)]
[X86] Add tests showing failure to merge shuffles through avx2 shift binops
Simon Pilgrim [Thu, 13 Jan 2022 15:06:13 +0000 (15:06 +0000)]
[X86] Add tests showing failure to merge shuffles through xop shift binops
Arthur O'Dwyer [Fri, 7 Jan 2022 14:45:05 +0000 (09:45 -0500)]
[libc++] Add tests verifying alphabetical order for several things.
These things are header #includes, CMakeLists.txt, and module.modulemap.
Differential Revision: https://reviews.llvm.org/D116958
Erich Keane [Thu, 13 Jan 2022 14:52:58 +0000 (06:52 -0800)]
Add another assert to cpu-dispatch emission to help track down a tough
to repro error.
As mentioned yesterday, I've got a problem that I can only reproduce on
Godbolt (none of the build configs on my local machine!), so this is at
least somewhat usable until I figure out a cause.
Simon Pilgrim [Thu, 13 Jan 2022 14:32:03 +0000 (14:32 +0000)]
[DAG] Add ISD::ROTL/ROTR to TargetLoweringBase::isBinOp
Allows shuffle combining through rotation nodes
Simon Pilgrim [Thu, 13 Jan 2022 14:09:05 +0000 (14:09 +0000)]
[X86] Add tests showing failure to merge shuffles through rotation binops
Denys Shabalin [Thu, 13 Jan 2022 10:33:42 +0000 (11:33 +0100)]
[mlir] Introduce C API for PDL dialect types
This change introduces C API helper functions to work with PDL types.
Modification closely follow the format of the https://reviews.llvm.org/D116546.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D117221
Denys Shabalin [Thu, 13 Jan 2022 14:11:33 +0000 (15:11 +0100)]
[mlir] Fix reference to out of date CMake function
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D117222
David Spickett [Thu, 13 Jan 2022 14:21:33 +0000 (14:21 +0000)]
[lldb][AArch64] Remove armv8.3-a flag from tagged memory read test
This was left over from when I had used some pointer authentication
instructions to sign the pointer. Then I realised that simply setting
the top byte is enough to prove the ABI plugin is being called.
Top byte ignore is a feature of the armv8-a architecure and doesn't
need any extra compiler flags.
Eugene Zhulenev [Thu, 13 Jan 2022 10:19:44 +0000 (02:19 -0800)]
[DebugInfo][InstrRef] Short-circuit unnecessary preferred location map construction
Reviewed By: cota
Differential Revision: https://reviews.llvm.org/D117162
Sam McCall [Thu, 13 Jan 2022 07:03:39 +0000 (08:03 +0100)]
[clangd] Ignore cvr-qualifiers in selection.
The AST doesn't track their locations, and the default behavior of attributing
them to the lexically-enclosing node is sloppy and often inaccurate.
Also add a couple of passing test cases for declarators that weren't obvious.
Differential Revision: https://reviews.llvm.org/D117185
Jon Chesterfield [Thu, 13 Jan 2022 13:57:31 +0000 (13:57 +0000)]
[openmp] Mark used variables as retain as well
D97446 changed the behaviour of 'used'. Compensate.
Reviewed By: ronlieb
Differential Revision: https://reviews.llvm.org/D117211
Nikita Popov [Thu, 13 Jan 2022 13:37:20 +0000 (14:37 +0100)]
[ConstantFold] Check uniform value in ConstantFoldLoadFromConst()
This case is automatically handled if ConstantFoldLoadFromConstPtr()
is used. Make sure that ConstantFoldLoadFromConst() also handles it.
Petar Avramovic [Thu, 13 Jan 2022 13:28:00 +0000 (14:28 +0100)]
AMDGPU/GlobalISel: Fix custom legalizatation for fceil
Petar Avramovic [Thu, 13 Jan 2022 13:26:04 +0000 (14:26 +0100)]
AMDGPU/GlobalISel: Regenerate fceil test (NFC)
Sander de Smalen [Thu, 13 Jan 2022 11:19:44 +0000 (11:19 +0000)]
[AArch64] Add native CPU detection for Neoverse-V1.
Map Main ID part number 0xd40 to neoverse-v1, as described in the
Neoverse-V1 Technical Reference Manual:
https://developer.arm.com/documentation/101427/0101/Register-descriptions/AArch64-system-registers/MIDR-EL1--Main-ID-Register--EL1
Differential Revision: https://reviews.llvm.org/D117207
Sam McCall [Mon, 10 Jan 2022 23:09:58 +0000 (00:09 +0100)]
[clangd] Selection: Prune gtest TEST()s earlier
When searching for AST nodes that may overlap the selection, mayHit() was only
attempting to prune nodes whose begin/end are both in the main file.
While failing to prune never gives wrong results, it hurts performance.
In GTest unit-tests, `TEST()` macros at the top level declare classes.
These were never pruned and we traversed *every* such class for any selection.
We fix this by reasoning about what tokens such a node might claim.
They must lie within its ultimate macro expansion range, so if this doesn't
overlap with the selection, we can prune the node.
Differential Revision: https://reviews.llvm.org/D116978
Kirill Bobyrev [Thu, 13 Jan 2022 12:42:01 +0000 (13:42 +0100)]
[clangd] Fix build after D115243
The api for loadIndex changed but was not updated everywhere due to
differences in the build configuration.
Simon Pilgrim [Thu, 13 Jan 2022 11:58:57 +0000 (11:58 +0000)]
[X86][AVX] lowerShuffleAsLanePermuteAndShuffle - don't split element rotate patterns
Partial element rotate patterns (e.g. for element insertion on Issue #53124) were being split if every lane wasn't crossing, but really there's a good repeated mask hiding in there.
Evgeny Mandrikov [Thu, 13 Jan 2022 11:51:48 +0000 (12:51 +0100)]
Fix build failure with MSVC in C++20 mode
Without this patch when using CMAKE_CXX_STANDARD=20
and MSVC 19.30.30705.0 compilation fails with
clang\lib\Tooling\Syntax\Tree.cpp(347): error C2666: 'clang::syntax::Tree::ChildIteratorBase<clang::syntax::Tree::ChildIterator,clang::syntax::Node>::operator ==': 4 overloads have similar conversions
clang\lib\Tooling\Syntax\Tree.cpp(392): error C2666: 'clang::syntax::Tree::ChildIteratorBase<clang::syntax::Tree::ChildIterator,clang::syntax::Node>::operator ==': 4 overloads have similar conversions
Note that removed comment that
"iterator_facade_base requires == to be a member"
was made obsolete by change https://reviews.llvm.org/D78938
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D116904
David Green [Thu, 13 Jan 2022 11:53:12 +0000 (11:53 +0000)]
[AArch64] Basic demand elements for some intrinsics
A lot of neon intrinsics work lane-wise, meaning that non-demanded
elements in and not demanded out. This teaches that to
AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic for some simple
single-input truncate intrinsics, which can help remove unnecessary
instructions.
Differential Revision: https://reviews.llvm.org/D117097
Simon Pilgrim [Thu, 13 Jan 2022 11:37:37 +0000 (11:37 +0000)]
[X86][AVX] Add v8f32/v8i32
01289abc test case
Blend Insertion + Element Rotation pattern similar to Issue #53124
Javier Setoain [Wed, 12 Jan 2022 17:01:07 +0000 (17:01 +0000)]
[mlir] Fix scalable type translation in splat element attr
LLVM Dialect Constant Op translations assume that if the attribute is a
vector, it's a fixed length one, generating an invalid translation for
constant scalable vector initializations.
Differential Revision: https://reviews.llvm.org/D117125
Alex Bradbury [Thu, 13 Jan 2022 11:05:03 +0000 (11:05 +0000)]
[llvm-objdump][test] Add RISC-V objdump test case
This test case captures the current state of support for printing branch
targets.
Differential Revision: https://reviews.llvm.org/D116676
Florian Hahn [Thu, 13 Jan 2022 11:13:04 +0000 (11:13 +0000)]
[VPlan] Make IV operand explicit for VPWidenCanonicalIVRecipe (NFC).
This makes the def-use relationship between VPCanonicalIVPHIRecipe and
VPWidenCanonicalIVRecipe explicit. Needed for D117140.
Simon Pilgrim [Thu, 13 Jan 2022 11:10:21 +0000 (11:10 +0000)]
Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC.
Simon Pilgrim [Thu, 13 Jan 2022 11:09:58 +0000 (11:09 +0000)]
Fix MSVC "32-bit shift implicitly converted to 64 bits" warning. NFC.
Simon Pilgrim [Wed, 12 Jan 2022 16:18:18 +0000 (16:18 +0000)]
[MIPS] Mips16DAGToDAGISel::selectAddr - Use cast<> instead of dyn_cast<> to avoid dereference of nullptr
The pointer is always dereferenced immediately below, so assert the cast is correct instead of returning nullptr
Hans Wennborg [Mon, 3 Jan 2022 17:03:43 +0000 (18:03 +0100)]
Don't override __attribute__((no_stack_protector)) by inlining (PR52886)
Since
26c6a3e736d3, LLVM's inliner will "upgrade" the caller's stack protector
attribute based on the callee. This lead to surprising results with Clang's
no_stack_protector attribute added in
4fbf84c1732f (D46300). Consider the
following code compiled with clang -fstack-protector-strong -Os
(https://godbolt.org/z/7s3rW7a1q).
extern void h(int* p);
inline __attribute__((always_inline)) int g() {
return 0;
}
int __attribute__((__no_stack_protector__)) f() {
int a[1];
h(a);
return g();
}
LLVM will inline g() into f(), and f() would get a stack protector, against the
users explicit wishes, potentially breaking the program e.g. if h() changes the
value of the stack cookie. That's a miscompile.
More recently,
bc044a88ee3c (D91816) addressed this problem by preventing
inlining when the stack protector is disabled in the caller and enabled in the
callee or vice versa. However, the problem remained if the callee is marked
always_inline as in the example above. This affected users, see e.g.
http://crbug.com/1274129 and http://llvm.org/pr52886.
One way to fix this would be to prevent inlining also in the always_inline
case. Despite the name, always_inline does not guarantee inlining, so this
would be legal but potentially surprising to users.
However, I think the better fix is to not enable the stack protector in a
caller based on the callee. The motivation for the old behaviour is unclear, it
seems counter-intuitive, and causes real problems as we've seen.
This commit implements that fix, which means in the example above, g() gets
inlined into f() (also without always_inline), and f() is emitted without stack
protector. I think that matches most developers' expectations, and that's also
what GCC does.
Another effect of this change is that a no_stack_protector function can now be
inlined into a stack protected function, e.g. (https://godbolt.org/z/hafP6W856):
extern void h(int* p);
inline int __attribute__((__no_stack_protector__)) __attribute__((always_inline)) g() {
return 0;
}
int f() {
int a[1];
h(a);
return g();
}
I think that's fine. Such code would be unusual since no_stack_protector is
normally applied to a program entry point which sets up the stack canary. And
even if such code exists, inlining doesn't change the semantics: there is still
no stack cookie setup/check around entry/exit of the g() code region, but there
may be in the surrounding context, as there was before inlining. This also
matches GCC.
See also the discussion at https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94722
Differential revision: https://reviews.llvm.org/D116589
Sebastian Neubauer [Fri, 7 Jan 2022 17:27:45 +0000 (18:27 +0100)]
[Docs] Fix IR and TableGen grammar inconsistencies
IR:
- globals (and functions, ifuncs, aliases) can have a partition
- catchret has a `to` before the label
- the sint/int types do not exist
- signext comes after the type
- a variable was missing its type
TableGen:
- The second value after a `#` concatenation is optional
See e.g. llvm/lib/Target/X86/X86InstrAVX512.td:L3351
- IncludeDirective and PreprocessorDirective were never referenced in
the grammar
- Add some missing ;
- Parent classes of multiclasses can have generic arguments.
Reuse the `ParentClassList` that is already used in other places.
MIR:
- liveins only allows physical registers, which start with a $
Differential Revision: https://reviews.llvm.org/D116674
Ivan Butygin [Wed, 12 Jan 2022 12:36:43 +0000 (15:36 +0300)]
[mlir] Provide getMixedOffsets/sizes/strides as free functions
* This is useful when you need to build mixed array from external static/dynamic arrays (e.g. from adaptor during dialect conversion)
* Also, to reduce C++ code in td and generated files
Differential Revision: https://reviews.llvm.org/D117106
David Green [Thu, 13 Jan 2022 10:46:00 +0000 (10:46 +0000)]
[AArch64] Add a demand bits intrinsic test for instcombine of AArch64 intrinsics. NFC
Ties Stuij [Thu, 13 Jan 2022 10:17:13 +0000 (10:17 +0000)]
[ARM] fix bug causing shrinkwrapping not always being off using PAC
If you want to check for all uses of PAC, the SpillsLR argument to
shouldSignReturnAddress should be true instead of false, as that value will be
returned from the function if the other checks fall through.
Reviewed By: miyuki
Differential Revision: https://reviews.llvm.org/D116213
Hans Wennborg [Thu, 13 Jan 2022 10:31:11 +0000 (11:31 +0100)]
Simplify llvm/test/Transforms/Inline/inline_ssp.ll (NFC)
The nounwind and uwtable attributes were just cluttering up the test.
Using regexes to give symbolic names to the attribute lists make the
test more readable.
This is pre-committing parts of D116589.
Andrzej Warzynski [Wed, 12 Jan 2022 10:45:44 +0000 (10:45 +0000)]
[flang][nfc] Update README.md
With https://reviews.llvm.org/D116731 merged, installing Clang, MLIR or
LLVM is no longer required for standalone builds. For consistency sake,
remove "installation" from the build instrucitons.
Differential Revision: https://reviews.llvm.org/D117100
Michał Górny [Tue, 11 Jan 2022 19:28:37 +0000 (20:28 +0100)]
[lldb] [llgs] Implement qXfer:siginfo:read
Implement the qXfer:siginfo:read that is used to read the siginfo_t
(extended signal information) for the current thread. This is currently
implemented on FreeBSD and Linux.
Differential Revision: https://reviews.llvm.org/D117113
Nikita Popov [Thu, 13 Jan 2022 10:12:05 +0000 (11:12 +0100)]
[GlobalOpt] Fix global to select transform under opaque pointers
We need to check that the load/store type is also the same, as this
is no longer implicitly checked through the pointer type.
Paulo Matos [Thu, 13 Jan 2022 09:03:59 +0000 (10:03 +0100)]
[WebAssembly] Fix reftype load/store match with idx from call
Implement support for matching an index from a WebAssembly CALL
instruction. Add test.
Reviewed By: tlively
Differential Revision: https://reviews.llvm.org/D115327
Jay Foad [Wed, 12 Jan 2022 14:56:20 +0000 (14:56 +0000)]
[FileCheck] Allow literal '['s before "[[var...]]"
Change FileCheck to accept patterns like "[[[var...]]" and treat the
excess open brackets at the start as literals.
This makes the patterns for matching assembler output with literal
brackets much cleaner. For example an AMDGPU pattern that used to be
written like:
buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
can now be:
buffer_store_dwordx2 v[[[LO]]:[[HI]]]
(Even before this patch the final close bracket did not need to be
wrapped in {{}}, but people tended to do it anyway for symmetry.)
This does not introduce any ambiguity since "[[" was always followed by
an identifier or '@' or '#', so "[[[" was always an error.
I've included a few test updates in this patch just for illustration and
testing. There are a couple of hundred tests that could be updated as a
follow up, mostly in test/CodeGen/.
Differential Revision: https://reviews.llvm.org/D117117
Change-Id: Ia6bc6f65cb69734821c911f54a43fe1c673bcca7
David Sherwood [Mon, 22 Nov 2021 11:38:06 +0000 (11:38 +0000)]
[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants
When we know the value we're extending is a negative constant then it
makes sense to use SIGN_EXTEND because this may improve code quality in
some cases, particularly when doing a constant splat of an unpacked vector
type. For example, for SVE when splatting the value -1 into all elements
of a vector of type <vscale x 2 x i32> the element type will get promoted
from i32 -> i64. In this case we want the splat value to sign-extend from
(i32 -1) -> (i64 -1), whereas currently it zero-extends from
(i32 -1) -> (i64 0xFFFFFFFF). Sign-extending the constant means we can use
a single mov immediate instruction.
New tests added here:
CodeGen/AArch64/sve-vector-splat.ll
I believe we see some code quality improvements in these existing
tests too:
CodeGen/AArch64/dag-numsignbits.ll
CodeGen/AArch64/reduce-and.ll
CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
The apparent regressions in CodeGen/AArch64/fast-isel-cmp-vec.ll only
occur because the test disables codegen prepare and branch folding.
Differential Revision: https://reviews.llvm.org/D114357
Florian Hahn [Thu, 13 Jan 2022 09:34:31 +0000 (09:34 +0000)]
[LV] Inline CreateSplatIV call for scalar VFs (NFC).
This is a NFC change split off from D116123, as suggested there.
D116123 will remove the last user of CreateSplatIV.
Kévin Petit [Wed, 5 Jan 2022 16:32:08 +0000 (16:32 +0000)]
libclc: Add clspv64 target
Add a variant of the clspv target that is built using spir64.
This is a pre-requisite to supporting spir64 in clspv which is
required to take advantage of SPV_KHR_physical_storage_buffer which
in turn enables more OpenCL C programs to be compiled with clspv.
https://reviews.llvm.org/D116668
David Sherwood [Wed, 12 Jan 2022 09:51:34 +0000 (09:51 +0000)]
[AArch64] Fix incorrect use of MVT::getVectorNumElements in AArch64TTIImpl::getVectorInstrCost
If we are inserting into or extracting from a scalable vector we do
not know the number of elements at runtime, so we can only let the
index wrap for fixed-length vectors.
Tests added here:
Analysis/CostModel/AArch64/sve-insert-extract.ll
Differential Revision: https://reviews.llvm.org/D117099
Sam McCall [Tue, 11 Jan 2022 17:43:17 +0000 (18:43 +0100)]
[clangd] Remove --inlay-hints flag
Differential Revision: https://reviews.llvm.org/D117036
Vladislav Khmelevsky [Wed, 12 Jan 2022 21:08:45 +0000 (00:08 +0300)]
RuntimeDyldELF: Don't abort on R_AARCH64_NONE relocation
Do nothing on R_AARCH64_NONE relocation. The relocation is used by BOLT when re-linking the final binary. It is used as a dummy relocation hack in order to stop the RuntimeDyld to skip the allocation of the section.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D117066
David Sherwood [Wed, 5 Jan 2022 09:40:50 +0000 (09:40 +0000)]
[NFC][AArch64][CodeGen] Add fixed-width vector tests for get.active.lane.mask
In practice we don't expect to see the get.active.lane.mask intrinsic
being used for fixed-width vectors, but we should at least be able
to generate code for it. This patch simply adds some fixed-width tests
to an existing file:
CodeGen/AArch64/active_lane_mask.ll
Differential Revision: https://reviews.llvm.org/D116644
Adrian Kuegel [Thu, 13 Jan 2022 08:29:10 +0000 (09:29 +0100)]
[mlir] Add missing const to cloneWith method.
luxufan [Mon, 10 Jan 2022 01:04:41 +0000 (09:04 +0800)]
[JITLink] Add fixup value range check
This patch makes jitlink to report an out of range error when the fixup value out of range
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D107328
mydeveloperday [Thu, 13 Jan 2022 07:53:00 +0000 (07:53 +0000)]
[clang-format] clang-format eats space in front of attributes for operator delete
https://github.com/llvm/llvm-project/issues/27037
Sorry its taken so long to get to this issue! (got it before it hit its 6th birthday!)
```
void operator delete(void *foo)ATTRIB;
```
(void *foo) is incorrectly determined to be a C-Style Cast resulting in the space being removed after the ) and before the attrib, due to the detection of
```
delete (A* )a;
```
The following was previously unaffected
```
void operator new(void *foo) ATTRIB;
```
Fixes #27037
Reviewed By: curdeius, HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D116920
Jim Lin [Thu, 13 Jan 2022 05:47:35 +0000 (13:47 +0800)]
[M68k][NFC] Use Register instead of unsigned int
Christian Sigg [Wed, 12 Jan 2022 19:52:53 +0000 (20:52 +0100)]
[NVPTX] Lower fp16 fminnum, fmaxnum to native on sm_80.
Reviewed By: bkramer, tra
Differential Revision: https://reviews.llvm.org/D117122
Sam McCall [Tue, 7 Dec 2021 13:06:40 +0000 (14:06 +0100)]
[clangd] Extend SymbolOrigin, stop serializing it
New values:
- Split Dynamic into Open/Preamble
- Add Background (previously was just Unknown)
- Soon: stdlib index
This requires extending to 16 bits, which fits within the padding of Symbol.
Unfortunately we're also *serializing* SymbolOrigin as a fixed 8 bits.
Stop serializing SymbolOrigin:
- conceptually, the source is whoever indexes or *deserializes* a symbol
- deserialization takes SymbolOrigin as a parameter and stamps it on each sym
- this is a breaking format change
Differential Revision: https://reviews.llvm.org/D115243
Sam McCall [Mon, 27 Dec 2021 03:08:01 +0000 (04:08 +0100)]
[CodeCompletion] (mostly) fix completion in incomplete C++ ctor initializers.
C++ member function bodies (including ctor initializers) are first captured
into a buffer and then parsed after the class is complete. (This allows
members to be referenced even if declared later).
When the boundary of the function body cannot be established, its buffer is
discarded and late-parsing never happens (it would surely fail).
For code completion this is the wrong tradeoff: the point of the parse is to
generate completions as a side-effect.
Today, when the ctor body wasn't typed yet there are no init list completions.
With this patch we parse such an init-list if it contains the completion point.
There's one caveat: the parser has to decide where to resume parsing members
after a broken init list. Often the first clear recovery point is *after* the
next member, so that member is missing from completion/signature help etc. e.g.
struct S {
S() m //<- completion here
int maaa;
int mbbb;
}
Here "int maaa;" is treated as part of the init list, so "maaa" is not available
as a completion. Maybe in future indentation can be used to recognize that
this is a separate member, not part of the init list.
Differential Revision: https://reviews.llvm.org/D116294
Kazu Hirata [Thu, 13 Jan 2022 06:12:01 +0000 (22:12 -0800)]
[clang] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
Kazu Hirata [Thu, 13 Jan 2022 06:11:59 +0000 (22:11 -0800)]
[Sema] Fix a bugprone argument comment (NFC)
Identified with bugprone-argument-comment.
Kazu Hirata [Thu, 13 Jan 2022 06:11:57 +0000 (22:11 -0800)]
[CSKY] Ensure a newline at the end of a file (NFC)
Igor Kudrin [Thu, 13 Jan 2022 04:38:26 +0000 (11:38 +0700)]
[ELF] Use tombstone values for discarded symbols in relocatable output
This extends D81784. Sections can be discarded when linking a
relocatable output. Before the patch, LLD did not update the content
of debug sections and only replaced the corresponding relocations with
R_*_NONE, which could break the debug information.
Differential Revision: https://reviews.llvm.org/D116946
Arthur O'Dwyer [Tue, 11 Jan 2022 16:27:53 +0000 (11:27 -0500)]
[libc++] [ranges] Implement ranges::cdata.
Differential Revision: https://reviews.llvm.org/D117044
James Y Knight [Thu, 13 Jan 2022 02:59:49 +0000 (02:59 +0000)]
Revert "[Inline] Attempt to delete any discardable if unused functions"
Somehow this ends up causing an infinite loop in the inliner.
This reverts commit
d5be48c66d3e5e8be21805c3a33dc67a20e258be.
Amir Ayupov [Thu, 13 Jan 2022 03:06:03 +0000 (19:06 -0800)]
[BOLT] Update repo location in Dockerfile
Lian Wang [Thu, 13 Jan 2022 02:53:00 +0000 (02:53 +0000)]
[RISCV] Add bfp and bfpw intrinsic in zbf extension
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D116994
Philip Reames [Thu, 13 Jan 2022 01:32:05 +0000 (17:32 -0800)]
[Attributor] Simplify how we handle required alignment during heap-to-stack [NFC]
The existing code duplicated the same concern in two places, and (weirdly) changed the inference of the allocation size based on whether we could meet the alignment requirement. Instead, just directly check the allocation requirement.
Peter Klausler [Wed, 29 Dec 2021 20:51:39 +0000 (12:51 -0800)]
[flang] RESHAPE(PAD=) can be arbitrary array rank
The "pad=" argument in the intrinsic function table entry for RESHAPE
has a Rank::Array constraint, and that would be fine if not for RESHAPE
already having an earlier argument that's Rank::Array. It's the only
intrinsic that has multiple Rank::Array arguments. The checking for
the Rank::Array constraint was enforcing that multiple occurrences
of it have the same rank in a call, and that's not appropriate.
Differential Revision: https://reviews.llvm.org/D117149
Shoaib Meenai [Thu, 13 Jan 2022 01:28:25 +0000 (17:28 -0800)]
[bolt] Fix relative links in README
The README is in the `bolt` subdirectory now, so relative links need to
be adjusted accordingly.
Kevin Athey [Wed, 12 Jan 2022 21:29:55 +0000 (13:29 -0800)]
[NFC] Minimize noundef analysis when disabled
Minor adjustment in order of noundef analysis to be a bit more optimal (when disabled).
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D117078
Lang Hames [Wed, 12 Jan 2022 21:09:05 +0000 (08:09 +1100)]
[JITLink] Fix assert condition broken in
118e953b18ff0.
The condition was accidentally changed from A != InvalidAddr to A != 0, this
commit changes it back.
Philip Reames [Thu, 13 Jan 2022 00:43:02 +0000 (16:43 -0800)]
[Attributor] Generalize calloc handling in heap-to-stack for any init value [NFC]
Rewrite the calloc specific handling in heap-to-stack to allow arbitrary init values. The basic problem being solved is that if an allocation is initilized to anything other than zero, this must be explicitly done for the formed alloca as well.
This covers the calloc case today, but once a couple of earlier guards are removed in this code, downstream allocators with other init values could also be handled.
Inspired by discussion on D116971
Philip Reames [Thu, 13 Jan 2022 00:16:36 +0000 (16:16 -0800)]
[Attributor] Reuse object size evaluation code [NFC]
Philip Reames [Thu, 13 Jan 2022 00:04:18 +0000 (16:04 -0800)]
[Attributor] Use getAllocAlignment where possible [NFC]
Inspired by D116971.
Matt Arsenault [Mon, 13 Dec 2021 21:26:02 +0000 (16:26 -0500)]
AMDGPU: Fix assert on function argument as loop condition
Stanislav Mekhanoshin [Tue, 11 Jan 2022 22:03:58 +0000 (14:03 -0800)]
[AMDGPU] Fixed physreg asm constraint parsing
We are always failing parsing of the physreg constraint because
we do not drop trailing brace, thus getAsInteger() returns a
non-empty string and we delegate reparsing to the TargetLowering.
In addition it did not parse register tuples.
Fixed which has allowed to remove w/a in two places we call it.
Differential Revision: https://reviews.llvm.org/D117055
Emily Shi [Tue, 11 Jan 2022 03:28:08 +0000 (19:28 -0800)]
[compiler-rt][darwin] check for strcmp to test interceptors instead of pthread_create
If `pthread_create` is not available on a platform, we won't be able to check if interceptors work. Use `strcmp` instead.
Reviewed By: yln
Differential Revision: https://reviews.llvm.org/D116989
LLVM GN Syncbot [Thu, 13 Jan 2022 00:08:45 +0000 (00:08 +0000)]
[gn build] Port
b9bc3c107c6c
Andrew Litteken [Thu, 6 Jan 2022 21:34:44 +0000 (15:34 -0600)]
[CostModel] Use cost of target trunc type when only it is the only use of a non-register sized load
The code size cost model for most targets uses the legalization cost for the type of the pointer of a load. If this load is followed directly by a trunc instruction, and is the only use of the result of the load, only one instruction is generated in the target assembly language. This adds a check for this case, and uses the target type of the trunc instruction if so.
This did not show any changes in CTMark code size benchmarks.
Reviewers: paquette, samparker, dmgreen
Differential Revision: https://reviews.llvm.org/D109388
Peter Klausler [Wed, 29 Dec 2021 20:14:25 +0000 (12:14 -0800)]
[flang] Fix handling of space between # and name in preprocessor stringification
When preprocessing "# ARG" in function-like macro expansion,
the preprocessor needs to pop the previously-pushed '#' token
from the end of the resulting token sequence after detecting the
argument name. The code to do this was just wrong in a couple of
ways.
Differential Revision: https://reviews.llvm.org/D117148
Konstantin Varlamov [Thu, 13 Jan 2022 00:00:44 +0000 (16:00 -0800)]
[libc++][ranges] Implement `construct_at` and `destroy{,_at}`.
Differential Revision: https://reviews.llvm.org/D116078
Matt Arsenault [Wed, 12 Jan 2022 20:31:51 +0000 (15:31 -0500)]
GlobalISel: Always enable GISelKnownBits for InstructionSelect
This wasn't running at -O0, and causing crashes for AMDGPU. AMDGPU
needs this to match the addressing modes of stack access instructions,
which is even more important at -O0 than with optimizations.
It currently costs nothing to run ahead of time, so just always enable
it.
Matt Arsenault [Wed, 1 Dec 2021 02:26:08 +0000 (21:26 -0500)]
RegScavenger: Remove used regs from scavenge candidates
In a future change, AMDGPU will have 2 emergency scavenging indexes in
some situations. The secondary scavenging index ends up being used
recursively when the scavenger calls eliminateFrameIndex for the
emergency spill slot. Without this, it would end up seeing the same
register which was just scavenged in the parent call as free, inserts
a second emergency spill to the same location and returns the same
register when 2 unique free registers are required.
We need to only do this if the register is used. SystemZ uses 2
scavenging slots, but calls the scavenger twice in sequence and not
recursively. In this case the previously scavenged register can be
re-clobbered, but is still tracked in the scavenger until it sees the
deferred restore instruction.
Matt Arsenault [Wed, 12 Jan 2022 20:01:27 +0000 (15:01 -0500)]
AMDGPU/GlobalISel: Fix assertions on legalize queries with huge align
For some reason we pass around the alignment in bits as uint64_t. Two
places were truncating it to unsigned, and losing bits in extreme
cases.
Matt Arsenault [Sun, 9 Jan 2022 22:42:09 +0000 (17:42 -0500)]
AMDGPU: Add base test for future optimization patch
Matt Arsenault [Tue, 4 Jan 2022 22:53:52 +0000 (17:53 -0500)]
IR: Make getRetAlign check callee function attributes
The attribute queries semi-consistently check the attribute set, and
then fallback to checking the callee's attributes.
Matt Arsenault [Tue, 4 Jan 2022 21:33:20 +0000 (16:33 -0500)]
GlobalISel: Add G_ASSERT_ALIGN hint instruction
Insert it for call return values only for now, which is the only case
the DAG handles also.
Arthur O'Dwyer [Tue, 11 Jan 2022 19:58:32 +0000 (14:58 -0500)]
[libc++] [ranges] Finish ADL-proofing ranges::data.
This should have been part of D116239.
Arthur O'Dwyer [Tue, 11 Jan 2022 16:05:41 +0000 (11:05 -0500)]
[libc++] [ranges] Fix a missing auto(x) cast in ranges::data.
Also remove some bogus `std::forward`s. My impression is that these
forwards were actually harmless, because `ranges::begin(FWD(t))` is
always identical to `ranges::begin(t)` (except when it's ill-formed,
and that can't happen in this case). However, they're also superfluous
and don't reflect the wording in the standard, so let's eliminate them.
Differential Revision: https://reviews.llvm.org/D117043
Amara Emerson [Wed, 12 Jan 2022 22:54:11 +0000 (14:54 -0800)]
[AArch64][GlobalISel] Re-generate checks for a test.
River Riddle [Mon, 3 Jan 2022 07:12:03 +0000 (23:12 -0800)]
[mlir] Add a parsePassPipeline overload that returns a new pass manager
This overload parses a pipeline string that contains the anchor operation type, and returns an OpPassManager
corresponding to the provided pipeline. This is useful for various situations, such as dynamic pass pipelines
which are not anchored within a parent pass pipeline.
fixes #52813
Differential Revision: https://reviews.llvm.org/D116525
Michael Jones [Wed, 12 Jan 2022 22:33:03 +0000 (14:33 -0800)]
[libc] fix strtold_test formatting on ARM
I missed a variable when reformatting the tests. This fixes that.
Differential Revision: https://reviews.llvm.org/D117161
Daniel McIntosh [Wed, 8 Dec 2021 18:22:52 +0000 (13:22 -0500)]
[libcxxabi] Added convenience classes to cxa_guard
This is the 5th of 5 changes to overhaul cxa_guard.
See D108343 for what the final result will be.
Depends on D115368
Reviewed By: ldionne, #libc_abi
Differential Revision: https://reviews.llvm.org/D115369
Daniel McIntosh [Wed, 8 Dec 2021 18:16:21 +0000 (13:16 -0500)]
[libcxxabi] Re-organized inheritance structure to remove CRTP in cxa_guard
Currently, the `InitByte...` classes inherit from `GuardObject` so they can
access the `base_address`, `init_byte_address` and `thread_id_address`. Then,
since `GuardObject` needs to call `acquire`/`release`/`abort_init_byte`, it uses
the curiously recurring template pattern (CRTP). This is rather messy.
Instead, we'll have `GuardObject` contain an instance of `InitByte`, and pass it
the addresses it needs in the constructor. `GuardObject` doesn't need the
addresses anyways, so it makes more sense for `InitByte` to keep them instead of
`GuardObject`. Then, `GuardObject` can call `acquire`/`release`/`abort` as one
of `InitByte`'s member functions.
Organizing things this way not only gets rid of the use of the CRTP, but also
improves separation of concerns a bit since the `InitByte` classes are no longer
indirectly responsible for things because of their inheritance from
`GuardObject`. This means we no longer have strange things like calling
`InitByteFutex.cxa_guard_acquire`, instead we call
`GuardObject<InitByteFutex>.cxa_guard_acquire`.
This is the 4th of 5 changes to overhaul cxa_guard.
See D108343 for what the final result will be.
Depends on D115367
Reviewed By: ldionne, #libc_abi
Differential Revision: https://reviews.llvm.org/D115368
Daniel McIntosh [Wed, 8 Dec 2021 17:53:03 +0000 (12:53 -0500)]
[libcxxabi] Pulled guard byte code out of GuardObject
Right now, GuardObject is in charge of both reading and writing to the guard
byte, and co-ordinating with the InitByte... classes. In order to improve
separation of concerns, create a separate class responsible for managing the
guard byte and use that inside GuardObject.
This is the 3rd of 5 changes to overhaul cxa_guard.
See D108343 for what the final result will be.
Depends on D110088
Reviewed By: ldionne, #libc_abi
Differential Revision: https://reviews.llvm.org/D115367
Daniel McIntosh [Mon, 16 Aug 2021 18:07:55 +0000 (14:07 -0400)]
[libcxxabi] Make InitByteGlobalMutex check GetThreadID instead of PlatformThreadID
By relying on PlatformSupportsThreadID, InitByteGlobalMutex disregards
the GetThreadID template argument, rendering it useless.
This is the 2nd of 5 changes to overhaul cxa_guard.
See D108343 for what the final result will be.
Depends on D109539
Reviewed By: ldionne, #libc_abi
Differential Revision: https://reviews.llvm.org/D110088
Daniel McIntosh [Wed, 11 Aug 2021 14:47:48 +0000 (10:47 -0400)]
[NFC][libcxxabi] Rename GlobalLock to GlobalMutex
This will make the naming more consistent with what it's called in the
rest of the file.
This is the 1st of 5 changes to overhaul cxa_guard.
See D108343 for what the final result will be.
Reviewed By: ldionne, #libc_abi
Differential Revision: https://reviews.llvm.org/D109539
Michael Jones [Wed, 12 Jan 2022 21:44:10 +0000 (13:44 -0800)]
[libc] add working ARM entrypoints
Some functions were added to x86_64 that were untested on Aarch64. Now
that I've had an opportunity to test them, they all work on Aarch64 with
the minor formatting change included.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D117146
natashaknk [Wed, 12 Jan 2022 22:10:27 +0000 (14:10 -0800)]
[tosa][mlir] Support dynamic batch dimension for ops where the batch dim is explicit
Dynamic batch for rescale, gather, max_pool, avg_pool, conv2D and depthwise_conv2D. Split helper functions into a separate header file.
Reviewed By: rsuderman
Differential Revision: https://reviews.llvm.org/D117031
River Riddle [Mon, 10 Jan 2022 18:55:57 +0000 (10:55 -0800)]
[mlir] Refactor ShapedType into an interface
ShapedType was created in a time before interfaces, and is one of the earliest
type base classes in the ecosystem. This commit refactors ShapedType into
an interface, which is what it would have been if interfaces had existed at that
time. The API of ShapedType and it's derived classes are essentially untouched
by this refactor, with the exception being the API surrounding kDynamicIndex
(which requires a sole home).
For now, the API of ShapedType and its name have been kept as consistent to
the current state of the world as possible (to help with potential migration churn,
among other reasons). Moving forward though, we should look into potentially
restructuring its API and possible its name as well (it should really have "Interface"
at the end like other interfaces at the very least).
One other potentially interesting note is that I've attached the ShapedType::Trait
to TensorType/BaseMemRefType to act as mixins for the ShapedType API. This
is kind of weird, but allows for sharing the same API (i.e. preventing API loss from
the transition from base class -> Interface). This inheritance doesn't affect any
of the derived classes, it is just for API mixin.
Differential Revision: https://reviews.llvm.org/D116962
River Riddle [Sat, 8 Jan 2022 01:41:06 +0000 (17:41 -0800)]
[mlir][Interfaces] Add a extraSharedClassDeclaration field
This field allows for defining a code block that is placed in both the interface
and trait declarations. This is very useful when defining a set of utilities to
expose on both the Interface class and the derived attribute/operation/type.
In non-static methods, `$_attr`/`$_op`/`$_type` (depending on the type of
interface) may be used to refer to an instance of the IR entity. In the interface
declaration, this is an instance of the interface class. In the trait declaration,
this is an instance of the concrete entity class (e.g. `IntegerAttr`, `FuncOp`, etc.).
Differential Revision: https://reviews.llvm.org/D116961
Rob Suderman [Wed, 12 Jan 2022 19:28:34 +0000 (11:28 -0800)]
[mlir][tosa] Expand tosa.apply_scale lowering for vectors
Apply scale may encounter scalar, tensor, or vector operations. Expand the
lowering so that it can lower arbitrary of container types.
Reviewed By: NatashaKnk
Differential Revision: https://reviews.llvm.org/D117080
Tomas Matheson [Mon, 13 Dec 2021 14:57:09 +0000 (14:57 +0000)]
clang support for Armv8.8/9.3 HBC
This introduces clang command line support for new Armv8.8-A and
Armv9.3-A Hinted Conditional Branches feature, previously introduced
into LLVM in https://reviews.llvm.org/D116156.
Patch by Tomas Matheson and Son Tuan Vu.
Differential Revision: https://reviews.llvm.org/D116939