Kenneth Graunke [Wed, 17 Jul 2019 00:22:01 +0000 (17:22 -0700)]
intel/mi: Add a unit test for gen_mi_store_if().
This tests that predicated stores work.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Kenneth Graunke [Mon, 1 Apr 2019 23:33:08 +0000 (16:33 -0700)]
intel/mi: Add a new gen_mi_store_if() helper.
This performs predicated MI_STORE_REGISTER_MEM commands, assuming that
the condition is already loaded into MI_PREDICATE_DATA.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Kenneth Graunke [Mon, 1 Apr 2019 23:01:50 +0000 (16:01 -0700)]
intel/mi: Add gen_mi_nz() and gen_mi_z() helpers.
These provide comparisons against zero.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Kenneth Graunke [Wed, 10 Jul 2019 19:05:23 +0000 (12:05 -0700)]
intel/mi: Add a gen_mi_ior() to go with gen_mi_iand()
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Kenneth Graunke [Mon, 1 Apr 2019 23:00:25 +0000 (16:00 -0700)]
intel/mi: Optimize away LOAD_REGISTER_REG from a register to itself
We might want to resolve something to be in a particular register,
so we can access it outside of the gen_mi framework...but it may already
be in that register, at which point there's no work to do.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Kenneth Graunke [Mon, 1 Apr 2019 18:16:22 +0000 (11:16 -0700)]
iris: Make iris_query.c a genxml-compiled file.
This will let us use Jason's new MI-builder shortly.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Kenneth Graunke [Mon, 1 Apr 2019 18:46:36 +0000 (11:46 -0700)]
iris: Move iris_resolve_conditional_render to the vtable.
It's going to be in genxml code shortly.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Kenneth Graunke [Fri, 12 Jul 2019 07:50:19 +0000 (00:50 -0700)]
iris: Refactor genxml macros and inlines into iris_genx_macros.h.
This will let us put the genxml boilerplate in one place, before we
expand genxml to more files shortly. Like i965/genX_boilerplate.h.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Kenneth Graunke [Mon, 1 Apr 2019 18:40:33 +0000 (11:40 -0700)]
iris: Make an iris_genx_protos.h header for prototypes.
This lets us specify the prototypes once, instead of cut and pasting
them per generation. isl uses a similar approach (isl_genX_priv.h).
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Marek Olšák [Wed, 24 Jul 2019 02:32:02 +0000 (22:32 -0400)]
radeonsi: fix DAL hang due to incorrect DCC offset on Raven
Set the correct relative offset.
Fixes: f8b6c5a "radeonsi: rewrite si_get_opaque_metadata, also for gfx10 support"
Jason Ekstrand [Thu, 25 Jul 2019 05:00:37 +0000 (00:00 -0500)]
anv: Disable subgroup arithmetic on gen7
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eric Anholt [Wed, 10 Apr 2019 22:59:12 +0000 (15:59 -0700)]
gitlab-ci: Add a shader-db run using v3d on drm-shim.
This provides significant compiler coverage during CI at a fairly low
cost in CPU time (~17s per thread for 4 threads on
gst-gitlab-htz-runner3).
I'm leaving wget in the docker image, as once this is in master I'm
planning on having an automatic shader-db comparison between master
and the branch included in the artifacts. I also haven't done
freedreno yet, because it has some races when run in multithreaded
mode that I'm still tracking down.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Eric Anholt [Wed, 24 Jul 2019 16:27:48 +0000 (09:27 -0700)]
gitlab-ci: Only keep the build logs as artifacts.
On a build failure, we were tarring up the whole ccache directory,
build.ninja, build products, etc. This was over 400MB compressed on a
recent early meson-main build failure, which fd.o then has to hang on
to for 4 weeks. The build logs are probably the interesting part, are
potentially useful regardless ("how did CI's build flags differ from
mine?"), and are <500k uncompressed on my personal meson build.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Eric Anholt [Tue, 23 Jul 2019 18:12:07 +0000 (11:12 -0700)]
gitlab-ci: Always set libdir to lib/
I introduced libdir for cross-builds so we could point at the
resulting drivers without per-arch dependencies, but I'd rather not
have to type x86_64-linux-whatever for non-cross-builds either.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Eric Anholt [Mon, 13 May 2019 21:03:07 +0000 (14:03 -0700)]
freedreno: Add support for drm-shim.
I'm using this for shader-db analysis on x86_64 systems.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Eric Anholt [Wed, 26 Sep 2018 02:15:45 +0000 (19:15 -0700)]
v3d: Introduce a DRM shim for calling out to the simulator.
The goal is to enable testing of parts of drivers without depending on any
particular kernel version or hardware being present.
Simply set LD_PRELOAD=$PREFIX/lib/libv3d_drm_shim.so in your environment,
and we'll fake a /dev/dri/renderD128 (or whatever the next available node
is) using v3dv3. That node can then be used with the surfaceless or gbm
EGL platforms.
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Erik Faye-Lund [Thu, 13 Jun 2019 10:03:27 +0000 (12:03 +0200)]
glsl: report no function instead of empty candidate list
When generating the error message for a missing function error where
all available overloads were missing due to a too low GLSL version, we
used to report something like this:
---8<---
0:224(14): error: no matching function for call to
`textureCubeLod(samplerCube, vec3, float)'; candidates are:
0:224(14): error: type mismatch
---8<---
This is a pretty confusing error message, and can throw people off when
debugging. So let's instead check if any overload is available before we
decide what to print. This allow us to report something like this
instead:
---8<---
0:224(14): error: no function with name 'textureCubeLod'
0:224(14): error: type mismatch
---8<---
This is arguably easier to understand for programmers, and doesn't send
you on a wild goose chase to figure out what argument is wrong just
because you stopped reading the message prematurely. I'm of course
referring to a friend, not me. For sure. I would never do that.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Bas Nieuwenhuizen [Thu, 25 Jul 2019 14:53:34 +0000 (16:53 +0200)]
radv: Set correct metadata size for GFX9+.
Without correct size, radeonsi assumes the metadata is incorrect,
which can and will cause issues.
Since the metadata is really incorrect without the size, let us
fix that.
Fixes:
e43cc3e3afc "radv/gfx9: handle GFX9 opaque metadata"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Arcady Goldmints-Orlov [Tue, 23 Jul 2019 19:36:48 +0000 (14:36 -0500)]
anv: report HOST_ALLOCATION as supported for images
Report VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT as
supported for images. It was being shown supported for buffers, but not
images.
Fixes:
69cc6272fbc1 ("anv: Implement VK_EXT_external_memory_host")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Samuel Pitoiset [Wed, 24 Jul 2019 14:50:38 +0000 (16:50 +0200)]
radv/gfx10: fix intensity formats by setting ALPHA_IS_ON_MSB
This fixes
dEQP-VK.rasterization.primitive_size.points.point_size_*
This also fixes some black squares with the Sascha SSAO demo.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 25 Jul 2019 13:38:51 +0000 (15:38 +0200)]
radv/gfx10: use L2 for DMA copy/fill operations
It's coherent and faster. GFX7-GFX9 should also support this but
for now only uses L2 for GFX10 because it's untested on previous gens.
This fixes dEQP-VK.memory.pipeline_barrier.transfer_*
This also fixes some missing geometry in Dawn Of War III because
VBOs weren't updated correctly.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Alyssa Rosenzweig [Wed, 24 Jul 2019 22:37:24 +0000 (15:37 -0700)]
pan/midgard: Optimize varying projection
We add a new opt pass fusing perspective projection with varyings. Minor
win..? We don't combine non-varying projections, since if we're too
agressive, the extra load/store traffic will hurt us so it's not really
a win in practice.
total instructions in shared programs: 3915 -> 3913 (-0.05%)
instructions in affected programs: 76 -> 74 (-2.63%)
helped: 1
HURT: 0
total bundles in shared programs: 2520 -> 2519 (-0.04%)
bundles in affected programs: 46 -> 45 (-2.17%)
helped: 1
HURT: 0
total quadwords in shared programs: 4027 -> 4025 (-0.05%)
quadwords in affected programs: 80 -> 78 (-2.50%)
helped: 1
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 03:02:56 +0000 (20:02 -0700)]
pan/midgard: Add perspective projection recombine pass
We don't use it yet, since it's actually a shader-db regression. This is
primarily helpful as an intermediate step for attaching projection to
varyings.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 22:36:46 +0000 (15:36 -0700)]
pan/midgard: Force perspective ops to use vec4
It doesn't make sense to use them with anything less.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 21:58:46 +0000 (14:58 -0700)]
pan/midgard: Add R27-only op handling
We use a special conflicting register class.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 21:52:57 +0000 (14:52 -0700)]
pan/midgard: Add OP_R27_ONLY helper
While load/store ops like st_vary can take an argument in either
r26/r27, ops like those for perspective projection must specifically
take their argument in r27.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:54:59 +0000 (12:54 -0700)]
pan/midgard: Enable RA for st_vary
Now that all the piping is in place to do so without regressions, we
flip on automatic register allocation for varyings. Hooray!
total instructions in shared programs: 4025 -> 3915 (-2.73%)
instructions in affected programs: 1667 -> 1557 (-6.60%)
helped: 62
HURT: 0
helped stats (abs) min: 1 max: 3 x̄: 1.77 x̃: 2
helped stats (rel) min: 0.93% max: 20.00% x̄: 10.80% x̃: 10.64%
95% mean confidence interval for instructions value: -1.89 -1.66
95% mean confidence interval for instructions %-change: -12.50% -9.11%
Instructions are helped.
total bundles in shared programs: 2683 -> 2520 (-6.08%)
bundles in affected programs: 1066 -> 903 (-15.29%)
helped: 62
HURT: 0
helped stats (abs) min: 1 max: 3 x̄: 2.63 x̃: 3
helped stats (rel) min: 2.94% max: 42.86% x̄: 23.85% x̃: 22.50%
95% mean confidence interval for bundles value: -2.83 -2.43
95% mean confidence interval for bundles %-change: -27.73% -19.97%
Bundles are helped.
total quadwords in shared programs: 4192 -> 4027 (-3.94%)
quadwords in affected programs: 1584 -> 1419 (-10.42%)
helped: 62
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 2.66 x̃: 3
helped stats (rel) min: 1.85% max: 30.00% x̄: 16.49% x̃: 16.52%
95% mean confidence interval for quadwords value: -2.87 -2.46
95% mean confidence interval for quadwords %-change: -19.14% -13.84%
Quadwords are helped.
total registers in shared programs: 433 -> 411 (-5.08%)
registers in affected programs: 67 -> 45 (-32.84%)
helped: 23
HURT: 1
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 25.00% max: 50.00% x̄: 41.30% x̃: 50.00%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 14.29% max: 14.29% x̄: 14.29% x̃: 14.29%
95% mean confidence interval for registers value: -1.09 -0.74
95% mean confidence interval for registers %-change: -45.45% -32.52%
Registers are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 21:10:12 +0000 (14:10 -0700)]
pan/midgard: Remove check for `class`
Fixes classes defaulting to vec4 in some cases.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 20:29:36 +0000 (13:29 -0700)]
pan/midgard: Move uniforms to special registers
The load/store pipes can't take a uniform register in, so an explicit
move is necessary here.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:53:58 +0000 (12:53 -0700)]
pan/midgard: Emit st_vary registers in install_registers
Now that we have its registers handled normally like the rest of the IR.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:53:08 +0000 (12:53 -0700)]
pan/midgard: Add mir_lower_special_reads helper
Given the constraints on special registers, we add a helper for lowering
these by inserting moves (copies) where needed to satsify the ISA
constraints.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:52:27 +0000 (12:52 -0700)]
pan/midgard: Add emit_explicit_constant helper
We generalize the constant emission helper used in fragment writeout as
we'll also need it for vertex outputs.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 19:51:51 +0000 (12:51 -0700)]
pan/midgard: Add mir_rewrite_index_src_tag
Specialized version of a rewrite that only rewrites a certain type of
instruction.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 18:33:26 +0000 (11:33 -0700)]
pan/midgard: Add class check
This ensures the rules for accessing special register classes are
satisfied. This is asserted as a prepass should have lowered offending
uses to something satisfying these rules. Special register classes are
*not* work registers and cannot be used for RMW operations; they are
essentially 1-way pipes straight into/from fixed-function logic in the
shader cores.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 18:16:48 +0000 (11:16 -0700)]
pan/midgard: Implement class spilling
We reuse the same register spilling mechanism as for work->memory to
spill special->work registers, e.g. to allow writing out more than 2
vec4 varyings (without better scheduling anyway).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 18:16:15 +0000 (11:16 -0700)]
pan/midgard: Extend liveness analysis to st_vary
These can consume sources now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 17:03:24 +0000 (10:03 -0700)]
pan/midgard: Implement load/store register classing
This does not yet support special->work spilling, nor does it support
multiclass breakup. These corner cases will be handled in succeeding
commits.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 15:31:46 +0000 (08:31 -0700)]
pan/midgard: Allocate special register classes
We'll want to also handle load/store and texture registers in our RA
loop.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 14:23:19 +0000 (07:23 -0700)]
pan/midgard: Move copy propagation into its own file
We also expose some utilities it uses as general MIR helpers.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 03:02:06 +0000 (20:02 -0700)]
pan/midgard: Add mir_simple_swizzle helper
Checks for x/xy/xyz/xyzw style swizzles (slightly more general but you
get the idea).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 03:01:44 +0000 (20:01 -0700)]
pan/midgard: Add mir_single_use helper
Helps as an optimization heuristic.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 00:02:38 +0000 (17:02 -0700)]
panfrost: Compute I/O counts from shader_info
...rather than exposing it in the vendored compiler region.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 23 Jul 2019 23:55:38 +0000 (16:55 -0700)]
panfrost: Don't DIY point size/coord fields
Again, it's in shader_info for us!
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 23 Jul 2019 23:52:40 +0000 (16:52 -0700)]
panfrost: Use nir_gather_info information about discards
No need to track this ourselves!
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 23 Jul 2019 23:49:37 +0000 (16:49 -0700)]
panfrost: Use NIR helper invocations info
We don't need to guesstimate this ourselves. This will help when we
bringup derivatives.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 15:39:39 +0000 (08:39 -0700)]
panfrost/sfbd: Flesh out fragment job
We include a zsbuf attachment function based on how the corresponding
MFBD code works, as well as extending cbufs to mipmapped rendering while
we're at it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 15:41:04 +0000 (08:41 -0700)]
panfrost: Disable tiled formats on SFBD systems
Just because we don't have the format codes to render to them yet.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 15:46:15 +0000 (08:46 -0700)]
panfrost: Move require_sfbd to screen
We'll need it to specialize resource creation by chip.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 23 Jul 2019 17:14:46 +0000 (10:14 -0700)]
panfrost: Reserve, but do not upload, shader padding
Fixes invalid read errors reported by valgrind.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 18:19:21 +0000 (11:19 -0700)]
util/ra: Add a getter for a node class
Complements the existing getters and the setter for node class. To be
used in the Panfrost RA refactor.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tomeu Vizoso [Thu, 25 Jul 2019 09:58:08 +0000 (11:58 +0200)]
panfrost/ci: Update kernel to 5.2
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Nicolas Dufresne [Sun, 14 Jul 2019 18:48:11 +0000 (14:48 -0400)]
egl: Also query modifiers when exporting DMABuf
This fixes eglExportDMABUFImageQueryMESA() so it will report the
modififers of the underlying image. Without this information,
re-importing will likely be broken as it is rare these days that no
modifiers are used.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Fixes:
8f7338f284cdb1fef64c ("egl: add initial EGL_MESA_image_dma_buf_export v2.4")
Heinrich Fink [Tue, 4 Jun 2019 15:19:47 +0000 (17:19 +0200)]
mesa: Enable GL_MESA_framebuffer_flip_y for GL 4.3
Extend MESA_framebuffer_flip_y to be used with OpenGL versions 4.3 and
higher. OpenGL 4.3 adds FramebufferParameteri needed by this extension.
Reviewed-by: Fritz Koenig <frkoenig@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Alyssa Rosenzweig [Wed, 24 Jul 2019 02:18:44 +0000 (19:18 -0700)]
panfrost: Don't expose some atomic stuff even with dEQP
Fixes dEQP crashes.
Fixes:
2f93ecd654e ("panfrost: Fake CAPs for dEQP-GLES31")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Dave Airlie [Wed, 24 Jul 2019 23:33:36 +0000 (09:33 +1000)]
gallium: fix windows build from params change.
This is why we can't have nice things. I'm sure there's someway
to do this with {0} but I really don't have time for that.
Fixes:
2631fd3b0bf ("gallivm: rework lp_build_tgsi_soa to take a struct")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Jonathan Marek [Wed, 24 Jul 2019 17:33:17 +0000 (13:33 -0400)]
nir/algebraic: add scmp algebraic optimizations
When 'x' is the result of a scmp op:
x != 0.0 or x == 1.0: passthrough
x == 0.0 or x != 1.0: invert
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jonathan Marek [Sun, 2 Jun 2019 22:44:49 +0000 (18:44 -0400)]
nir/algebraic: add option to lower fall_equalN/fany_nequalN
Add generic lowerings for fall_equalN/fany_nequalN. These should be optimal
for vec4 backends that doesn't have any special instructions for it, as
long as they support saturate.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jonathan Marek [Fri, 21 Jun 2019 01:56:29 +0000 (21:56 -0400)]
nir/algebraic: add fdot2 optimizations
Add simple fdot2 optimizations that are missing.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jonathan Marek [Fri, 21 Jun 2019 01:47:16 +0000 (21:47 -0400)]
nir/algebraic: add option to lower fdph
For backends that don't have a 'fdph' instructions
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jonathan Marek [Wed, 8 May 2019 14:26:49 +0000 (10:26 -0400)]
nir: replace lower_sincos with algebraic opt
This version has less ops for the same precision.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Jonathan Marek [Fri, 21 Jun 2019 01:23:53 +0000 (21:23 -0400)]
nir/algebraic: allow swizzle in nir_algebraic replace expression
This is to allow optimizations in nir_opt_algebraic not otherwise possible
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Rob Clark [Mon, 22 Jul 2019 21:23:52 +0000 (14:23 -0700)]
gallium/u_transfer_helper: fix assert in RGTC case
Previously we'd hit the unreachable() for uploading RGTC.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Yevhenii Kolesnikov [Tue, 23 Jul 2019 15:35:29 +0000 (18:35 +0300)]
main: Free memory allocated for gl_bitmap_atlas structure
Structure itself wasn't freed during context tear-down, causing a
memory leak on iris.
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Daniel Schürmann [Thu, 18 Jul 2019 11:39:49 +0000 (13:39 +0200)]
nir,intel: lower if (cond) demote() to new intrinsic demote_if(cond)
This will effectively enable the optimization in anv.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Sun, 21 May 2017 08:36:14 +0000 (01:36 -0700)]
i965: Use NIR to lower legacy userclipping.
This allows us to drop legacy userclip plane handling in both the vec4
and FS backends, and simplifies a few interfaces.
v2 (Jason Ekstrand):
- Move brw_nir_lower_legacy_clipping to brw_nir_uniforms.cpp because
it's i965-specific.
- Handle adding the params in brw_nir_lower_legacy_clipping
- Call brw_nir_lower_legacy_clipping from brw_codegen_vs_prog
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 21 Feb 2019 20:50:10 +0000 (14:50 -0600)]
anv: Implement VK_EXT_subgroup_size_control
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 22 Feb 2019 21:21:13 +0000 (15:21 -0600)]
anv/pipeline: Plumb pipeline shader stage create flags
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Tue, 9 Jul 2019 19:28:18 +0000 (14:28 -0500)]
intel/compiler: Allow for required subgroup sizes
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 22 Feb 2019 21:28:24 +0000 (15:28 -0600)]
intel/compiler: Allow for varying subgroup sizes
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Thu, 11 Jul 2019 03:20:00 +0000 (22:20 -0500)]
nir/lower_subgroups: Properly lower masks when subgroup_size == 0
Instead of building a constant mask (which depends on knowing the
subgroup size), we build an expression. Because the pass uses the
nir_shader_lower_instructions helper, subgroup lowering will be run on
any newly emitted instructions as well as the previously existing
instructions. In particular, if the subgroup size is known, the newly
emitted subgroup_size intrinsic will get turned into a constant and a
later constant folding pass will clean it up.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Thu, 4 Jul 2019 20:10:23 +0000 (15:10 -0500)]
vulkan: Update the XML and headers to 1.1.116
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 22 Feb 2019 16:48:39 +0000 (10:48 -0600)]
intel/compiler: Be more conservative about subgroup sizes in GL
The rules for gl_SubgroupSize in Vulkan require that it be a constant
that can be queried through the API. However, all GL requires is that
it's a uniform. Instead of always claiming that the subgroup size in
the shader is 32 in GL like we have to do for Vulkan, claim 8 for
geometry stages, the maximum for fragment shaders, and the actual size
for compute.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Thu, 21 Feb 2019 21:29:12 +0000 (15:29 -0600)]
intel/compiler: Lower gl_SubgroupSize in postprocess_nir
Instead of lowering the subgroup size so early, wait until we have more
information. In particular, we're going to want different subgroup
sizes from different stages depending on the API. We also defer
lowering of subgroup masks because the ge/gt masks require the subgroup
size to generate a subgroup mask.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Jason Ekstrand [Fri, 22 Feb 2019 17:15:21 +0000 (11:15 -0600)]
intel/nir: Make brw_nir_apply_sampler_key more generic
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Sagar Ghuge [Tue, 16 Apr 2019 06:06:23 +0000 (23:06 -0700)]
nir: Add lowering for nir_op_irem and nir_op_imod
Tested on Gen > 9.
v2: 1) Fix lowering
2) Keep a consistent i/u order (Matt Turner)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Yevhenii Kolesnikov [Thu, 11 Jul 2019 10:00:46 +0000 (13:00 +0300)]
main: Fix memleaks in mesa_use_program
Add freeing of SubroutineIndexes to the _mesa_free_shader_state.
Fixes:
4566aaaa5b1 ("mesa/subroutines: start adding per-context
subroutine index support (v1.1)")
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Andrii Simiklit [Tue, 23 Jul 2019 11:48:58 +0000 (14:48 +0300)]
intel/compiler: don't use a keyword struct for a class fs_reg
warning: struct 'fs_reg' was previously declared as a class
Fixes:
e64be391 ("intel/compiler: generalize the combine constants pass")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Qiang Yu [Sat, 20 Jul 2019 10:11:07 +0000 (18:11 +0800)]
lima/ppir: fix disassembler temp read/write print
temp read/write use negtive offset, and handle
alignment==1 case.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Eric Engestrom [Tue, 23 Jul 2019 09:01:44 +0000 (10:01 +0100)]
gallium+mesa: fix tgsi_semantic array type
Fixes:
ed23335a313dfc9cec26 ("gallium: use enums in p_shader_tokens.h (v2)")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Eric Engestrom [Tue, 23 Jul 2019 09:03:26 +0000 (10:03 +0100)]
util: fix no-op macro (bad number of arguments)
Fixes:
b8e077daee4d6369d774 ("util: no-op __builtin_types_compatible_p() for non-GCC compilers")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Pitoiset [Tue, 23 Jul 2019 12:53:34 +0000 (14:53 +0200)]
radv/gfx10: enable VK_EXT_transform_feedback
When a pipeline uses transform feedback, the driver fallbacks to
the legacy path because NGG support for streamout is a non-trivial
amount of work.
AMDVLK also uses the legacy path for streamout, while RadeonSI
uses the new NGG path.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 23 Jul 2019 13:12:42 +0000 (15:12 +0200)]
radv/gfx10: do not enable NGG if a pipeline uses XFB
NGG GS for streamout requires a bunch of work, so enable it with
the legacy path only for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 23 Jul 2019 12:55:16 +0000 (14:55 +0200)]
radv/gfx10: emit streamout shader config
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 23 Jul 2019 12:53:45 +0000 (14:53 +0200)]
radv/gfx10: declare streamout user SGPRs
Required for legacy streamout.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 23 Jul 2019 08:12:13 +0000 (10:12 +0200)]
radv/gfx10: update streamout descriptors
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 23 Jul 2019 09:52:36 +0000 (11:52 +0200)]
radv/gfx10: fix VS input VGPRs with the legacy path
For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Mon, 22 Jul 2019 02:04:27 +0000 (12:04 +1000)]
gallivm: rework lp_build_tgsi_soa to take a struct
The parameters were getting messy and I have to add a few more
for compute shaders, so clean it up before proceeding.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jason Ekstrand [Fri, 19 Jul 2019 20:30:27 +0000 (15:30 -0500)]
nir/lower_io: Return SSA defs from helpers
I can't find a single place where nir_lower_io is called after going out
of SSA which is the only real reason why you wouldn't do this. Returning
SSA defs is more idiomatic and is required for the next commit.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Dylan Baker [Mon, 1 Jul 2019 17:04:03 +0000 (10:04 -0700)]
meson: allow building all glx without any drivers
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111016
Fixes:
a47c525f3281a2753180e076c7e9b7772aff8f06
("meson: build glx")
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Jan Zielinski [Tue, 23 Jul 2019 10:47:28 +0000 (12:47 +0200)]
swr/rasterizer: Fix 3D resource copies.
Ensure constant attributes stay constant with barycentric interpolation.
Reviewed-by: Alok Hota <alok.hota@intel.com>
Jan Zielinski [Tue, 23 Jul 2019 10:31:35 +0000 (12:31 +0200)]
swr/rasterizer: Fix return type on SIMD8 version of Clamp and Normalize utility functions
Reviewed-by: Alok Hota <alok.hota@intel.com>
Jan Zielinski [Tue, 23 Jul 2019 10:18:03 +0000 (12:18 +0200)]
swr/rasterizer: small formatting changes
Reviewed-by: Alok Hota <alok.hota@intel.com>
Jan Zielinski [Tue, 23 Jul 2019 08:30:47 +0000 (10:30 +0200)]
swr/rasterizer: Adding support for unhandled clipEnable state
Clipping is not correctly handled by the rasterizer - fixing this.
Reviewed-by: Alok Hota <alok.hota@intel.com>
Bas Nieuwenhuizen [Sun, 21 Jul 2019 01:40:00 +0000 (03:40 +0200)]
radv/gfx10: Enable binning.
Numbers for Talos:
gfx10 without binning: 77.0 77.7 77.2 77.6
gfx10 with binning: 82.3 82.0 82.7 82.4
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Sat, 20 Jul 2019 23:38:13 +0000 (01:38 +0200)]
radv/gfx10: Implement bin size calculation.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Fri, 19 Jul 2019 22:58:12 +0000 (00:58 +0200)]
radv/gfx9: Select between depth/color bins based on area.
Mirrors radeonsi.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 18 Jul 2019 23:54:24 +0000 (01:54 +0200)]
radv: Generalize binning settings.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 18 Jul 2019 23:18:28 +0000 (01:18 +0200)]
radv/gfx10: Use new scan converter.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Thu, 18 Jul 2019 23:48:47 +0000 (01:48 +0200)]
radv: Set FLUSH_ON_BINNING_TRANSITION.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Thu, 18 Jul 2019 23:10:36 +0000 (01:10 +0200)]
radv: Use pbb_allow for framebuffer BREAK_BATCH.
Ported from radeonsi.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>