Bas Nieuwenhuizen [Sat, 19 Sep 2020 12:00:05 +0000 (14:00 +0200)]
radv: Implement VK_KHR_zero_initialize_workgroup_memory.
Reuses the pass that was implemented for ANV.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8751>
Caio Marcelo de Oliveira Filho [Tue, 2 Feb 2021 07:19:13 +0000 (23:19 -0800)]
spirv: Fail when parsing invalid Initializers
Fail when parsing Initializers used in Variables with Storage Classes
that doesn't support it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8820>
Dave Airlie [Wed, 3 Feb 2021 04:17:46 +0000 (14:17 +1000)]
zink: don't pick a cpu device ever.
This goes down the list and picks the first non-cpu device, when
we merge the CI patch we should add a forcing env var in here.
Fixes: 8d46e35d1 ("zink: introduce opengl over vulkan")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8845>
Marek Olšák [Sun, 24 Jan 2021 06:14:54 +0000 (01:14 -0500)]
winsys/amdgpu: expand the slab allocation range to [256 B, 1 MB]
This increases the wasted memory to 140 MB for DeusExMD, still below
the original number. The advantage is that we now get 2 MB pages for more
buffers and fewer total buffers allocated by the kernel, enabling faster
GPU page translation and slightly lower kernel overhead.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8683>
Marek Olšák [Sun, 24 Jan 2021 02:53:30 +0000 (21:53 -0500)]
winsys/amdgpu,pb_slab: add slabs with 3/4 of power of two sizes to save memory
Instead of aligning slab allocations to powers of two (e.g. 129K -> 256K),
implement slab allocations with 3/4 of power of two sizes to reduce
overallocation. (e.g. 129K -> 192K)
The limitation is that the alignment must be 1/3rd of the allocation size.
DeusExMD allocates 2.1 GB of VRAM. Without this, slabs waste 194 MB due
to alignment, i.e. 9.2%. This commit reduces the waste to 102 MB, i.e. 4.9%.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8683>
Marek Olšák [Sun, 24 Jan 2021 02:43:05 +0000 (21:43 -0500)]
winsys/amdgpu: clean up slab alignment code, handle small buffers better
The next commit will build upon this.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8683>
Marek Olšák [Sat, 23 Jan 2021 22:21:44 +0000 (17:21 -0500)]
winsys/amdgpu,radeonsi: add HUD counters for how much memory is wasted by slabs
Slabs always allocate the next power of two size from their pools. This
wastes memory if the size is not a power of two.
bo->base.size is overwritten because the default is the allocated power of
two size, but we need the real size to compute the wasted size in
amdgpu_bo_slab_destroy. entry_size is added to the hole in pb_slab_entry
to hold the real entry size.
Like other memory stats, no atomics are used.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8683>
Samuel Pitoiset [Tue, 2 Feb 2021 18:52:09 +0000 (19:52 +0100)]
radv: fix waiting on the last enabled RB for occlusion queries
Wait on the last enabled RB, not the last RB. This fixes GPU hangs
because the GPU was waiting forever.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4212
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8836>
Rob Clark [Tue, 2 Feb 2021 20:32:22 +0000 (12:32 -0800)]
freedreno: Put an upper limit on VSC size
Left unchecked, an app that just did an endless series of draws could
result in VSC buffer sizes >4GB, which doesn't work out well.
This limit is semi-arbitrary (ie. it is lower than hw limit, but 32*8MB
seems a bit excessive and not a limit that you'd hit in the real world).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8842>
Rob Clark [Tue, 2 Feb 2021 20:12:14 +0000 (12:12 -0800)]
freedreno/decode: Fix overflow
CP_SET_DRAW_STATE state-groups count as a 4th level of IB. Fixes a
crash seen on 32b/arm builds of crashdec.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8842>
Samuel Iglesias Gonsálvez [Wed, 13 Jan 2021 08:06:51 +0000 (08:06 +0000)]
turnip: fix resolve MSAA D32_SFLOAT_S8_UINT image to S8_UINT
According to VK_KHR_depth_stencil_resolve spec (see
VUID-VkSubpassDescriptionDepthStencilResolve-pDepthStencilResolveAttachment-03182):
"If the VkFormat of pDepthStencilResolveAttachment has a stencil
component, then the VkFormat of pDepthStencilAttachment must have a
stencil component with the same number of bits and numerical
type"
The issue with D32_SFLOAT_S8_UINT format is that it is implemented as
two planes, so we need to execute the separate_stencil path in
tu_emit_blit() to resolve its stencil component into S8_UINT image.
Fixes the following tests:
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8527>
Samuel Iglesias Gonsálvez [Tue, 12 Jan 2021 21:31:33 +0000 (21:31 +0000)]
turnip: fix resolve MSAA D24_UNORM_S8_UINT image to S8_UINT
According to VK_KHR_depth_stencil_resolve spec (see
VUID-VkSubpassDescriptionDepthStencilResolve-pDepthStencilResolveAttachment-03182)
"If the VkFormat of pDepthStencilResolveAttachment has a stencil
component, then the VkFormat of pDepthStencilAttachment must have a
stencil component with the same number of bits and numerical type"
That means that we can resolve MSAA depth/stencil to a stencil only
image only if the stencil component matches with same number of bits
and type.
Although the driver only supports VK_RESOLVE_MODE_SAMPLE_ZERO_BIT
resolve mode, it was doing a sample average when resolving a MSAA
D24_UNORM_S8_UINT image to S8_UINT.
Fixes the following tests:
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.compatibility_depth_zero_stencil_zero_testing_s
tencil
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.compatibility_depth_zero_stenc
il_zero_testing_stencil
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8527>
Tapani Pälli [Tue, 2 Feb 2021 09:33:23 +0000 (11:33 +0200)]
i965: use aligned malloc for context instead of ralloc
Fixes: 3175b63a ("mesa: don't allocate matrices with malloc")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4118
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8805>
Tapani Pälli [Tue, 2 Feb 2021 09:26:16 +0000 (11:26 +0200)]
intel/perf: introduce additional ralloc context parameter
This makes it possible to use a separate ralloc context, not gl context
itself which might not be allocated with ralloc.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8805>
Tapani Pälli [Tue, 2 Feb 2021 09:21:37 +0000 (11:21 +0200)]
intel/perf: cleanup, remove duplicate function declaration
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8805>
Bas Nieuwenhuizen [Tue, 2 Feb 2021 12:15:20 +0000 (13:15 +0100)]
radv: Fix assert.
Fixes: 7f7da82dbb7 ("radv: Add image layout with drm format modifiers.")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8828>
Bas Nieuwenhuizen [Tue, 2 Feb 2021 12:13:29 +0000 (13:13 +0100)]
radv: Add modifier fails for CTS bug.
Fixes: 58e52326254 ("radv: Enable DRM format modifiers on GFX9+.")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8828>
Witold Baryluk [Thu, 28 Jan 2021 17:52:06 +0000 (17:52 +0000)]
radv: memset the alignment hole in cache_entry to 0
Detected using valgrind. Otherwise these bytes at the end
will be touched by zstd compression, spamming valgrind output.
Other option is to do full memset(entry, 0, size),
but that is somehow unnecessary and suboptimal.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8229>
Samuel Iglesias Gonsálvez [Wed, 3 Feb 2021 08:36:52 +0000 (09:36 +0100)]
turnip: fix UINT64_MAX size wrapping in tu_GetBufferMemoryRequirements()
tu_GetBufferMemoryRequirements() ends up wrapping the UINT64_MAX size
to 0 when aligning.
Fixes:
dEQP-VK.api.buffer.basic.size_max_uint64
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4493>
Samuel Iglesias Gonsálvez [Thu, 9 Apr 2020 08:16:51 +0000 (10:16 +0200)]
turnip: set sparseAddressSpaceSize to zero
According to Vulkan spec, "Table 46. Required Limits", as sparse
binding is unsupported, we need to return unsupported limit for
sparseAddressSpaceSize, which is zero.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4493>
Alyssa Rosenzweig [Mon, 18 Jan 2021 19:13:32 +0000 (14:13 -0500)]
pan/decode: Prefer sizeof to ARRAY_SIZE for char
One less macro.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 19:12:40 +0000 (14:12 -0500)]
pan/decode: Remove tile range validation
Fault pointer works as you expect so it's not terribly useful.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 19:10:13 +0000 (14:10 -0500)]
pan/mdg: Drop unused stage parameter to disassembler
No longer used but was adding a dependency on compiler/shader_enums.h
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 18:12:51 +0000 (13:12 -0500)]
pan/decode: Remove mesa header dependencies
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 18:11:49 +0000 (13:11 -0500)]
pan/decode: Remove unused disasm stats
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 18:11:02 +0000 (13:11 -0500)]
pan/decode: Remove pandecode_prop
For pre-GenXML printing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 18:08:56 +0000 (13:08 -0500)]
pan/decode: Simplify tiler printing
Again, most of this is either wrong or doesn't really matter.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 18:03:39 +0000 (13:03 -0500)]
pan/decode: Remove unused MEMORY_PROP macro
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 18:03:05 +0000 (13:03 -0500)]
pan/decode: Deduplicate shader property printing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 18:01:55 +0000 (13:01 -0500)]
pan/decode: Deduplicate SFBD blend printing
Annoying verbosity of traces on midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 17:59:22 +0000 (12:59 -0500)]
pan/decode: Remove dependency of decoder on the encoder
Obstacle to decouple panwrap from the rest of mesa.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 17:58:54 +0000 (12:58 -0500)]
pan/decode: Remove tiler size checks
Bad dependency and also mostly speculation at the time of writing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Alyssa Rosenzweig [Mon, 18 Jan 2021 17:58:36 +0000 (12:58 -0500)]
pan/decode: Be explicit when printing invocations
Our "canonical" forms weren't really... good.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8829>
Jonathan Marek [Tue, 26 Jan 2021 03:08:57 +0000 (22:08 -0500)]
turnip: add missing register write to disable dithering
This was causing rendering issues with low precision formats because GL
driver can enable it.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8707>
Jonathan Marek [Tue, 26 Jan 2021 03:06:26 +0000 (22:06 -0500)]
turnip: don't always use 3d ops for blit_image
Revert this accidentally committed testing change.
Fixes: 872c4bcd27db ("turnip: implement z-scaling and z-mirroring BlitImage")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8707>
Jonathan Marek [Sat, 23 Jan 2021 03:04:45 +0000 (22:04 -0500)]
turnip: IMAGE_FILTER_{LINEAR,CUBIC}_BIT only for non-integer formats
Avoid CTS trying to use linear filtering for integer formats.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8707>
Jonathan Marek [Wed, 16 Sep 2020 13:56:33 +0000 (09:56 -0400)]
turnip: use vk_format_is_int to disable COLOR_ATTACHMENT_BLEND_BIT
This is simpler and easier to understand.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8707>
Jonathan Marek [Sat, 23 Jan 2021 02:57:19 +0000 (21:57 -0500)]
turnip: delete unused vk_format_parse.py file
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8707>
Jonathan Marek [Sat, 23 Jan 2021 02:56:24 +0000 (21:56 -0500)]
turnip: fix logicOp
Don't ignore logic op for integer formats.
Blend also doesn't need this path, because it isn't valid for blendEnable
to be true for integer formats.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8707>
Rhys Perry [Tue, 2 Feb 2021 11:13:11 +0000 (11:13 +0000)]
radv: correctly enable WGP_MODE for tessellation control
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8811>
Rhys Perry [Mon, 1 Feb 2021 15:01:57 +0000 (15:01 +0000)]
radv: correctly enable WGP_MODE for NGG and GS
Previously, we would set WGP_MODE on GFX10+ and then only on GFX10.
Because we used bitwise or, the result was WGP_MODE being set on GFX10+.
We also set the wrong bit, S_00B848_WGP_MODE instead of S_00B228_WGP_MODE.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8811>
Rhys Perry [Mon, 30 Nov 2020 15:44:08 +0000 (15:44 +0000)]
radv: round-up num_records division in radv_flush_vertex_descriptors
Vertex attribute bounds checking is supposed to be done per-attribute:
is_oob = index * stride + attrib_offset + attrib_size > buffer_size
but we were obtaining num_records by dividing the buffer size by the
stride, making it per-vertex:
is_oob = index * stride + (stride - 1) >= buffer_size
An example from Dead Cells (Wine) is:
attribute bindings: 0, 1, 2
attribute formats: r32g32, r32g32, r32g32b32a32
attribute offsets: 0, 0, 0
binding buffers: all the same buffer
binding offsets: 0, 8, 16
binding sizes: 128, 120, 112
binding strides: 32, 32, 32
Workaround this issue without switching to per-attribute descriptors by
rounding up the division. This is still incorrect, but it should now no
longer consider in-bounds attributes out-of-bounds.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3796
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4199
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8835>
James Park [Mon, 14 Dec 2020 18:33:03 +0000 (10:33 -0800)]
radv: Use typed outarray API
MSVC cannot perform GCC __typeof__ for C code. (C++ has decltype.)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8818>
James Park [Fri, 8 Jan 2021 07:20:44 +0000 (23:20 -0800)]
ac: Remove unnecessary header
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8819>
Tony Wasserka [Wed, 27 Jan 2021 13:28:12 +0000 (14:28 +0100)]
aco/ra: Add helper to get a PhysRegInterval for the register demand
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8737>
Marek Olšák [Tue, 26 Jan 2021 05:35:10 +0000 (00:35 -0500)]
gallium/u_vbuf: skip non-indirect draws with 0 vertices
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8770>
Marek Olšák [Thu, 28 Jan 2021 21:15:40 +0000 (16:15 -0500)]
Revert "gallium/u_vbuf: skip draws with 0 vertices"
This reverts commit
be8d811e57973e9d3632f90e47fda1f5c24ca379.
Fixes: be8d811e57973e9d3632f90e47fda1f5c24ca379
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4184
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8770>
Caio Marcelo de Oliveira Filho [Thu, 25 Jun 2020 05:15:28 +0000 (22:15 -0700)]
anv: Implement VK_KHR_zero_initialize_workgroup_memory
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8708>
Caio Marcelo de Oliveira Filho [Fri, 18 Sep 2020 21:19:21 +0000 (14:19 -0700)]
nir: Add nir_zero_initialize_shared_memory
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8708>
Caio Marcelo de Oliveira Filho [Wed, 24 Jun 2020 20:44:08 +0000 (13:44 -0700)]
spirv: Recognize zero initializers in Workgroup variables
This will be used to implement
VK_KHR_zero_initialize_workgroup_memory.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8708>
Caio Marcelo de Oliveira Filho [Thu, 28 Jan 2021 19:47:24 +0000 (11:47 -0800)]
spirv: Refactor variable initializer code
Pass the vtn_value and let vtn_create_variable do the validation.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8708>
Erico Nunes [Mon, 1 Feb 2021 00:27:50 +0000 (01:27 +0100)]
lima: always set stride in texture descriptor
We can just always specify the stride parameter regardless of whether
an alignment was forced or not. This fixes some issues where it is not
straightforward to detect the need to specify stride by checking the
buffer width (e.g. imported dmabuf to be used as texture).
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8549>
Erico Nunes [Mon, 18 Jan 2021 01:44:40 +0000 (02:44 +0100)]
lima: enable r and rg pixel formats again
Enable r and rg targets to allow r and rg so that lima exposes
GL_EXT_texture_rg.
This is notably required by programs working with textures for
video playback.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8549>
Erico Nunes [Mon, 18 Jan 2021 01:44:46 +0000 (02:44 +0100)]
lima: set yuv formats as external_only
lima is not able to use yuv textures directly.
Set them as external_only so that drivers don't attempt to send yuv
planes directly as dma bufs.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8549>
Jason Ekstrand [Tue, 2 Feb 2021 02:21:52 +0000 (20:21 -0600)]
nir: Drop the lower_mem_constant_vars declaration
The function was removed in
c730ace12b51d46585fac6710fbe57dccd67071c.
Fixes: c730ace12b5 "nir,clover: Drop nir_lower_mem_constant_vars"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8834>
Karol Herbst [Thu, 8 Oct 2020 11:24:59 +0000 (13:24 +0200)]
clover/api: make use of validate_mem_migration_flags in clEnqueueMigrateMemObjects
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6401>
Jérôme Glisse [Thu, 9 Aug 2018 19:32:01 +0000 (15:32 -0400)]
nouveau: add support for SVM migrate
v2 (Ralph): don't allign address as the kernel handles that already
support migration from GPU to system RAM
v3 (Karol): use DIV_ROUND_UP for sizes not being page aligned
Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6401>
Jérôme Glisse [Wed, 8 Aug 2018 23:16:06 +0000 (19:16 -0400)]
clover: implement clEnqueueSVMMigrateMem
Memory migration for SVM (share virtual memory). This allow to migrate
a range of virtual address of the process to device memory to speed up
device processing when that memory is in use by the device.
v2 (Karol): use tracked SVM allocation in order to support cases where
the size of the migration is not specified
Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6401>
Karol Herbst [Thu, 20 Aug 2020 15:05:13 +0000 (17:05 +0200)]
clover: track allocated svm pointers
We need those to proper validate the SVM API.
v2: use std::map instead of std::unordered_map
v3: guard against segfaults on std::prev with empty containers
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6401>
Jérôme Glisse [Thu, 9 Aug 2018 18:53:53 +0000 (14:53 -0400)]
gallium: add support for SVM (Share Virtual Memory) migrate
v2 (Karol): Fix declaration of pointers argument
v3 (Karol): Move flags into function interface as bools
Signed-off-by: Jérôme Glisse <jglisse@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6401>
Erik Faye-Lund [Tue, 2 Feb 2021 12:03:25 +0000 (13:03 +0100)]
zink: wrap some long lines
These lines are very long, let's wrap them a bit.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 12:00:29 +0000 (13:00 +0100)]
zink: refactor vertex-order emitting
Using a ternary expression inside the argument list avoids some
repetition, showing that the rest of the call is the same. This increase
readability a tad.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 11:59:01 +0000 (12:59 +0100)]
zink: add a get_spacing-helper
Similarly to the previous commit, this makes the code a bit easier to
read.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 11:54:32 +0000 (12:54 +0100)]
zink: add a get_primitive_mode-helper
This just makes the code a bit easier to read, where the details are
hidden slightly.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 11:43:35 +0000 (12:43 +0100)]
zink: do not insist shaders come from glsl
We don't know what shading-language our shaders come from. This
information is lost before we get here. So let's not declare that these
come from GLSL shaders, even though that's likely to be the case.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 11:34:45 +0000 (12:34 +0100)]
zik: correct spir-v caps for textures and images
There's a couple of minor issues with these the way they where:
1. All shader stages can perform texturing. So let's check for textures
instead of fragment-shader
2. Not all implementations support StorageImageExtendedFormats. We don't
expose image support for those implementations, but we shouldn't
enable the cap just because we're texturing.
Both of these issues can be tackled by splitting these into texturing
and images conditionals.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 11:29:11 +0000 (12:29 +0100)]
zink: only emit cap when needed
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 11:24:33 +0000 (12:24 +0100)]
zink: only emit SpvCapabilityDerivativeControl when needed
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 10:42:18 +0000 (11:42 +0100)]
zink: correct return-type for function
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 10:40:41 +0000 (11:40 +0100)]
zink: be more careful about limits when unsupported
These limits are dependent on feature caps, so let's try to thread
a bit more carefully when the cap is unsupported.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Erik Faye-Lund [Tue, 2 Feb 2021 10:35:29 +0000 (11:35 +0100)]
zink: remove stale TODO
By now, I think we're fairly sure about this one ;)
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8832>
Jason Ekstrand [Sat, 30 Jan 2021 01:33:19 +0000 (19:33 -0600)]
nir: Add some ssa-only fast-paths for nir_src rewrite
Basically every pass in NIR uses nir_ssa_def_rewrite_uses which calls
nir_instr_rewrite_src which is fairly complex because it handles all
sorts of non-SSA cases. Since we already know a priori that every
source written by nir_ssa_def_rewrite_uses is SSA, we can check new_src
once at the top of the function and cut out all that complexity.
While we're at it, we expose a new SSA-only nir_ssa_def_rewrite_uses_ssa
helper which takes an SSA def which avoids the one SSA check. It's also
more convenient 90% of the time.
Compile time as tested by Rhys Perry <pendingchaos02@gmail.com>
Difference at 95.0% confidence
-797.166 +/- 418.649
-0.566174% +/- 0.296441%
(Student's t, pooled s = 325.459)
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8790>
SureshGuttula [Sun, 24 Jan 2021 05:32:55 +0000 (11:02 +0530)]
va/picture : Added failure check for stability
This patch created to exit from for loop incase handle function
returns error vaStatus. This will help to capture the correct
failure return to application.
Signed-off-by: SureshGuttula <sguttula@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8679>
Lionel Landwerlin [Thu, 10 Sep 2020 08:54:55 +0000 (11:54 +0300)]
anv: switch intel perf queries to query layout
Apart from the single additional marker field, these queries will now
use the same layout as all other drivers.
This should allow us to modify a single component to add an additional
register for new metrics.
v2: Capture the query beging registers in reverse order to ensure
timestamp is as close as possible from measured draw call.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 26 Aug 2020 12:44:07 +0000 (15:44 +0300)]
anv: switch khr perf query code to use query layout
This unifies performance data gathering between the GL & Vulkan
drivers.
v2: Also move all NOOPs to before the query, leaving none inside
v3: Capture the query beging registers in reverse order to ensure
timestamp is as close as possible from measured draw call.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Tue, 15 Sep 2020 08:22:17 +0000 (11:22 +0300)]
anv: compute commands required to implement perf queries
We'll use this later to try to limit the number of NOOPs emitted for
self modifying batches.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Thu, 8 Oct 2020 12:15:51 +0000 (15:15 +0300)]
intel/perf: drop the special READ_REG operator
Makes things a bit more uniform.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 26 Aug 2020 13:39:13 +0000 (16:39 +0300)]
intel/perf: add DG1 support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 26 Aug 2020 13:36:40 +0000 (16:36 +0300)]
intel/perf: add RKL support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 26 Aug 2020 12:48:36 +0000 (15:48 +0300)]
intel/dev: identify rocketlake
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Tue, 25 Aug 2020 13:12:16 +0000 (16:12 +0300)]
intel/perf: break TGL perf configs in GT1/2
Programming and equations are different enough that we really need 2
files.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 26 Aug 2020 12:44:23 +0000 (15:44 +0300)]
intel/dev: identify tigerlake
We'll need that to pick the right query sets between TGL/RKL/DG1.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Thu, 8 Oct 2020 11:48:24 +0000 (14:48 +0300)]
intel/perf: add async compute metrics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Thu, 8 Oct 2020 11:47:30 +0000 (14:47 +0300)]
intel/perf: small ICL equation refactor
No functional changes.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Thu, 8 Oct 2020 11:44:55 +0000 (14:44 +0300)]
intel/perf: update files from IGT
IGT has received a bunch of updates, this is resyncing the files with
it.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 18 Nov 2020 12:07:53 +0000 (14:07 +0200)]
intel/perf: remove reordering script
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 18 Nov 2020 10:43:42 +0000 (12:43 +0200)]
intel/perf: reorder xml files
Make the file match the order of the ones from IGT (which have changed
because of python2->3 transition).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Tue, 17 Nov 2020 21:48:51 +0000 (23:48 +0200)]
intel/perf: add reorder script
When transitioning the oa-*.xml files from Gputop to IGT, we also had
to deal with a python2->3 transition. Unfortunately the implementation
dependent hash table ordering leaked into the XML files and so things
changed quite a bit.
This script reorders things from the old to the new order in the
existing files.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 26 Aug 2020 13:17:53 +0000 (16:17 +0300)]
intel/perf: rename lkf into ehl
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 2 Sep 2020 13:39:32 +0000 (16:39 +0300)]
anv: remove unused query pool field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 26 Aug 2020 11:09:35 +0000 (14:09 +0300)]
anv: fix layout comment
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Wed, 26 Aug 2020 09:41:41 +0000 (12:41 +0300)]
intel/perf: switch query code to use query layout
That way we can describe new registers to that could be used both by
Anv & Iris/i965 without having to modifying code in multiple places.
v2: Do reverse order for begin queries so that we have MI_RPC as close
as possible from the drawcall
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Mon, 7 Sep 2020 12:56:54 +0000 (15:56 +0300)]
intel/perf: add performance query layout using MI_SRM
For all generations supported we had a layout describing what register
to store to implement a MI_RPC replacement.
This is because, on Gen12 we need to snapshot OAG registers to get
correct values for the perf equations. There, the MI_RPC instruction
captures OAR register which do not have all the information we need.
v2: Fix commented code for debug (Marcin)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Thu, 3 Sep 2020 07:52:34 +0000 (10:52 +0300)]
intel/perf: query register descriptions
This will be useful when we implement queries using a series of MI_SRM
instead of MI_RPC.
Unfortunately on Gen12, the MI_RPC command sources values from the OAR
unit which has a similar series of register as the OAG unit but some
of the configuration of HW doesn't reach OAR so we have to snapshot
OAG manually instead.
v2: Fix comments
Use const
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Thu, 4 Jul 2019 17:34:28 +0000 (20:34 +0300)]
intel/perf: prep work to enable new perf counters
Those are not part of the OA reports and need some additional
scaffolding. Those counters are only available when doing queries as
we need to emit MI_SRMs to record them.
Equations making use of those counters are not there yet, they will
come in a follow up commit updating a bunch of oa-*.xml files.
v2: Fix typo
v3: Use PERF_CNT_VALUE_MASK (Marcin)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Lionel Landwerlin [Mon, 30 Nov 2020 08:54:14 +0000 (10:54 +0200)]
genxml: PERFCNT registers are available since HSW
We were using those registers on Gen7.5 in the GL driver already, we
just need them in Genxml for Anv too.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6518>
Andrii Simiklit [Fri, 8 Jan 2021 11:34:34 +0000 (13:34 +0200)]
iris: don't emit IRIS_DIRTY_VF depending on trash in restart_index
The `restart_index` field can be uninitialized if `primitive_restart`
is false so we have to track `restart_index` changes
only if `primitive_restart` is true
Here is a valgrind warning:
Conditional jump or move depends on uninitialised value(s)
==52021== at 0x6D44968: iris_update_draw_info (iris_draw.c:102)
==52021== by 0x6D450B5: iris_draw_vbo (iris_draw.c:273)
==52021== by 0x642FD8E: cso_multi_draw (cso_context.c:1708)
==52021== by 0x5C434D3: st_draw_gallium (st_draw.c:271)
==52021== by 0x5DF5F1B: _mesa_draw_arrays (draw.c:554)
==52021== by 0x5DF68F7: _mesa_DrawArrays (draw.c:768)
==52021== by 0x49011F2: stub_glDrawArrays (piglit-dispatch-gen.c:12181)
==52021== by 0x11C611: piglit_display (shader_runner.c:4549)
==52021== by 0x4994D83: process_next_event (piglit_x11_framework.c:137)
==52021== by 0x4994E47: enter_event_loop (piglit_x11_framework.c:153)
==52021== by 0x49939A4: run_test (piglit_winsys_framework.c:88)
==52021== by 0x49821A9: piglit_gl_test_run (piglit-framework-gl.c:229)
v2: - don't propagate trash to state->cut_index
(Kenneth Graunke <kenneth@whitecape.org>)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8409>
Boris Brezillon [Mon, 25 Jan 2021 12:55:20 +0000 (13:55 +0100)]
panfrost: Update ctx->batch when a fresh batch is requested
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
Boris Brezillon [Tue, 26 Jan 2021 16:41:08 +0000 (17:41 +0100)]
panfrost: Add a panfrost_compile_shader() helper
This deduplicates the
if (pan_is_bifrost())
return bifrost_compile_shader_nir();
else
return midgard_compile_shader_nir();
pattern.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
Boris Brezillon [Tue, 26 Jan 2021 16:05:22 +0000 (17:05 +0100)]
panfrost: Use dev->arch where appropriate
The architecture has already been extracted in panfrost_open_device()
don't do it again.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8808>
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