platform/kernel/u-boot.git
3 years agocolibri_imx6ull/imx7: add missing tdxargs variable
Philippe Schenker [Thu, 11 Mar 2021 20:00:35 +0000 (22:00 +0200)]
colibri_imx6ull/imx7: add missing tdxargs variable

All the other boards have tdxargs specified for setting manual kernel
command-line arguments. Add them also to NAND-based boards.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
3 years agocolibri_imx6: adjust boot order
Igor Opaniuk [Thu, 11 Mar 2021 20:00:34 +0000 (22:00 +0200)]
colibri_imx6: adjust boot order

Remove duplicate of mmc0, set this boot order:
1) SD
2) eMMC
3) USB
4) DHCP boot

Fixes: 0e15165bc4e0 ("colibri_imx6: boot env configuration updates")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
3 years agoboard: gateworks: venice: increase CONFIG_SYS_SPL_MALLOC_SIZE
Tim Harvey [Mon, 8 Mar 2021 21:52:36 +0000 (13:52 -0800)]
board: gateworks: venice: increase CONFIG_SYS_SPL_MALLOC_SIZE

commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images")'
changed the way buffer allocation worked for SPL to a more flexible
method.

For venice this caused breakage that is resolved by increasing the size
of CONFIG_SYS_SPL_MALLOC_SIZE as the current FIT slighly exceeds 512KiB.

Additionally remove the unnecessary comment on CONFIG_SPL_BSS_MAX_SIZE
and CONFIG_SYS_SPL_MALLOC_SIZE as the size is obvious from the define.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
3 years agoboard: gateworks: venice: fix gsc_get_dev
Tim Harvey [Mon, 8 Mar 2021 21:52:35 +0000 (13:52 -0800)]
board: gateworks: venice: fix gsc_get_dev

use dm_i2c_probe instead of i2c_get_chip which appears to be more
reliable.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
3 years agoMAINTAINERS: Use my personal e-mail address
Fabio Estevam [Thu, 4 Mar 2021 17:09:34 +0000 (14:09 -0300)]
MAINTAINERS: Use my personal e-mail address

Use my personal e-mail address for U-Boot related work.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
3 years agoimx: ventana: enable dm for SPI
Tim Harvey [Mon, 1 Mar 2021 22:33:37 +0000 (14:33 -0800)]
imx: ventana: enable dm for SPI

Enable driver model for SPI which allows us to remove the iomux
and init.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoimx: ventana: enable dm for MTD and NAND
Tim Harvey [Mon, 1 Mar 2021 22:33:36 +0000 (14:33 -0800)]
imx: ventana: enable dm for MTD and NAND

Enable driver model for MTD and NAND support allowing us to remove
the iomux, init, and most of the static configuration.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoimx: ventana: enable dm support for MMC and SATA
Tim Harvey [Mon, 1 Mar 2021 22:33:35 +0000 (14:33 -0800)]
imx: ventana: enable dm support for MMC and SATA

Enable driver model support for MMC and SATA.

Note that DM_MMC requires aliases for your mmc devices so
they are added to the dts. Linux does not support enumerating mmc
devices by alias so these are not present in the Linux dts.

Note that we still need board_mmc_init() and board_mmc_getcd() for
not DM SPL to support MMC.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoimx: ventana: enable dm support for USB
Tim Harvey [Mon, 1 Mar 2021 22:33:34 +0000 (14:33 -0800)]
imx: ventana: enable dm support for USB

Enable dm support for USB (which also requires dm support for fixed
regulators used for vbus enable) and remove usb iomux which is no
longer needed.

We can remove the handling of otgpwr_en gpio as this is defined in
dt as usbotg vbus-supply but we need to keep the handling of
USB_HUB_RST# for boards that have a USB HUB as that isn't defined in
the dt's currently.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoimx: ventana: add pinctrl and remove unneeded UART init and config
Tim Harvey [Mon, 1 Mar 2021 22:33:33 +0000 (14:33 -0800)]
imx: ventana: add pinctrl and remove unneeded UART init and config

Once the IMX6 pinctrl driver is added UART is fully using driver mode
so we no longer need to config and initialize it.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoimx: ventana: convert U-Boot to OF_CONTROL using FIT image
Tim Harvey [Mon, 1 Mar 2021 22:33:32 +0000 (14:33 -0800)]
imx: ventana: convert U-Boot to OF_CONTROL using FIT image

In preparation for dm conversion convert to OF_CONTROL by adding FIT image
support and multi dtb.

Add a board_fit_config_name_match to match the dtb based off of EEPROM
model.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoarm: dts: imx6qdl-gw*: add dr_mode prop to dt to avoid error
Tim Harvey [Mon, 1 Mar 2021 22:33:31 +0000 (14:33 -0800)]
arm: dts: imx6qdl-gw*: add dr_mode prop to dt to avoid error

The fsl-usb dt bindings in Linux default dr_mode to 'host' for
backward compatibility however U-Boot prints an error if
this property does not exist. Declare it in the Gateworks
Ventana device-trees to avoid the error.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agoimx: ventana: add Gateworks Ventana dts
Tim Harvey [Mon, 1 Mar 2021 22:33:30 +0000 (14:33 -0800)]
imx: ventana: add Gateworks Ventana dts

Add Gateworks Ventana dts/dtsi files from Linux 5.11 in preparation for
conversion to driver-model.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agodt-bindings: add tda1997x and bindings
Tim Harvey [Mon, 1 Mar 2021 22:33:29 +0000 (14:33 -0800)]
dt-bindings: add tda1997x and bindings

Add td1997x header from Linux to be included by dts files.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
3 years agospl: fit: nand: allow for non-page-aligned elements
Tim Harvey [Mon, 1 Mar 2021 22:33:28 +0000 (14:33 -0800)]
spl: fit: nand: allow for non-page-aligned elements

Add a weak nand_get_mtd function for nand drivers to provide mtd info
and use this to set pagesize such that reading of non page-aligned
elements can succeed.

The spl_load_simple_fit already handles block block access so all we
need to do is provide the nand writesize as the block length.

Further cleanup of the drivers which use nand_spl_loaders.c such as
am335x_spl_bch.c, atmel_nand.c, and nand_spl_simple.c could be done
using info from mtd_info instead of statically defined details.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
3 years agospl: fit: nand: skip bad block handling if NAND chip not fully defined
Tim Harvey [Mon, 1 Mar 2021 22:33:27 +0000 (14:33 -0800)]
spl: fit: nand: skip bad block handling if NAND chip not fully defined

commit 9f6a14c47ff9 ("spl: fit: nand: fix fit loading in case of bad blocks")
added support for adjusting the image offset to account for bad blocks.
However this requires nand_spl_adjust_offset() which requires fully defined
specifics of the NAND chip being used may not be avialable.

Allow skipping this support for drivers or configs which don't specify
the NAND chip details statically with defines.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
3 years agoARM: imx: Add OCRAM_S into iMX8M MMU tables
Marek Vasut [Thu, 25 Feb 2021 20:52:26 +0000 (21:52 +0100)]
ARM: imx: Add OCRAM_S into iMX8M MMU tables

The OCRAM_S is regular memory, just like the OCRAM, add it to the MMU
tables so it can be used and cached.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
3 years agodoc: imx8mp-evk: update after using binman
Peng Fan [Tue, 6 Apr 2021 03:59:03 +0000 (11:59 +0800)]
doc: imx8mp-evk: update after using binman

update doc after using binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mp-evk: switch to use binman
Peng Fan [Tue, 6 Apr 2021 03:59:02 +0000 (11:59 +0800)]
imx8mp-evk: switch to use binman

Use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agodoc: imx8mn_evk: update doc after using binman
Peng Fan [Tue, 6 Apr 2021 03:59:01 +0000 (11:59 +0800)]
doc: imx8mn_evk: update doc after using binman

Update doc after using binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mn-evk: switch to use binman
Peng Fan [Tue, 6 Apr 2021 03:59:00 +0000 (11:59 +0800)]
imx8mn-evk: switch to use binman

Use binman to pack images.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mn-ddr4-evk: switch to use binman
Peng Fan [Tue, 6 Apr 2021 03:58:59 +0000 (11:58 +0800)]
imx8mn-ddr4-evk: switch to use binman

Use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agodoc: imx8mm_evk: update doc after using binman
Peng Fan [Tue, 6 Apr 2021 03:58:58 +0000 (11:58 +0800)]
doc: imx8mm_evk: update doc after using binman

Update doc after switch to binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mm_evk: switch to use binman to pack images
Peng Fan [Tue, 6 Apr 2021 03:58:57 +0000 (11:58 +0800)]
imx8mm_evk: switch to use binman to pack images

Use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocrypto: fsl: refactor for 32 bit version CAAM support on ARM64
Ye Li [Thu, 25 Mar 2021 09:30:36 +0000 (17:30 +0800)]
crypto: fsl: refactor for 32 bit version CAAM support on ARM64

Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit
for i.MX8M" breaks the 64 bits CAAM.

Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64),
to adapt and not break 64 bits CAAM support,  add a new config
CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t".

This config is default enabled when CONFIG_PHYS_64BIT is set except
for iMX8M.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agofsl_mfgprot: Fix typo in sign_mppubk()
Breno Lima [Thu, 25 Mar 2021 09:30:35 +0000 (17:30 +0800)]
fsl_mfgprot: Fix typo in sign_mppubk()

The signature is generated using manufacturing protection private key.

Fix typo in fsl_mfgprot.c.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8: Add DEK blob encapsulation
Clement Faure [Thu, 25 Mar 2021 09:30:34 +0000 (17:30 +0800)]
imx8: Add DEK blob encapsulation

Add DEK encapsulation support for imx8. The DEK blob is generated by the
SECO through the SCFW API.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8m: Add DEK blob encapsulation for imx8m
Clement Faure [Thu, 25 Mar 2021 09:30:33 +0000 (17:30 +0800)]
imx8m: Add DEK blob encapsulation for imx8m

Add DEK blob encapsulation support for IMX8M through "dek_blob" command.
On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob
for encrypted boot.
The DEK blob is encapsulated by OP-TEE through a trusted application call.
U-boot sends and receives the DEK and the DEK blob binaries through OP-TEE
dynamic shared memory.

To enable the DEK blob encapsulation, add to the defconfig:
CONFIG_SECURE_BOOT=y
CONFIG_FAT_WRITE=y
CONFIG_CMD_DEKBLOB=y

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: caam: new u-boot command to set PRIBLOB bitfield from CAAM SCFGR register to 0x3
Clement Le Marquis [Thu, 25 Mar 2021 09:30:32 +0000 (17:30 +0800)]
imx: caam: new u-boot command to set PRIBLOB bitfield from CAAM SCFGR register to 0x3

It is highly recommended to set the PRIBLOB bitfield to 0x3 once your
encrypted boot image has booted up, this prevents the generation of new
blobs that can be used to decrypt an encrypted boot image. The PRIBLOB is
a sticky type bit and cannot be changed until the next power on reset.

Add the set_priblob_bitfield U-Boot command to prevent the generation of
new blobs.

Signed-off-by: Clement Le Marquis <clement.lemarquis@nxp.com>
Acked-by: Ye Li <Ye.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocrypto: caam: Add secure memory vid 3 support
Aymen Sghaier [Thu, 25 Mar 2021 09:30:29 +0000 (17:30 +0800)]
crypto: caam: Add secure memory vid 3 support

In i.MX8M platforms the secure memory block has a newer version
than those used in i.MX6/7 platforms, this patch update the driver
to use the correct registers offsets.

Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocrypto: caam: Fix pointer size to 32bit for i.MX8M
Aymen Sghaier [Thu, 25 Mar 2021 09:30:28 +0000 (17:30 +0800)]
crypto: caam: Fix pointer size to 32bit for i.MX8M

  The CAAM block used in i.MX8M is 32 bits address size but when the flag
 PHYS_64BIT is enabled for armv8, the CAAM driver will try to use a
 wrong pointer size.
  This patch fixes this issue.

Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocrypto: Add blob command support for i.MX8M platforms
Aymen Sghaier [Thu, 25 Mar 2021 09:30:27 +0000 (17:30 +0800)]
crypto: Add blob command support for i.MX8M platforms

 This patch enable blob command for mScale platforms.

Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocrypto: caam: Fix build warnings pointer casting
Aymen Sghaier [Thu, 25 Mar 2021 09:30:26 +0000 (17:30 +0800)]
crypto: caam: Fix build warnings pointer casting

  Enabling CAAM driver for i.MX8M platforms, a 64 bits architecture,
 lead to casting warnings: from/to pointer to/from integer with
 different size. This patch fix these warnings

Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocrypto: caam: Add CAAM support to i.MX8M platforms
Aymen Sghaier [Thu, 25 Mar 2021 09:30:25 +0000 (17:30 +0800)]
crypto: caam: Add CAAM support to i.MX8M platforms

This patch enable CAAM support for i.MX8M platforms.

Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx7ulp: Enable support for cmd blob
Franck LENORMAND [Thu, 25 Mar 2021 09:30:24 +0000 (17:30 +0800)]
imx7ulp: Enable support for cmd blob

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocaam: enable support for iMX7ULP
Franck LENORMAND [Thu, 25 Mar 2021 09:30:23 +0000 (17:30 +0800)]
caam: enable support for iMX7ULP

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocrypto: caam: change JR running loop
Franck LENORMAND [Thu, 25 Mar 2021 09:30:22 +0000 (17:30 +0800)]
crypto: caam: change JR running loop

Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocmd: blob: Instantiate RNG before running CMD_BLOB
Breno Lima [Thu, 25 Mar 2021 09:30:21 +0000 (17:30 +0800)]
cmd: blob: Instantiate RNG before running CMD_BLOB

U-Boot can instantiate CAAM RNG if needed by crypto operations.
Call sec_init() prior running a blob operation to ensure
RNG is correctly instantiated.

Make sure CAAM clock is enabled and check if a job ring is
available for that operation.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocmd: blob: Add IMX_HAB and CAAM supported SoCs as dependency
Breno Lima [Thu, 25 Mar 2021 09:30:20 +0000 (17:30 +0800)]
cmd: blob: Add IMX_HAB and CAAM supported SoCs as dependency

In order to build CMD_BLOB on i.MX CAAM supported devices it's
necessary to select IMX_HAB. Add IMX_HAB and CAAM supported
SoCs as dependency.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agomx6dq: hab: Fix chip version in hab.h code
Breno Lima [Thu, 25 Mar 2021 09:30:19 +0000 (17:30 +0800)]
mx6dq: hab: Fix chip version in hab.h code

Since commit 8891410c729b ("MLK-19848 mx6dq: Fix chip version issue for
rev1.3") it's not possible to call the HAB API functions on i.MX6DQ
SoC Rev 1.3:

Authenticate image from DDR location 0x12000000...
undefined instruction
pc : [<412c00dc>]          lr : [<8ff560bc>]
reloc pc : [<c8b6d0dc>]    lr : [<178030bc>]
sp : 8ef444a8  ip : 126e8068     fp : 8ff59aa8
r10: 8ffd51e4  r9 : 8ef50eb0     r8 : 006e8000
r7 : 00000000  r6 : 126ea01f     r5 : 0000002b  r4 : 126e8000
r3 : 412c00dd  r2 : 00000001     r1 : 00000001  r0 : 00000063
Flags: nzCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

The hab.h code is defining the HAB API base address according to the
old SoC revision number, thus failing when calling the HAB API
authenticate_image() function.

Fix this issue by using mx6dq rev 1.3 instead of mx6dq rev 1.5.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: cmd_dek: Enable DEK only for chips supporting CAAM
Ye Li [Thu, 25 Mar 2021 09:30:18 +0000 (17:30 +0800)]
imx: cmd_dek: Enable DEK only for chips supporting CAAM

Since cmd_dek is using CAAM JR, so enable the CMD_DEK only when
HAS_CAAM is set

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoiMX8M: Add support to enable CONFIG_IMX_HAB
Ye Li [Thu, 25 Mar 2021 09:30:17 +0000 (17:30 +0800)]
iMX8M: Add support to enable CONFIG_IMX_HAB

Add some SOC level codes and build configurations to use HAB lib for
CONFIG_IMX_HAB (secure boot), like adding the SEC_CONFIG fuse, enable
fuse driver, CAAM clock function, and add CAAM secure RAM to MMU table.

The FSL_CAAM is temporally not enabled for iMX8M when CONFIG_IMX_HAB is set,
because we don't need the CAAM driver for SPL.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agocrypto: fsl: blob: Flush dcache range for destination address
Breno Lima [Thu, 25 Mar 2021 09:30:16 +0000 (17:30 +0800)]
crypto: fsl: blob: Flush dcache range for destination address

The blob command is not working on i.MX7D, i.MX8MQ and i.MX8MM
devices.

Due to different cache management it's necessary to flush dcache
range for destination address so data can be available in memory.

Add necessary operations in blob_encap() and blob_decap() functions.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: HAB: Add support for iMX8MM
Ye Li [Thu, 25 Mar 2021 09:30:15 +0000 (17:30 +0800)]
imx: HAB: Add support for iMX8MM

The imx8mm has changed the address of rvt_hab, use new address for imx8mm.

The authentication procedure is same as imx8mq. In u-boot, the authentication
uses SIP call to trap ATF to run HAB authenticate.

Users need to add CONFIG_SECURE_BOOT=y to defconfig to enable the feature.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: hab: Fix build warnings in 32-bit targets
Breno Lima [Thu, 25 Mar 2021 09:30:14 +0000 (17:30 +0800)]
imx: hab: Fix build warnings in 32-bit targets

When building 32-bit targets with CONFIG_SECURE_BOOT and DEBUG enabled
the following warnings are displayed:

arch/arm/mach-imx/hab.c:840:41: warning: format '%lx' expects argument \
of type 'long unsigned int', but argument 3 has type 'uint32_t \
{aka unsigned int}' [-Wformat=]
   printf("HAB check target 0x%08x-0x%08lx fail\n",
                                     ~~~~^
                                     %08x
          ddr_start, ddr_start + bytes);

arch/arm/mach-imx/hab.c:845:45: warning: format '%x' expects argument \
of type 'unsigned int', but argument 3 has type 'ulong \
{aka long unsigned int}' [-Wformat=]
  printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr);
                                            ~^
                                            %lx

Fix warnings by providing the correct data type.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agomx7ulp: hab: Add hab_status command for HABv4 M4 boot
Breno Lima [Thu, 25 Mar 2021 09:30:13 +0000 (17:30 +0800)]
mx7ulp: hab: Add hab_status command for HABv4 M4 boot

When booting in low power or dual boot modes the M4 binary is
authenticated by the M4 ROM code.

Add an option in hab_status command so users can retrieve M4 HAB
failure and warning events.

=> hab_status m4

   Secure boot disabled

   HAB Configuration: 0xf0, HAB State: 0x66
   No HAB Events Found!

Add command documentation in mx6_mx7_secure_boot.txt guide.

As HAB M4 API cannot be called from A7 core the code is parsing
the M4 HAB persistent memory region. The HAB persistent memory
stores HAB events, public keys and others HAB related information.

The HAB persistent memory region addresses and sizes can be found
in AN12263 "HABv4 RVT Guidelines and Recommendations".

Reviewed-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: hab: Check if IVT header is HABv4
Breno Lima [Thu, 25 Mar 2021 09:30:12 +0000 (17:30 +0800)]
imx: hab: Check if IVT header is HABv4

The HABv4 implementation in ROM checks if HAB major version
in IVT header is 4.x.

The current implementation in hab.c code is only validating
HAB v4.0 and HAB v4.1 and may be incompatible with newer
HABv4 versions.

Modify verify_ivt_header() function to align with HABv4
implementation in ROM code.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: hab: Display All HAB events via hab_status command
Utkarsh Gupta [Thu, 25 Mar 2021 09:30:11 +0000 (17:30 +0800)]
imx: hab: Display All HAB events via hab_status command

Add ability for hab_status command to show All HAB events and not just
HAB failure events

Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: hab: Enable hab.c to authenticate additional images in open configuration
Breno Lima [Thu, 25 Mar 2021 09:30:10 +0000 (17:30 +0800)]
imx: hab: Enable hab.c to authenticate additional images in open configuration

Currently it's not possible to authenticate additional boot images in HAB
open configuration.

The hab.c code is checking if the SEC_CONFIG[1] fuse is programmed prior
to calling the hab_authenticate_image() API function. Users cannot check
if their additional boot images has been correctly signed prior to closing
their device.

Enable hab.c to authenticate additional boot images in open mode so HAB
events can be retrieved through get_hab_status() function.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agohab: Change calling to ROM API failsafe
Ye Li [Thu, 25 Mar 2021 09:30:09 +0000 (17:30 +0800)]
hab: Change calling to ROM API failsafe

Modify to use hab_rvt_failsafe function for failsafe ROM API, not
directly call its ROM address. This function will wrap the sip call for iMX8M
platforms.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: HAB: Validate IVT before authenticating image
Utkarsh Gupta [Thu, 25 Mar 2021 09:30:08 +0000 (17:30 +0800)]
imx: HAB: Validate IVT before authenticating image

Calling csf_is_valid() with an un-signed image may lead to data abort
as the CSF pointer could be pointing to a garbage address when accessed
in HAB_HDR_LEN(*(const struct hab_hdr *)(ulong)ivt_initial->csf).

Authenticate image from DDR location 0x80800000...
Check CSF for Write Data command before authenticating image
data abort
pc : [<fff5494c>]          lr : [<fff54910>]
reloc pc : [<8780294c>]    lr : [<87802910>]
sp : fdf45dc8  ip : 00000214     fp : 00000000
r10: fffb6170  r9 : fdf4fec0     r8 : 00722020
r7 : 80f20000  r6 : 80800000     r5 : 80800000  r4 : 00720000
r3 : 17a5aca3  r2 : 00000000     r1 : 80f2201f  r0 : 00000019
Flags: NzcV  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

To avoid such errors during authentication process, validate IVT structure
by calling validate_ivt function which checks the following values in an IVT:

IVT_HEADER = 0x4X2000D1
ENTRY != 0x0
RES1 = 0x0
DCD = 0x0       /* Recommended */
SELF != 0x0     /* Absoulute address of IVT */
CSF != 0x0
RES2 = 0x0

This commit also checks if Image's start address is 4 byte aligned.

commit "0088d127 MLK-14945 HAB: Check if IVT valid before authenticating image"
removed as this patch addresses the issue.

Signed-off-by: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: HAB: Update hab codes to support ARM64 and i.MX8M
Peng Fan [Thu, 25 Mar 2021 09:30:07 +0000 (17:30 +0800)]
imx: HAB: Update hab codes to support ARM64 and i.MX8M

There are some changes to support ARM64 i.MX8M platform in this patches:
1. The hab_rvt base and function vectors are different as i.MX6/7

2. Need to bypass an workaround for i.MX6 to fix problem in MMU.

3. The x18 register needed save & restore before calling any HAB API. According
   to ARM procedure call spec, the x18 is caller saved when it is used as
   temporary register. So calling HAB API may scratch this register, and
   cause crash once accessing the gd pointer.

   On ARMv7, the r9 is callee saved when it is used as variable register. So
   no need to save & restore it.

4. Add SEC_CONFIG fuse for iMX8M

When current EL is not EL3, the direct calling to HAB will fail because
CAAM/SNVS can't initialize at non-secure mode. In this case, we use
SIP call to run the HAB in ATF.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: hab: Add function to authenticate kernel image
Ye Li [Thu, 25 Mar 2021 09:30:06 +0000 (17:30 +0800)]
imx: hab: Add function to authenticate kernel image

When loading kernel image, the image size is parsed from header, so it
does not include the CSF and IVT.

Add back the authenticate_image function to wrap the imx_hab_authenticate_image
with calculating IVT offset and full image size.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: Avoid hardcoded Job Ring Max size
Breno Lima [Thu, 25 Mar 2021 09:30:05 +0000 (17:30 +0800)]
imx: Avoid hardcoded Job Ring Max size

Prior instantiating RNG we have to ensure if the CAAM job rings are
available. Avoid hardcoded job ring max size and use the definition at
fsl_sec.h

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: Ensure CAAM clock is enabled prior getting out_jr_size
Breno Lima [Thu, 25 Mar 2021 09:30:04 +0000 (17:30 +0800)]
imx: Ensure CAAM clock is enabled prior getting out_jr_size

Prior calling sec_in32() we have to ensure CAAM clock is enabled, the
function sec_in32() is reading CAAM registers and if CAAM clock is disabled
the system will hang.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: Avoid hardcoded output ring size register offset (ORSR)
Breno Lima [Thu, 25 Mar 2021 09:30:03 +0000 (17:30 +0800)]
imx: Avoid hardcoded output ring size register offset (ORSR)

The CAAM output ring size register offset is currently defined in fsl_sec.h
as FSL_CAAM_ORSR_JRa_OFFSET, use this definition to avoid hardcoded value in
i.MX common code.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx: imx7 Support for Manufacturing Protection
Breno Lima [Thu, 25 Mar 2021 09:30:02 +0000 (17:30 +0800)]
imx: imx7 Support for Manufacturing Protection

This code was originally developed by Raul Cardenas <raul.casas@nxp.com>
and modified to be applied in U-Boot imx_v2017.03.

More information about the initial submission can be seen
in the link below:
https://lists.denx.de/pipermail/u-boot/2016-February/245273.html

i.MX7D has an a protection feature for Manufacturing process.
This feature uses asymmetric encryption to sign and verify
authenticated software handled between parties. This command
enables the use of such feature.

The private key is unique and generated once per device.
And it is stored in secure memory and only accessible by CAAM.
Therefore, the public key generation and signature functions
are the only functions available for the user.

The manufacturing-protection authentication process can be used to
authenticate the chip to the OEM's server.

Command usage:

Print the public key for the device.
- mfgprot pubk

Generates Signature over given data.
- mfgprot sign <data_address> <data_size>

Signed-off-by: Raul Ulises Cardenas <raul.casas@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8m: add regs used by CAAM
Peng Fan [Thu, 25 Mar 2021 09:30:01 +0000 (17:30 +0800)]
imx8m: add regs used by CAAM

Add regs used by CAAM

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mn: evk: update MAINTAINERS
Peng [Thu, 25 Mar 2021 09:30:00 +0000 (17:30 +0800)]
imx8mn: evk: update MAINTAINERS

Add imx8mn_evk_defconfig to be maintained
Typo fix

Signed-off-by: Peng <peng.fan@nxp.com>
3 years agoimx8mq_evk: Applying default LPDDR4 script for B2
Ye Li [Fri, 19 Mar 2021 07:57:18 +0000 (15:57 +0800)]
imx8mq_evk: Applying default LPDDR4 script for B2

Both i.MX8MQ B1 and B2 should use default LPDDR4 script, while B0
has another dedicated script.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agomisc: ocotp: Update OCOTP driver for iMX8MQ B2
Ye Li [Fri, 19 Mar 2021 07:57:17 +0000 (15:57 +0800)]
misc: ocotp: Update OCOTP driver for iMX8MQ B2

i.MX8MQ B2 also has fixed value in OCOTP_READ_FUSE_DATA register,
so it does not support "fuse sense" command like B1.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoiMX8MQ: Recognize the B2 revision
Ye Li [Fri, 19 Mar 2021 07:57:16 +0000 (15:57 +0800)]
iMX8MQ: Recognize the B2 revision

i.MX8MQ B2 is using same value in OCOTP_READ_FUSE_DATA like B1, so
we have to check the ROM verision to distinguish the revision.

As we have checked the B1 rev for sticky bits work around in
secure boot. So it won't apply on B2.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoarch: mach-imx: imx8m: fix unique_id read error for imx8mp
Peng Fan [Fri, 19 Mar 2021 07:57:15 +0000 (15:57 +0800)]
arch: mach-imx: imx8m: fix unique_id read error for imx8mp

The value of Unique ID in uboot and kernel is different for iMX8MP:

serial#=02e1444a0002aaff
root@imx8mpevk:/sys/devices/soc0# cat soc_uid
D699300002E1444A

The reason is that Fuse Addresses of Unique ID of iMX8MP are 0x420 and
0x430.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8m: ddr: Disable CA VREF Training for LPDDR4
Ye Li [Fri, 19 Mar 2021 07:57:14 +0000 (15:57 +0800)]
imx8m: ddr: Disable CA VREF Training for LPDDR4

Users reported LPDDR4 MR12 value is set to 0 during PHY training,
not the value from FSP timing structure, which cause compliance test failed.
The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
but not set in 1D.  According to PHY training application node,
to enable the feature both 1D and 2D need set this field to 1,
otherwise the training result will be incorrect.
The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
MR12 value from message block (FSP structure). So update the LPDDR4
scripts of all mscale to clear CATrainOpt[0].

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8m: soc: update fuse path
Peng Fan [Fri, 19 Mar 2021 07:57:13 +0000 (15:57 +0800)]
imx8m: soc: update fuse path

Update fuse path to disable modules correctly.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8m: Update thermal and PMU kernel nodes for dual/single cores
Ye Li [Fri, 19 Mar 2021 07:57:12 +0000 (15:57 +0800)]
imx8m: Update thermal and PMU kernel nodes for dual/single cores

For dual core and single core iMX8M parts, the thermal node and PMU node
in kernel DTB also needs update to remove the refers to deleted core nodes.
Otherwise both driver will fail to work.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mn: Add support for 11x11 UltraLite part number
Ye Li [Fri, 19 Mar 2021 07:57:11 +0000 (15:57 +0800)]
imx8mn: Add support for 11x11 UltraLite part number

There are 3 part numbers for 11x11 i.MX8MNano with different core number
configuration: UltraLite Quad/Dual/Solo

Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So
checking the MIPI DSI disable fuse to recognize these parts.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mn: Add low drive mode support for DDR4/LPDDR4 EVK
Ye Li [Fri, 19 Mar 2021 07:57:09 +0000 (15:57 +0800)]
imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK

Add dedicated defconfigs for iMX8MN low drive mode which set the VDD_SOC
and VDD_DRAM to 0.8v, DDR at 1600MTS (800Mhz clock) and GPU at 200Mhz.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mn: Add LPDDR4 EVK board support
Peng Fan [Fri, 19 Mar 2021 07:57:08 +0000 (15:57 +0800)]
imx8mn: Add LPDDR4 EVK board support

Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and
PCA9450B PMIC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mn_evk: drop duplicated code
Peng Fan [Fri, 19 Mar 2021 07:57:07 +0000 (15:57 +0800)]
imx8mn_evk: drop duplicated code

uart clk has been enabled, no need enable again.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agopower: pca9450: add a new parameter for power_pca9450_init
Peng Fan [Fri, 19 Mar 2021 07:57:06 +0000 (15:57 +0800)]
power: pca9450: add a new parameter for power_pca9450_init

Currently PCA9450 might have address 0x25 or 0x35, so let user
choose the address.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agoimx8mn: Update the DDR4 timing script on imx8mn ddr4 evk
Jacky Bai [Fri, 19 Mar 2021 07:57:05 +0000 (15:57 +0800)]
imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk

On i.MX8MN, we can only support DLL-ON mode only, so update the timing
to support 2400mts & 1066mts setpoint.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage
Peng Fan [Fri, 19 Mar 2021 07:57:04 +0000 (15:57 +0800)]
imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage

There is a frequency/timing limitation for SOC and ARM, if SOC is OD
voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have
timing risk from SOC to ARM.

Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will
increase bus clocks to OD frequency before it increases ARM voltage.
So to conform to the limitation, we'd better increases VDD_ARM to OD
voltage in SPL.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mp_evk: spl: clean up including headers
Peng Fan [Fri, 19 Mar 2021 07:57:03 +0000 (15:57 +0800)]
imx8mp_evk: spl: clean up including headers

Clean up the including headers

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mp: refine power on imx8mp board
haidong.zheng [Fri, 19 Mar 2021 07:57:02 +0000 (15:57 +0800)]
imx8mp: refine power on imx8mp board

VDD SOC normal run changed to 0.85V
LPDDR4 freq0 change from 4000MTS to 2400MTS

Signed-off-by: haidong.zheng <haidong.zheng@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mp_evk: Update LPDDR4 refresh time
Ye Li [Fri, 19 Mar 2021 07:57:01 +0000 (15:57 +0800)]
imx8mp_evk: Update LPDDR4 refresh time

Use more safer refresh time value for 6GB LPDDR4 on this EVK board.
Update the parameters for every frequency point.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mp_evk: Update LPDDR4 timing for new FW 202006
Ye Li [Fri, 19 Mar 2021 07:57:00 +0000 (15:57 +0800)]
imx8mp_evk: Update LPDDR4 timing for new FW 202006

After switching to new LPDDR4 firmware 202006 version, have to
update the LPDDR4 timing accordingly from RPA tool.

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Sherry Sun <sherry.sun@nxp.com>
Tested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mp: ddr: Add inline ECC feature support
Sherry Sun [Fri, 19 Mar 2021 07:56:59 +0000 (15:56 +0800)]
imx8mp: ddr: Add inline ECC feature support

Add inline ECC support for lpddr4 on imx8mp-evk. And add a config which
can enable/disable inline ECC feature for lpddr4 on imx8mp-evk board.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mp_evk: add/cleanup variable for distro
Peng Fan [Fri, 19 Mar 2021 07:56:58 +0000 (15:56 +0800)]
imx8mp_evk: add/cleanup variable for distro

Add fdt_addr_r fdtfile which used by distro boot
Clean up environment

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mm_evk: add/cleanup variable for distro
Peng Fan [Fri, 19 Mar 2021 07:56:57 +0000 (15:56 +0800)]
imx8mm_evk: add/cleanup variable for distro

Add fdt_addr_r fdtfile which used by distro boot
Clean up environment

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mm/p: remove boot.cmd
Peng Fan [Fri, 19 Mar 2021 07:56:56 +0000 (15:56 +0800)]
imx8mm/p: remove boot.cmd

These files should not be in U-Boot repo

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoimx8mm_evk: Switch to new imx8mm evk board
Ye Li [Fri, 19 Mar 2021 07:56:55 +0000 (15:56 +0800)]
imx8mm_evk: Switch to new imx8mm evk board

Update PMIC to use PCA9540, the legacy board not supported by NXP

Signed-off-by: Ye Li <ye.li@nxp.com>
3 years agoimx8mm_evk: Update to latest LPDDR4 script
Ye Li [Fri, 19 Mar 2021 07:56:54 +0000 (15:56 +0800)]
imx8mm_evk: Update to latest LPDDR4 script

Update LPDDR4 script to sync with v2020.04 u-boot

Signed-off-by: Ye Li <ye.li@nxp.com>
3 years agotools: imx image: fix write warning
Peng Fan [Fri, 19 Mar 2021 07:56:53 +0000 (15:56 +0800)]
tools: imx image: fix write warning

Fix the warning by set the variable zero to uint64_t
"warning: ‘write’ reading 5 bytes from a region of size 4"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agoMerge branch '2021-04-07-CI-improvements'
Tom Rini [Wed, 7 Apr 2021 19:54:07 +0000 (15:54 -0400)]
Merge branch '2021-04-07-CI-improvements'

- Assorted Azure/GitLab improvements
- Move the Dockerfile used for making containers in CI in to this
  repository.

3 years agotools: Integrate the Dockerfile used for CI
Tom Rini [Mon, 15 Mar 2021 17:19:01 +0000 (13:19 -0400)]
tools: Integrate the Dockerfile used for CI

Integrate the Dockerfile from
https://source.denx.de/u-boot/gitlab-ci-runner.git as of
commit bc6130d572f1 ("Dockerfile: Remove high UID/GID") and introduce a
short rST on how to build the container.

Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoAzure/GitLab: bump OpenSBI version to 0.9
Heinrich Schuchardt [Fri, 2 Apr 2021 09:42:01 +0000 (11:42 +0200)]
Azure/GitLab: bump OpenSBI version to 0.9

Version 0.9 of OpenSBI provides the system reset extension which allows us
to reset and power off boards without board specific code.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agoMerge branch '2021-04-07-fs-updates'
Tom Rini [Wed, 7 Apr 2021 15:14:13 +0000 (11:14 -0400)]
Merge branch '2021-04-07-fs-updates'

- JFFS2 updates

3 years agopytest: Lower pygit2 requirement
Tom Rini [Fri, 26 Feb 2021 12:52:28 +0000 (07:52 -0500)]
pytest: Lower pygit2 requirement

The latest versions of pygit2 are not available in practically any
distribution at this time.  Furthermore, we don't need the latest in
order to run all of our testsuites.  Reduce this version requirement to
something older that meets our needs while still supporting running our
tests on older hosts (and so, test labs).

Reported-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoGitLab: Remove "tags" stanzas
Tom Rini [Fri, 26 Feb 2021 12:52:27 +0000 (07:52 -0500)]
GitLab: Remove "tags" stanzas

Given the structure of our current GitLab tests, we don't make real use
of the tags.  Furthermore, these tags prevent the automatic usage of the
default GitLab runners.  Remove these tags.

Reported-by: Roger Meier <r.meier@siemens.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoAzure: Rework SH / Renesas job
Tom Rini [Mon, 15 Feb 2021 15:52:19 +0000 (10:52 -0500)]
Azure: Rework SH / Renesas job

Now that there is a single SuperH platform, rework the Azure job
slightly.  Azure build time limits mean that we need to split the world
build up still.  Make a single build job for the single Renesas SuperH
platform as well as all of the ARM platforms from Renesas.

Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoJFFS2: fix jffs2 summary datacrc status uninitialized
Wagner Popov dos Santos [Tue, 23 Feb 2021 03:49:00 +0000 (00:49 -0300)]
JFFS2: fix jffs2 summary datacrc status uninitialized

The function jffs2_1pass_read_inode() was discarding the summary
inodes and dirent because the value in datacrc flag wasn't
initialized in function jffs2_sum_process_sum_data().

This fix initializes the status of all summary records to indicate
that the CRC needs to be verified when they are loaded.

Before this fix, the behaviors produced by the undefined value of
datacrc was:
- Summary's registries were discarded when 'b->datacrc' is equal
  as 'CRC_BAD'.
- Summary's registries were not checked when b->datacrc differs of
  'CRC_BAD' and 'CRC_UNKNOWN'

So, almost all of the time the crc just isn't checked, and in some
cases the registries are discarded.

Signed-off-by: Wagner Popov dos Santos <wpopov@gmail.com>
3 years agoJFFS2: fix the reading address over nand's limit
Wagner Popov dos Santos [Tue, 23 Feb 2021 02:30:58 +0000 (23:30 -0300)]
JFFS2: fix the reading address over nand's limit

Fixes address violation in functions read_nand_cached() and
read_onenand_cached(). This happens because these functions
try to read a fixed amount
of data even when the offset+length
is above the nand's limit.

Signed-off-by: Wagner Popov dos Santos <wpopov@gmail.com>
3 years agoMerge tag 'mmc-2021-4-6' of https://source.denx.de/u-boot/custodians/u-boot-mmc
Tom Rini [Wed, 7 Apr 2021 02:42:55 +0000 (22:42 -0400)]
Merge tag 'mmc-2021-4-6' of https://source.denx.de/u-boot/custodians/u-boot-mmc

Update hwpartition usage
Check bootbus's arguments
workaround for erratum A-011334 for fsl_esdhc driver
add pulse width detection workaround for fsl_esdhc driver
Use alias num before checking mmc index when creating device

3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-usb
Tom Rini [Tue, 6 Apr 2021 18:11:21 +0000 (14:11 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb

- XHCI fixes

3 years agousb: xhci: Make debug output better readable and checkpatch clean
Stefan Roese [Tue, 6 Apr 2021 10:10:18 +0000 (12:10 +0200)]
usb: xhci: Make debug output better readable and checkpatch clean

This change makes debugging a bit easier as the output is better
readable with the added space. The explicit le16_to_cpu() is not
needed in the output. Also this patch moves the strings into one line
to make the patch checkpatch clean.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
3 years agousb: xhci: Add missing xhci_readl()
Aaron Williams [Tue, 6 Apr 2021 10:10:17 +0000 (12:10 +0200)]
usb: xhci: Add missing xhci_readl()

Accessing the xHCI controller registers should be done via the
xhci_readl/writel functions. This patch adds this to a few missing
places.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
3 years agousb: hub: Fix usb_get_port_status() for big-endian platforms
Aaron Williams [Tue, 6 Apr 2021 10:10:16 +0000 (12:10 +0200)]
usb: hub: Fix usb_get_port_status() for big-endian platforms

Add missing endianness conversions to usb_get_port_status(). This
(amongst others) is necessary to enable the use of USB 3 hubs on
big-endian platforms like MIPS Octeon.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
3 years agoMerge tag 'u-boot-amlogic-20210406' of https://source.denx.de/u-boot/custodians/u...
Tom Rini [Tue, 6 Apr 2021 12:37:28 +0000 (08:37 -0400)]
Merge tag 'u-boot-amlogic-20210406' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- Add MMIO MDIO mux driver
- Add Amlogic G12A MDIO mux driver
- Add DM_MDIO support for designware ethernet driver
- Add Amlogic Meson8b and later designware ethernet glue driver
- Switch all amlogic boards to Amlogic designware ethernet glue driver
- Switch all amlogic boards to DM_MDIO when necessary
- Remove all static ethernet setup code

3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Tue, 6 Apr 2021 12:37:06 +0000 (08:37 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- Enhance WDT handling (starting / stopping) and introduce
  CONFIG_WATCHDOG_AUTOSTART to allow disabling of autostart of
  the WDT (Pali)