Dylan Baker [Thu, 2 Feb 2023 21:05:33 +0000 (13:05 -0800)]
meson: combine checks for linker --gc-sections support
We first do an incomplete check for whether the linker supports
--gc-sections, then potentially add C and C++ arguments assuming that it
works, then later do a complete check to see if it actually works and
use --gc-sections. This means we can end up putting functions and data
in separate sections when we can't gc them.
Combine the checks, do less work, and be more accurate.
fixes:
f51ce21e4e0bf7efabe58afb4a2cd6b9f98d9505
("meson: Drop adding -Wl,--gc-sections to project c/cpp arguments.")
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21083>
Alyssa Rosenzweig [Thu, 12 Jan 2023 21:25:52 +0000 (16:25 -0500)]
panfrost: Implement GL_EXT_render_snorm on Bifrost+
It turns out it's really easy.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20684>
Emma Anholt [Tue, 31 Jan 2023 22:45:46 +0000 (14:45 -0800)]
ci/lvp: Drop the subgroupbroadcast skips.
These have the same runtime as the others in the group, and with these
optimizations they no longer time out.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
Emma Anholt [Mon, 30 Jan 2023 23:33:44 +0000 (15:33 -0800)]
gallivm: Use first active invocation in some image/ssbo accesses.
These should be looking at that rather than blindly using invocation 0
(which may be junk when in control flow).
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
Emma Anholt [Mon, 30 Jan 2023 22:14:26 +0000 (14:14 -0800)]
gallivm: Use cttz instead of a loop for first_active_invocation().
This should be way faster to compile by not spamming so many loops at
LLVM, and faster to execute if LLVM didn't figure out what that loop
meant.
It looks vector reduce ops aren't really a thing, just a convenience in
the IR. We should be able to do better by counting zeroes in the
exec_mask != 0 result.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
Emma Anholt [Mon, 30 Jan 2023 21:42:48 +0000 (13:42 -0800)]
gallivm: Return 0 first_active_invocation when we know that up front.
46 -> 30 seconds on
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i16vec4 by
not spamming LLVM with so many loops.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
Emma Anholt [Mon, 30 Jan 2023 21:38:23 +0000 (13:38 -0800)]
gallivm: Refactor out a shared "get the first active invocation" loop.
Dynamic texture indices had a similar "find an active channel" loop,
though it happened to use the last active channel rather than the first.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
Emma Anholt [Mon, 30 Jan 2023 21:05:45 +0000 (13:05 -0800)]
gallivm: Optimize emit_read_invocation's first-invocation loop.
We don't need to deref invoc inside -- invoc is uniform in active
channels, so we can find our first active invocation in the loop, and then
dereference invocation once outside.
50 -> 46 seconds on
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i16vec4
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>
Alyssa Rosenzweig [Sun, 18 Dec 2022 04:03:24 +0000 (23:03 -0500)]
asahi: Lower texcoords late
This uses the new pass to lower tex coordinates late, which gets us one step
closer to preprocessing NIR at CSO create time instead of variant create time.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>
Alyssa Rosenzweig [Tue, 29 Nov 2022 03:37:31 +0000 (22:37 -0500)]
asahi: Run nir_lower_fragcolor during preprocessing
This pass needs to run early (because it depends on early I/O), but it doesn't
actually need the shader key. Why not? If we overestimate the number of render
targets, extra store_output intrinsics will be generated, but they will be
deleted by AGX tilebuffer lowering later.
Note we'll probably want something smarter than this for fragment epilogues in
the future to avoid piles of unnecessary moves.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>
Alyssa Rosenzweig [Sun, 18 Dec 2022 04:02:32 +0000 (23:02 -0500)]
nir: Add a late texcoord replacement pass
Add a second NIR pass for lowering point/texture coordinate replacement (i.e.
point sprites). Why a second one? The current pass works on derefs/variables,
which is good for drivers that don't lower I/O at all (like Zink, where the pass
originates). However, it is problematic for hardware drivers: the inputs to this
pass depend on the shader key, so we want to run the pass as late as possible to
minimize the cost of building/compiling the associated shader variants. In
particular, we need to be able to lower point sprites after lowering I/O if we
would like to lower I/O when preprocessing NIR.
The logic for early lowering and late lowering is considerably different (the
late lowering is a lot simpler), so I've split this out into a second pass
rather than trying to weld them together into one.
This pass will be used on Asahi, which currently uses the early pass. It may be
useful for other drivers as well. (Actually, it's been shipping on Asahi for a
little while now, just hasn't been sent upstream yet.)
Tested with Neverball.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Asahi Lina <lina@asahilina.net>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>
Konstantin Seurer [Thu, 26 Jan 2023 10:30:17 +0000 (11:30 +0100)]
radv: Work around shader_call_data variables in raygen shaders
Closes: #5326
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20930>
David Heidelberg [Wed, 25 Jan 2023 00:38:00 +0000 (01:38 +0100)]
ci/lavapipe: use dxvk for the traces
Since the job is manual, this stayed overlooked.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20875>
David Heidelberg [Fri, 20 Jan 2023 22:26:43 +0000 (23:26 +0100)]
ci: uprev piglit (etag md5 checksumming support)
Support for FDO etag http header.
Includes line-smooth-stipple test improvements.
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20875>
Qiang Yu [Sun, 15 Jan 2023 11:04:18 +0000 (19:04 +0800)]
aco: remove early_rast wait insert
It's done in nir position export.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sun, 25 Dec 2022 15:08:38 +0000 (23:08 +0800)]
nir,ac/llvm,aco,radv,radeonsi: remove nir_export_vertex_amd
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sun, 25 Dec 2022 14:41:39 +0000 (22:41 +0800)]
nir,ac/llvm,aco: remove nir_export_primitive_amd
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sun, 25 Dec 2022 14:27:18 +0000 (22:27 +0800)]
ac/nir/ngg,radv: ms use ac_nir_export_(primitive|position|parameter)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sat, 24 Dec 2022 11:23:55 +0000 (19:23 +0800)]
ac/nir/ngg: gs use ac_nir_export_(position|parameter)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sat, 24 Dec 2022 11:16:08 +0000 (19:16 +0800)]
ac/nir/ngg: prepare gather_vs_outputs to be used by gs
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sat, 24 Dec 2022 06:55:29 +0000 (14:55 +0800)]
ac/nir/ngg,radv,radeonsi: nogs use ac_nir_export_(position|parameter)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sat, 14 Jan 2023 14:17:47 +0000 (22:17 +0800)]
ac/nir/ngg: change clipdist_neg_mask_var type to uint32
ACO does not support 8bit ALU ops.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sat, 14 Jan 2023 14:06:32 +0000 (22:06 +0800)]
ac/nir/ngg: fix clip dist culling mask uninitialized
Fixes:
f75452918b2 ("ac/nir/ngg: support clipdist culling")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Fri, 23 Dec 2022 12:58:59 +0000 (20:58 +0800)]
ac/nir,radv,radeonsi: gs copy shader use ac_nir_export_(position|parameter)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Fri, 23 Dec 2022 09:17:54 +0000 (17:17 +0800)]
ac/nir,radv,radeonsi: legacy vs use ac_nir_export_(position|parameter)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Fri, 23 Dec 2022 12:06:07 +0000 (20:06 +0800)]
radeonsi: set nr_pos_exports outside of llvm translation
This can save an abi interface when we share position export
code with RADV.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Wed, 4 Jan 2023 02:16:19 +0000 (10:16 +0800)]
radeonsi: remove the extra handling for VS/TES primitive id
We have moved si_nir_assign_param_offsets before output lowering
pass, so there won't be primitive id store output when VS/TES here.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Wed, 4 Jan 2023 02:11:59 +0000 (10:11 +0800)]
radeonsi: update outputs written nir info
We may remove some outputs when si_nir_kill_outputs and
ac_nir_optimize_outputs, so update the outputs written
info for output lower pass to skip manipulating these
outputs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sat, 28 Jan 2023 02:17:38 +0000 (10:17 +0800)]
radeonsi: clamp vertex color in legacy gs instead of gs copy shader
gs copy shader is going to emit nir_export_amd directly so this vertex
color clamp pass which apply to nir_store_output will not work.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sat, 28 Jan 2023 08:25:11 +0000 (16:25 +0800)]
amd,radeonsi: implement nir_load_force_vrs_rates_amd in driver abi
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Sun, 29 Jan 2023 01:46:43 +0000 (09:46 +0800)]
ac/nir: add force_vrs to ac_nir_export_position
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Wed, 21 Dec 2022 07:49:43 +0000 (15:49 +0800)]
ac/nir: add ac_nir_export_parameter
For last VGT stage to export parameter outputs.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Wed, 21 Dec 2022 07:04:47 +0000 (15:04 +0800)]
ac/nir: add ac_nir_export_position
Used by last VGT stage to export position related outputs.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Mon, 19 Dec 2022 08:01:15 +0000 (16:01 +0800)]
ac/nir: gs and nogs use ac_nir_export_primitive
Mesh shader primitive export is left unchanged because it needs
extra changes for per primitive output export when export
primitive.
Mesh shader will use second channel of primitive export.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Mon, 19 Dec 2022 07:38:19 +0000 (15:38 +0800)]
aco: implement nir_export_amd
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Mon, 19 Dec 2022 06:27:56 +0000 (14:27 +0800)]
ac/llvm: implement nir_export_amd
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Qiang Yu [Mon, 19 Dec 2022 03:03:54 +0000 (11:03 +0800)]
nir: add nir_export_amd intrinsic
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>
Timur Kristóf [Mon, 30 Jan 2023 14:34:40 +0000 (15:34 +0100)]
ac/nir/cull: Alway remove zero-area triangles in face culling.
The face culling algorithm should have been disabled for
conservative overestimation because it already
(mistakenly) removed some close-to-zero area triangles.
Now that the driver disables it in that case,
let's always remove zero-area triangles.
This only costs +2 SALU instructions.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20987>
Timur Kristóf [Mon, 30 Jan 2023 14:23:12 +0000 (15:23 +0100)]
radv: Disable NGG culling when conservative overestimation is used.
Even when small primitive culling is disabled, the face culling algorithm
in ac_nir_cull can delete tiny triangles when their area is almost zero.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20987>
Constantine Shablya [Thu, 2 Feb 2023 08:45:16 +0000 (10:45 +0200)]
anv: handle ATTACHMENT_OPTIMAL layout
Closes: #8216
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21066>
Yonggang Luo [Wed, 21 Dec 2022 16:46:34 +0000 (00:46 +0800)]
util: Implement util_iround with lrintf unconditionally
Because the place that called util_iround are always ensured
that INT_MIN <= f <= INT_MAX
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19978>
Mike Blumenkrantz [Thu, 2 Feb 2023 22:15:25 +0000 (17:15 -0500)]
zink: enable bindless texture with ZINK_DESCRIPTORS=db
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>
Mike Blumenkrantz [Thu, 2 Feb 2023 22:14:36 +0000 (17:14 -0500)]
zink: implement descriptor buffer handling of bindless texture
pretty straightforward, just lazily allocating the context-based db
and then writing updates to it on-demand
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>
Mike Blumenkrantz [Thu, 2 Feb 2023 22:09:14 +0000 (17:09 -0500)]
zink: add a flag to indicate whether a descriptor buffer is bound
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>
Mike Blumenkrantz [Thu, 2 Feb 2023 22:08:35 +0000 (17:08 -0500)]
zink: break out descriptor binding into separate function
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>
Mike Blumenkrantz [Thu, 2 Feb 2023 21:14:56 +0000 (16:14 -0500)]
zink: set VK_PIPELINE_CREATE_DESCRIPTOR_BUFFER_BIT_EXT on compute pipelines
same as gfx
Fixes:
7ab5c5d36d2 ("zink: use EXT_descriptor_buffer with ZINK_DESCRIPTORS=db")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>
Mike Blumenkrantz [Thu, 2 Feb 2023 19:06:40 +0000 (14:06 -0500)]
zink: skip updating descriptor buffer sets that aren't active
this is a no-op and illegal
Fixes:
7ab5c5d36d2 ("zink: use EXT_descriptor_buffer with ZINK_DESCRIPTORS=db")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>
Mike Blumenkrantz [Thu, 2 Feb 2023 18:02:06 +0000 (13:02 -0500)]
zink: fix bindless struct member comments
this was a bit confusing having the overall substruct comment which
was occasionally wrong
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>
Mike Blumenkrantz [Thu, 2 Feb 2023 16:22:25 +0000 (11:22 -0500)]
zink: make bindless buffer_infos a union
prep for descriptor buffer handling
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>
Mike Blumenkrantz [Thu, 2 Feb 2023 15:44:12 +0000 (10:44 -0500)]
zink: enable PIPE_CAP_ALLOW_GLTHREAD_BUFFER_SUBDATA_OPT
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21073>
Marek Olšák [Wed, 1 Feb 2023 17:03:27 +0000 (12:03 -0500)]
amd/ci: update sanctuary trace sha1
I guess it's because RB+ blending is now more precise.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 31 Jan 2023 06:05:44 +0000 (01:05 -0500)]
radeonsi: set sampler COMPAT_MODE in the corresponding branch
no functional change
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 31 Jan 2023 12:30:51 +0000 (07:30 -0500)]
radeonsi: call ac_init_llvm_once before any util_queue initialization
The winsys uses util_queue, which calls atexit, so do it before the winsys
is created.
Cc: stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Wed, 25 Jan 2023 03:26:38 +0000 (22:26 -0500)]
amd/llvm: fix LLVM 15 & 16 crashes in SelectionDAG.cpp
Cc: stable
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 31 Jan 2023 11:15:34 +0000 (06:15 -0500)]
radeonsi: set NEVER as the depth compare func if depth compare is disabled
Fixes:
0c6e56c391a262bef - mesa: (more) correctly handle incomplete depth textures
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 31 Jan 2023 05:16:55 +0000 (00:16 -0500)]
amd/registers: remove confusing definitions from gfx10-rsrc.json
this will never be used and shouldn't have been added
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Mon, 30 Jan 2023 12:49:34 +0000 (07:49 -0500)]
amd: document OOB behavior on gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Fri, 27 Jan 2023 23:02:37 +0000 (18:02 -0500)]
amd: fix typo in shadowed uconfig registers on gfx11
It used an invalid offset, which hung.
Fixes:
f24f8665dbe2a - ac: implement register shadowing for gfx11
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Fri, 27 Jan 2023 04:31:38 +0000 (23:31 -0500)]
amd: sort and re-indent packet definitions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Wed, 25 Jan 2023 09:40:38 +0000 (04:40 -0500)]
amd: update late_alloc_wave64 for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Wed, 25 Jan 2023 09:40:13 +0000 (04:40 -0500)]
amd: update the cache size for gfx1103_r1
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Wed, 25 Jan 2023 09:39:03 +0000 (04:39 -0500)]
amd: change pbb_max_alloc_count for gfx11
based on PAL
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Wed, 25 Jan 2023 09:37:54 +0000 (04:37 -0500)]
amd: unify and tune the attribute ring size for gfx11
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Wed, 25 Jan 2023 07:48:44 +0000 (02:48 -0500)]
radeonsi: never set INTERPOLATE_COMP_Z
based on PAL
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Wed, 25 Jan 2023 06:19:27 +0000 (01:19 -0500)]
radeonsi: determine alpha_to_coverage robustly in si_update_framebuffer_blend_rasterizer
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Wed, 25 Jan 2023 06:10:41 +0000 (01:10 -0500)]
radeonsi: merge si_ps_key_update_framebuffer_blend & .._update_blend_rasterizer
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 23:29:28 +0000 (18:29 -0500)]
radeonsi/gfx11: always set MSAA_NUM_SAMPLES=0 for DCC_DECOMPRESS
hw requirement
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 22:06:50 +0000 (17:06 -0500)]
radeonsi: deduplicate VS/TES/GS update code
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 11:10:12 +0000 (06:10 -0500)]
radeonsi/gfx11: use new packet EVENT_WRITE_ZPASS
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 11:02:15 +0000 (06:02 -0500)]
radeonsi/gfx11: move the PIXEL_PIPE_STAT_CONTROL event into the GFX preambles
Both the normal and shadowing preamable should do this.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 05:21:47 +0000 (00:21 -0500)]
radeonsi/gfx11: fix blend->cb_target_mask dependency for shader keys
Shader keys only use cb_target_enabled_4bit. This may cause shaders to be
updated less often, but otherwise no change in behavior.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>š
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 05:05:11 +0000 (00:05 -0500)]
radeonsi/gfx11: adjust ACCUM_* fields for tessellation
based on PAL
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 04:40:36 +0000 (23:40 -0500)]
radeonsi/gfx11: add a comment why we use PRIM_GRP_SIZE <= 252
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 02:29:37 +0000 (21:29 -0500)]
radeonsi/gfx11: remove the INST_PREF_SIZE workaround
The hw does the right thing automatically. (i.e. enables or disables
the feature)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 06:08:33 +0000 (01:08 -0500)]
radeonsi: implement RB+ depth-only rendering for better perf
The explanation is in the last change of this commit.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 10:48:33 +0000 (05:48 -0500)]
amd: improve RB+ blending precision
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 02:27:34 +0000 (21:27 -0500)]
amd: update shadowed register tables for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 10:47:38 +0000 (05:47 -0500)]
amd: update SX_BLEND_OPT_EPSILON.MRT0_EPSILON enum definitions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 07:44:48 +0000 (02:44 -0500)]
amd: fix tile_swizzle on gfx11 - should be shifted by 10 bits, not 8
This reverts the radv_adjust_tile_swizzle change to unify the code.
Fixes:
529eb739fc4 - radeonsi/gfx11: add CB deltas
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 08:00:38 +0000 (03:00 -0500)]
amd: split GFX1103 into GFX1103_R1 and GFX1103_R2
Fixes:
caa09f66ae4 - amd: add chip identification for gfx1100-1103
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 04:08:36 +0000 (23:08 -0500)]
radeonsi/gfx11: unset SAMPLE_MASK_TRACKER_WATERMARK to fix hangs
Same as PAL.
Fixes:
529eb739fc4 - radeonsi/gfx11: add CB deltas
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Tue, 24 Jan 2023 10:52:17 +0000 (05:52 -0500)]
radeonsi: fix RB+ blending with sRGB formats
The epsilon for 8bpc is for the linear colorspace. There is no epsilon
for sRGB.
Fixes:
17021efc742 - radeonsi: adjust RB+ blend optimization settings
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Thu, 26 Jan 2023 19:37:58 +0000 (14:37 -0500)]
radeonsi/ci: add gfx1100 results
There are also a lot of flakes.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Marek Olšák [Fri, 27 Jan 2023 04:00:45 +0000 (23:00 -0500)]
radeonsi/ci: update gfx10.3 results
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>
Emma Anholt [Wed, 1 Feb 2023 23:23:00 +0000 (15:23 -0800)]
turnip: Make the tiling-impossible case have an impossible tile layout.
This helped me catch inappropriate tiling work being done in this case.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21004>
Emma Anholt [Wed, 1 Feb 2023 23:09:05 +0000 (15:09 -0800)]
tu: Only emit the conditional gmem subpass resolves when gmem is possible.
No sense emitting this work when the subpass deps or attachment size
prevents gmem. Noticed when I had uninit values in the tiling layout.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21004>
Emma Anholt [Tue, 31 Jan 2023 00:25:30 +0000 (16:25 -0800)]
turnip: Optimize tile sizes to reduce the number of bins.
We were aiming for very square tiles, but it's actually better for us to
reduce the number of different bins so you take fewer trips through the
geometry and keep the caches hotter. Example changes to aztec ruins on
angle:
3x3 tiles of 352x352 to 4x2 tiles of 256x512
4x5 tiles of 256x224 to 5x4 tiles of 224x256
17x11 tiles of 160x128 to 14x11 tiles of 192x128
12x7 tiles of 224x224 to 7x11 tiles of 384x128
12x8 tiles of 224x192 to 7x11 tiles of 384x128
11x6 tiles of 256x256 to 12x5 tiles of 224x288
11x7 tiles of 256x224 to 7x9 tiles of 384x160
8x4 tiles of 352x352 to 6x5 tiles of 448x288
and minecraft:
3x3 tiles of 352x352 to 4x2 tiles of 256x512
12x6 tiles of 256x256 to 3x23 tiles of 1024x64
12x7 tiles of 256x224 to 8x9 tiles of 384x160
FPS changes:
VK aztec ruins normal: 1.12478% +/- 0.213393% (n=67)
ANGLE manhattan_31: +1.42813% +/- 0.893332% (n=7).
ANGLE minecraft: no change (n=21)
ANGLE google_maps: +6.80618% +/- 2.40857% (n=4)
ANGLE trex_200: no change (n=11)
ANGLE pubg: no change (n=21)
Fixes: #8160
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21004>
Emma Anholt [Wed, 1 Feb 2023 23:20:14 +0000 (15:20 -0800)]
tu: Mark tiling impossible if we couldn't lay out gmem in the first place.
We were leaving the field undefined, which tripped me up later.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21004>
Sagar Ghuge [Wed, 1 Feb 2023 23:44:48 +0000 (15:44 -0800)]
nir: Handle other variants of image_samples properly while lowering
while lowering image_samples to one, we need to take
nir_intrinsic_image_deref_samples and
nir_intrinsic_bindless_image_samples intrinsic into account.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8211
Fixes:
ab4c2990ed4 ("intel/compiler: use lower_image_samples_to_one")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21053>
Juston Li [Tue, 31 Jan 2023 23:57:24 +0000 (15:57 -0800)]
anv: check initial cmd_buffer is chainable
Submitting a batch with the first command buffer with the simultaneous
bit set followed by a command buffer without the bit set gets past the
check and triggers this assert attempting to chain them:
../src/intel/vulkan/anv_batch_chain.c:1147: anv_cmd_buffer_chain_command_buffers: Assertion `num_cmd_buffers == 1' failed.
Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21056>
Jesse Natalie [Wed, 1 Feb 2023 20:48:24 +0000 (12:48 -0800)]
wsi/win32: We don't need a window DC for DXGI
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21049>
Jesse Natalie [Wed, 1 Feb 2023 20:48:24 +0000 (12:48 -0800)]
wsi/win32: Don't require buffer blits for software drivers
Lavapipe can directly render to a linear CPU image and then BitBlit
straight from there.
Fixes:
2f462105 ("vulkan/wsi: Hook-up DXGI swapchains and DComp")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8085
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21049>
Erik Faye-Lund [Wed, 1 Feb 2023 15:06:36 +0000 (16:06 +0100)]
anv, hasvk: remove stale TODO-files
This file hasn't really been updated since 2016, apart from a single
search-replace two years ago.
That's an eternity in ANV-land, so let's just remove these.
While we're at it, also remove the duplicate in hasvk.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21044>
Lucas Stach [Mon, 30 Jan 2023 17:58:30 +0000 (18:58 +0100)]
etnaviv: fix double scanout import of multiplanar resources
etna_resource_from_handle() is called for each plane of a multiplanar
resource, so there is no point in looping over all planes to do the
renderonly scanout import. In fact that will cause us to lose track
of the scanout imports from later planes when the earlier planes are
redoing the import, overwriting the pointer to the allocated
renderonly_scanout struct.
Drop the loop and just do the import for the current plane.
Fixes:
826f95778a4e ("etnaviv: always try to create KMS side handles for imported resources")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20993>
Emma Anholt [Thu, 2 Feb 2023 01:07:15 +0000 (17:07 -0800)]
ci: Drop the itoral-gl-terrain demo from traces.
There's an app bug in the CSM rendering that causes undefined results.
Fixes: #8212
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21055>
Georg Lehmann [Tue, 3 Jan 2023 21:54:10 +0000 (22:54 +0100)]
aco: Improve wave64 cycle estimates.
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20507>
Mike Blumenkrantz [Thu, 2 Feb 2023 16:15:18 +0000 (11:15 -0500)]
Revert "zink: fix zink_mem_type_idx_from_bits()"
This reverts commit
f7796997964bb462bcbfa6b9faca5dcf04b64e1b.
I was doing too much F2F and not enough thinking with this one
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21076>
Rose Hudson [Sat, 21 Jan 2023 22:23:33 +0000 (22:23 +0000)]
asahi: wire up shader disk cache support
Note: I (Alyssa) have squashed in some minor changes squashed in pre merge. The
rest is Rose's work :-)
Closes: #8091
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20835>
Samuel Pitoiset [Thu, 2 Feb 2023 13:24:45 +0000 (14:24 +0100)]
radv: simplify an assertion after considering RADV_FORCE_VRS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21068>
Samuel Pitoiset [Wed, 1 Feb 2023 18:14:47 +0000 (19:14 +0100)]
radv: skip compilation when possible with GPL fast-linking
When all shader stages have already been imported it's possible to
skip radv_graphics_pipeline_compile() entirely. This makes GPL
fast-linking VERY fast.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21068>