blorp: Use a non-zero MOCS for disabled constant buffers

We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is disabled constant buffers, where MOCS shouldn't matter, as
there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for these null constant
buffers; we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>

blorp: Fill in MOCS for null depth/stencil/HiZ buffers.

isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero.  We just assume a generic internal MOCS when we
have entirely NULL surfaces.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>

blorp: Fill in MOCS even for SURFTYPE_NULL surfaces.

We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is SURFTYPE_NULL surfaces, where MOCS really shouldn't matter,
as there's no actual surface to be cached.

That said, it should be harmless to set MOCS for these null surfaces;
we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>

isl: Fill in MOCS for NULL depth, stencil, and HiZ buffers.

We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is SURFTYPE_NULL depth, stencil, and HiZ buffers, where MOCS
really shouldn't matter, as there's no actual surface to be cached.

That said, it should be harmless to set MOCS for these null surfaces.
We now set the one provided in info->mocs regardless of whether any
buffers actually exist or not.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>

isl: Fill in MOCS even for SURFTYPE_NULL surfaces.

We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is SURFTYPE_NULL surfaces, where MOCS really shouldn't matter,
as there's no actual surface to be cached.

That said, it should be harmless to set MOCS for these null surfaces;
we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>

intel/genxml: Change 3DSTATE_CONSTANT_XS::MOCS to be MBZ on Gfx8.

The Broadwell PRM says: "Constant Buffer Object Control State must
always be programmed to zero."

This patch changes the MOCS field in gen8.xml to be "mbz" type, so that
it's impossible to set it to a non-zero value.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>

intel/genxml: Drop "Hierarchical Depth Buffer MOCS" field

This is redundant with the existing "MOCS" field.  We don't need both.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>

intel/genxml: Add an "mbz" data type

There are some fields which Must Be Zero, and we don't want to allow
setting them from the template struct, but we do want them in the XML
to allow them to be decoded properly, and for documentation purposes.

This adds a new "mbz" type, much like "mbo", except it doesn't set
anything in the struct.  We also update the decoder to handle it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>

intel/genxml: Fix Indirect Object Access Upper Bound on Gfx4

We had this field mislabeled as "Instruction Access Upper Bound", but
instruction state base address doesn't exist until Gfx5.  This is
supposed to be the upper bound for indirect object base address,
matching the G45 copy.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>

drirc: enable do_dce_before_clip_cull_analysis for ANSA

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12897>

glsl/drirc: add an option for gl_ClipVertex / gl_CullDistance checks

The GLSL spec says it's an error if a shader statically writes to these
2 variables.

Until this commit, Mesa refused to link a shader if it had an unused
function writing to one of these variables while another (used) function
wrote to the other.

This commit adds an option to perform dead function elimination after
the intra-stage linking step but before performing these checks.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12897>

docs: update calendar and link releases notes for 21.2.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13579>

docs: add sha256 sums for 21.2.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13579>

docs: add release notes for 21.2.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13579>

r300: improve precission of linear interpolation

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13554>

ir3/ra: Check register file upper bound when updating preferred_reg

Otherwise we could get invalid reg in get_reg()

Would fix many dEQP-VK.ssbo.phys.layout.*

Fixes: 0ffcb19b9d9fbe902224542047c389a661fbf816 "ir3: Rewrite register allocation"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13546>

radeon/vce: Limiting max supported refernce frames to 1  for h264 encoding

VCE currently restricted  max_supported reference frames to 1

Signed-off-by: shanshengwang <shansheng.wang@amd.com>
Suggested-by: Suresh Guttula <suresh.guttula@amd.com>
Acked-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13543>

ac/nir: remove bogus assertion about the position for culling

It's undefined to not export a position but some applications rely
on that. The position is always initialized to 0,0,0,1 everywhere else
if not exported.

Fixes KHR-GL46.shader_image_load_store.multiple-uniforms with Zink.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13470>

intel/pps: reuse timestamp_frequency from intel_device_info

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>

intel/pps: provide accurate min sampling period

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>

intel/dev: printout timestamp period

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>

docs: put a list of commands to setup perfetto

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>

pps: add an intel config file

It was useful to set a colleague up on perfetto.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>

pps: remove counter_ids fields

Those appear not to be recognized anymore by perfetto.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>

intel/dev/test: Assert (verx10 / 10) == ver

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13568>

aco: use std::vector and IDSet in RA validator

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13541>

broadcom/compiler: padding fixes to QPU assembly dumps

When there are dst/src modifiers it is pretty common that instructions
take too much space and lead to alignment issues that make code a lot
harder to read, so align the MUL and SIG columns a bit wider to avoid
this:

Before:

0x380021828003faa8 fmax  rf2, rf42.abs, rf40.abs; nop
0x3800f186c503f0f0 fcmp.pushc  -, rf3, rf48; nop
0x380c038b85b83282 fmax  rf11, rf10, rf2; mov.ifa  rf14, rf46
0x3800219ab503f359 and  rf26, rf13, rf25; nop
0x3820f186c503f2f0 fcmp.pushc  -, rf11, rf48; nop           ; thrsw
0x382c013fb5b8368e and  rf63, rf26, rf14; mov.ifa  rf4, rf46; thrsw
0x38002185b503ffc4 and  rf5, rf63, rf4  ; nop
0x38002186b503f141 and  rf6, rf5, rf1   ; nop
0x382031873503f186 vfpack  tlb, rf6, rf6; nop               ; thrsw
0x380031873503f18f vfpack  tlb, rf6, rf15; nop
0x38003186bb03f000 nop                  ; nop

After:

0x380021828003faa8 fmax rf2, rf42.abs, rf40.abs  ; nop
0x3800f186c503f0f0 fcmp.pushc -, rf3, rf48       ; nop
0x380c038b85b83282 fmax rf11, rf10, rf2          ; mov.ifa rf14, rf46
0x3800219ab503f359 and rf26, rf13, rf25          ; nop
0x3820f186c503f2f0 fcmp.pushc -, rf11, rf48      ; nop                         ; thrsw
0x382c013fb5b8368e and rf63, rf26, rf14          ; mov.ifa rf4, rf46           ; thrsw
0x38002185b503ffc4 and rf5, rf63, rf4            ; nop
0x38002186b503f141 and rf6, rf5, rf1             ; nop
0x382031873503f186 vfpack tlb, rf6, rf6          ; nop                         ; thrsw
0x380031873503f18f vfpack tlb, rf6, rf15         ; nop
0x38003186bb03f000 nop                           ; nop

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13545>

zink: always use explicit lod for texture() when legal in non-fragment stages

implicit lod is something else entirely

fixes #5566

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13563>

zink: set aspectMask for renderpass2 VkAttachmentReference2 structs

this is otherwise just garbage

fixes #5569

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13561>

zink: use align64 for allocation sizes

avoid 32bit sint overflows

fixes #5568

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13560>

zink: cache bo SpvId array types

this cuts down on a truckload of useless new validation spam

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13559>

venus: implement vn_buffer_cache_entries_create

1. advertise high hit rate cache combinations, and we should limit the
   caches to those only require device memory pool alloc
2. use size = 1 to ask for buffer memory requirements so that we do a
   sanity check on our assumption of returned size and alignment. For
   implementations don't meet our assumption, continue without cache.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

venus: implement vn_buffer_cache_get_memory_requirements

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

venus: implement vn_buffer_get_max_buffer_size

This change estimates the max_buffer_size with quick sort. Try to
avoid some traffic upon device creation time, but not worth adding a
buffer simple create api to avoid the extra requirement query traffic
since this is temporary.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

venus: add buffer cache init and usage flows

1. struct vn_buffer_cache_entry for buffer memory requirements
2. struct vn_buffer_cache for all buffer related cached info
3. implement vn_buffer_cache_init
4. implement vn_buffer_cache_fini
5. empty vn_buffer_get_max_buffer_size
6. empty vn_buffer_cache_entries_create
7. implement vn_buffer_cache_entries_destroy
8. empty vn_buffer_cache_get_memory_requirements

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

venus: add struct vn_image_memory_requirements

This aligns with vn_buffer_memory_requirements and can potentially
simplify future image memory requirements cache init.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

venus: add struct vn_buffer_memory_requirements

This will simplify later buffer cache api.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

venus: refactor the ahb buffer mem_type_bits query api

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

venus: refactor to add vn_buffer_init

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

venus: refactor to add vn_device_init

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

venus: release queues on device creation failure

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>

zink: add better handling for CUBE_COMPATIBLE bit

this check was illegal because the usage bits weren't yet populated,
so add another check after usage bits are determined to figure out if
CUBE_COMPATIBLE can be applied

additionally, checking sample counts was never needed since the spec
prohibits CUBE_COMPATIBLE use with multisampling

zink DEBUG: ERR: 'Validation Error: [ VUID-vkGetPhysicalDeviceImageFormatProperties-usage-requiredbitmask ] Object 0: VK_NULL_HANDLE, type = VK_OBJECT_TYPE_DEVICE; | MessageID = 0x991b3105 | vkGetPhysicalDeviceImageFormatProperties: value of usage must not be 0. The Vulkan spec states: usage must not be 0 (https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/vkspec.html#VUID-vkGetPhysicalDeviceImageFormatProperties-usage-requiredbitmask)'

Fixes: 71494c4874c ("zink: only mark resources as cube-compatible if supported")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12580>

venus: assign valid memoryTypeIndex of exportable ahb memory for image

The current AHB spec leaves the input memoryTypeIndex undefined when
allocating exportable AHB memory backing an external image.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13537>

amd/rgp: Use VGH clocks for RGP workaround.

Hear that it matters for RGP. This is the most likely scenario where
we would hit this workaround, given the tooling for profiling on the
deck will set profile_peak as workaround for hangs.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13534>

ci/piglit-runner: Merge piglit-driver-*.txt files into driver-*.txt.

The test names are definitely unique (deqp has specific prefixes, piglit
uses '@' as a separator instead of '.'), so we can just have a single file
regardless of test type.  Merges the two groups of xfails together so you
can't mix up which file to edit (I certainly have), and so that we don't
need to introduce yet another set of files when we add gtest for libva.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13517>

ci/deqp-runner: Rename the deqp-drivername-*.txt files to drivername-*.txt

We have two testsuites with the same format for fails/flakes/skips files,
and test names that are definitely unique.  As I'm about to add a third
testsuite (gtest for libva-utils), so let's have just one file each for
fails/flakes/skips instead of one per type of testsuite.  This starts the
move with just the bulk rename of deqp.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13517>

iris: destroy our mutexes a little later

While there seems to be no bug with the state things are today, I was
recently doing some debugging and put an iris_bo_wait() before a
bo_close() in iris_bufmgr_destroy(), which caused an issue since the
bo_deps_lock mutex had already been destroyed.

Since there are quite a few things we do with the bufmgr after
destroying the mutexes, I figured we should probably postpone mutex
destruction in order to be a little safer against future code
modifications like the one I just did.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13494>

docs: update calendar for 21.3.0-rc3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13557>

venus: refactor private descriptor_set helpers to be private

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13522>

anv: Enable CCS for storage image formats

v2: (Jason Ekstrand)
- Restructure if condition.
- Add early return.

v3: (Felix)
- Don't set aux_supported to false for storage image on XeHPG.

v4: (Nanley)
- Check image view format against fmt_list.
- Add helper anv_get_isl_format_with_usage.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3606>

anv: Pass correct aux usage while filling out surface state

While filling out surface state, pass correct aux usage for storage
images as we support compression on XeHPG.

v2: (Jason Ekstrand)
- Move assertion down a bit
- Use general layout aux usage

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3606>

zink: move all shader bo/sharedmem access to compiler passes

this moves more code to nir passes, which makes it easier to debug
and also allows deleting some much-more-difficult-to-read ntv code

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>

zink: add more glsl base types to get_glsl_basetype()

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>

zink: move all 64-32bit shader store rewriting to nir pass

this also enables natural 64bit stores on drivers that support it

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>

zink: move shared intrinsic offset adjustments to compiler passes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>

zink: move ssbo store offset adjustment to compiler passes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>

zink: move all 64-32bit shader load rewriting to nir pass

this also enables natural 64bit loads on drivers that support it

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>

zink: run lower_io_to_scalar before rewriting bo access

this is happening in ntv anyway, so move it to the compiler here

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>

zink: move bo load offset adjustment to compiler passes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>

zink: run optimize_nir() only once during compile

running all the optimizer passes repeatedly is stupid

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13484>

nir/lower_io_to_scalar: add support for bo and shared io

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13485>

ci/radeonsi: Use a deqp-runner suite suite for stoney.

This should make it easier to tune the runtime, and enable KHR-GL* tests
in the future.  (Not done currently because something in KHR-GL* causes
oomkiller).

This drops the redundant FDO_CI_CONCURRENT settings, since the default on
these boards is 4 anyway.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13504>

util: use anonymous file for memory fd creation

The original implementation in os_memory_fd.c always uses memfds.
Replace this by using the already existing os_create_anonymous_file in
order to support older systems or systems without memfd.

Fixes: 1166ee9caf3 ("gallium: add utility and interface for memory fd allocations")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13331>

radv: don't use a separate cache entry for GS copy shaders

This seems simpler and probably faster.

This also fixes a warning for these CTS tests:
dEQP-VK.pipeline.creation_feedback.graphics_tests.vertex_stage_geometry_stage_delayed_destroy_fragment_stage_delayed_destroy
dEQP-VK.pipeline.creation_feedback.graphics_tests.vertex_stage_geometry_stage_fragment_stage
because we no longer set found_in_application_cache=false for pipelines
with NGG GS.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13528>

radv: fix invalid wait_dst_stage_mask type

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13354>

glsl/nir/linker: Also remove image variables

If we don't, then the array shrinker may shrink them to an array of zero
images which can cause GLSL serialization to blow up but only the next
time the GLSL shader is loaded from the disk cache.

Fixes: b8ee37472d3e ("glsl: Use nir_var_mem_image for images")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5520
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13412>

broadcom/compiler: fix condition encoding bug

When both AC and MC are set, AC is encoded in bits 0..1 not 0..3.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13527>

broadcom/compiler: rework simultaneous peripheral access checks

This was not quite correct in that our checks for the allowed cases
were not checking that there were no other peripheral access other
than the ones allowed.

For example, we allowed  wrtmuc signal and TMU write other than
TMUC, and we also allowed TMU read and VPM read/write. But we
cannot allow wrtmuc with TMU write other than TMUC and at the
same time a VPM write for example, so we can't just check if we
have a combination of allowed peripherals, we still need to check
that those are the only ones in use by the combined instructions.

Another example is that even if we allow a TMU write (other than TMUC)
with a wrtmuc signal, the resulting instruction must still have just
one TMU write other than TMUC, but we were allowing the merge if one
instruction signaled wrtmuc and the other wrote to tmu other than tmuc
without testing if the combined result would have 2 tmu writes.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13527>

gbm: add GBM_FORMAT_GR1616 and RG1616

Only GR1616 has a corresponding DRI format.

Signed-off-by: Manuel Stoeckl <code@mstoeckl.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13501>

gbm: add missing R16 case in gbm_bo_get_bpp

Signed-off-by: Manuel Stoeckl <code@mstoeckl.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13523>

radv: Add bufferDeviceAddressMultiDevice support.

We don't support multiple devices so this is a nop. However, Baldurs Gate 3 enables
this and with the new more complete checks this causes device creation to fail.

Fixes: 2e5718c9574 ("vulkan: provide common functions to check device features")
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5509
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13482>

glthread: add a trivial thread-safe way to skip display list execution

There are apps that never put state changes into display lists.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13403>

glthread: add an option to make glCheckFramebufferStatus a no-op

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13403>

glthread: don't sync for glIsEnabled with a few enums

viewperf benefits

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13403>

glthread: don't execute display lists if they have no effect

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13403>

nir/lower_samplers_as_deref: rewrite more image intrinsics

"I think we want to lower them."

-Jason "And I do know how the pass works" Ekstrand

fixes #5540

cc: mesa-stable

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13489>

zink: more accurately update samplemask for fs shader keys

the fs samplemask needs to be updated on framebuffer rebind and on
fs bind to ensure that the key gets updated in time for the pipeline
change

fixes #5559

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13531>

zink: fix gl_SampleMaskIn spirv generation

the uint[1] -> uint dance is only relevant on the first load, so move
the variable type shuffling inside the create block to avoid breaking successive
loads

fixes #5543

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13488>

radv: fence->user_ptr and ctx->fence_map are now totally unused.

Garbage collect them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13525>

mesa: Require MRT support for GL3/ES3

OpenGL 3.0 requires the driver can draw to 8 simultaneous render
targets. Similarly, OpenGL ES 3.0 requires the driver can draw to 4
simultaneous render targets. Fix the version computation logic to take
this into account.

On Mali T720, we support ~all features of OpenGL ES 3.1 except we only
support a single render target. Mali T720 should advertise OpenGL 2.1
and OpenGL ES 2.0 only. With the previous logic, it incorrectly
advertised OpenGL ES 3.1.

v2: Lie about the minimum for GL 3.0 to make freedreno a3xx happy. Add
Emma's reviewed-by.

v3: Update the Mali T720 CI expectations. There are tests that pass on
GLES3 but not GLES2. Unclear if these are dEQP bugs or Mesa bugs, lima
hits the same issues. Add them to the known fails

Note to mesa-stable maintainers: this downgrades the OpenGL version
advertised on Mali T720. As such, this patch should apply to the
unreleased 21.3 (Eric) but should NOT be backported to any released Mesa
versions (21.2 or older should NOT have this patch). This is a bit of a
compromise; Emma agreed with this plan on IRC.

Reported-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net> [v2]
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> [v2]
Cc: 21.3 mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13455>

microsoft/compiler: Use memcpy instead of a union to write dxil_features

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13496>

nir/lower_blend: Use correct clamp for SNORM

nir_lower_blend was written against the OpenGL ES 3.2 specification,
which does not support blending SNORM render targets. The ES spec
says that non-floating point buffers get clamped to [0, 1] before
blending. The story is not so simple: SNORM buffers are blendable in
OpenGL and must clamped to [-1, 1] rather than [0, 1]. Handle this case.

NIR does have the fsat_signed_mali instruction to clamp to [-1, 1], but
it is only implemented in Panfrost, and this pass is in common code.
Open code it instead. Panfrost optimizes the open coded version, so this
is good enough.

Fixes SNORM subtests of Piglit arb_texture_view-rendering-formats.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13499>

panvk: Pass through alpha_zero_nop/one_store flags

When constructing the Internal Blend Descriptor for fixed-function
blending, set the alpha_zero_nop/one_store flags based on the given
equation.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13508>

panfrost: Pass through alpha_zero_nop/one_store

Compute whether these flags can be set when constructing the blend CSO
and pass them in the appropriate place in the Internal Blend Descriptor.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13508>

panfrost: Test alpha_zero_nop/one_store predicates

For each blend mode in our blending unit tests, add whether we can set
the alpha_zero_nop and alpha_one_store flags and check against the
predicates.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13508>

panfrost: Add alpha_zero_nop/one_store predicate

Some Mali GPUs can avoid storing to the tilebuffer if src alpha = 0, and
can replace blending with a store if src alpha = 1. This saves power in
the common case of alpha blending. Add predicates to check if these
optimizations are valid for a given blend equation.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13508>

panfrost: Rename depth bias fields

Make it clear that the distinction is the facingness of the primitives
the depth bias applies to.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13509>

iris: Drop hint if primitive id is required or not

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13474>

anv: Drop hint if primitive id is required or not

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13474>

intel/compiler: Track primitive id in domain/evaluation shader

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggeted-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13474>

intel/genxml: Add new Primitive ID Not Required bit field to 3DSTATE_DS

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13474>

zink: don't add dynamic vertex pipeline states if no attribs are used

adding the states requires that vertex attribs be bound, but it's illegal
to bind 0 attribs

cc: mesa-stable

fixes #5558

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13519>

intel/compiler: Don't use SIMD larger than needed for workgroup

Unless we are combining multiple workgroups in the same HW thread,
there's no advantage of using SIMD16 when SIMD8 already fits the
entire workgroup.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13249>

intel/compiler: Use SIMD selection helpers for variable workgroup size

Variable workgroup size works by compiling as much SIMD variants as
possible and then selecting the right one during dispatch (when the
actual workgroup size is passed to us).

Instead of replicating the logic in a separate function, reuse the
same logic for regular SIMD selection.  And move function for that
together with the remaining simd selection functions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13249>

intel/compiler: Use SIMD selection helpers for CS

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13249>

intel/compiler: Add helpers to select SIMD for compute shaders

Clean up the logic and move it to functions that work with prog_data
attributes to select the right SIMD.  This shouldn't change any
behavior compared to the original.

Having it extracted will allow reuse by Task/Mesh and make it easier
to write tests.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13249>

zink: stop exporting PIPE_SHADER_CAP_FP16_DERIVATIVES

spirv doesn't support this

fixes #5561

cc: mesa-stable

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13530>

microsoft/spirv_to_dxil: turn sysvals into input varyings

Fixes: b47090c5b33 ("spirv: Always declare FragCoord as a sysval")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13276>

anv: fix push constant lowering with bindless shaders

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9fa1cdfe7ffd ("intel/rt: Implement push constants as global memory reads")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13529>

zink: add notes about binding points which aren't counted in util funcs

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13490>