Gerhard Sittig [Wed, 5 Jun 2013 12:51:08 +0000 (14:51 +0200)]
ac14xx: re-order the recovery condition checks
re-order the conditions which make the recovery system startup: combine
those conditions which were explicitly initiated (key press, software
request) and those which post-process error conditions (installer issues)
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Gerhard Sittig [Wed, 5 Jun 2013 12:51:07 +0000 (14:51 +0200)]
ac14xx: minor improvement in diagnostics
- minor rewording of diagnostics output
- make diagnostics optional and off by default
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Gerhard Sittig [Wed, 5 Jun 2013 12:51:06 +0000 (14:51 +0200)]
ac14xx: cleanup comments in the board support
fix typos, minor rephrasing, remove obsolete notes and TODO items
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Gerhard Sittig [Wed, 5 Jun 2013 12:51:05 +0000 (14:51 +0200)]
ac14xx: fix a potential NULL deref in diagnostics
getenv() immediately after setenv() may perfectly legally return NULL, so
make sure to not deference an invalid pointer when creating diagnostic output
Signed-off-by: Gerhard Sittig <gsi@denx.de>
Rajeshwari Shinde [Mon, 24 Jun 2013 11:17:23 +0000 (16:47 +0530)]
CONFIG: EXYNOS5: Enable silent console
This patch enables CONFIG_SILENT_CONSOLE for EXYNOS5.
This patch also removes the hardcoding of UART port from
exynos5250 config.
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Shinde [Mon, 24 Jun 2013 11:17:22 +0000 (16:47 +0530)]
S5P: Serial: Add fdt support to driver
This patch adds FDT support to the serial s5p driver.
At present disabling the serial console (from the device tree) crashes
U-Boot. Add checks for this case, so that execution can continue without
a serial console.
It also enables the serial_s5p driver recognize the silent_console option.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Shinde [Mon, 24 Jun 2013 11:17:21 +0000 (16:47 +0530)]
EXYNOS5: FDT: Add serial device node values
This patch adds the device node required for serial driver
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Shinde [Mon, 24 Jun 2013 11:17:20 +0000 (16:47 +0530)]
EXYNOS5: FDT: Add compatible strings for Serial
Add required compatible information for s5p serial driver
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Bernie Thompson [Mon, 15 Apr 2013 17:34:34 +0000 (10:34 -0700)]
exynos: Adjust the starting MIF voltage to 1.05v
Some Exynos5250 silicon may require 1.05v on the MIF to be stable, so to be
safe we can default to 1.05v instead of 1.00v. This can be set optimally later
in the boot process by the kernel.
The 0x6 value for 1.05v comes from the MAX77686 datasheet.
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Amar [Thu, 4 Apr 2013 06:27:06 +0000 (02:27 -0400)]
EXYNOS5: I2C: Add FDT and non-FDT support for I2C
This patch updates the function board_i2c_init() to add support for both
FDT and non-FDT for I2C, and initialise the I2C channels.
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Jagannadha Sutradharudu Teki [Fri, 21 Jun 2013 13:49:03 +0000 (19:19 +0530)]
sf: Warn to use BAR for > 16MiB flashes
Warning for > 16MiB flashes to #define CONFIG_SPI_FLASH_BAR
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Fri, 21 Jun 2013 13:49:02 +0000 (19:19 +0530)]
sf: Add debug messages on spi_flash_read_common
- Added debug's on spi_flash_read_common()
- Added space
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Fri, 21 Jun 2013 13:49:01 +0000 (19:19 +0530)]
sf: Place the sf calls in proper order
Placed the sf calls in proper order - erase/write/read
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Fri, 21 Jun 2013 13:49:00 +0000 (19:19 +0530)]
sf: Unify spi_flash write code
Move common flash write code into spi_flash_write_common().
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
Jagannadha Sutradharudu Teki [Fri, 21 Jun 2013 10:26:30 +0000 (15:56 +0530)]
sf: Add flag status register polling support
Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.
Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagannadha Sutradharudu Teki [Sun, 26 May 2013 18:07:11 +0000 (23:37 +0530)]
sf: Remove spi_flash_cmd_poll_bit()
There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagannadha Sutradharudu Teki [Mon, 10 Jun 2013 18:11:57 +0000 (23:41 +0530)]
sf: spansion: Add support for S25FL512S_64K
Add support for Spansion S25FL512S_64K SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Tue, 16 Apr 2013 14:53:48 +0000 (20:23 +0530)]
sf: stmicro: Add support for N25Q1024A
Add support for Numonyx N25Q1024A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Tue, 16 Apr 2013 14:52:48 +0000 (20:22 +0530)]
sf: stmicro: Add support for N25Q1024
Add support for Numonyx N25Q1024 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Tue, 16 Apr 2013 14:50:12 +0000 (20:20 +0530)]
sf: stmicro: Add support for N25Q512A
Add support for Numonyx N25Q512A SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Tue, 16 Apr 2013 14:48:29 +0000 (20:18 +0530)]
sf: stmicro: Add support for N25Q512
Add support for Numonyx N25Q512 SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Tue, 11 Jun 2013 16:06:20 +0000 (21:36 +0530)]
sf: Use spi_flash_addr() in write call
Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagannadha Sutradharudu Teki [Wed, 19 Jun 2013 10:03:58 +0000 (15:33 +0530)]
sf: Add bank addr code in CONFIG_SPI_FLASH_BAR
Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.
It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagannadha Sutradharudu Teki [Fri, 31 May 2013 10:30:36 +0000 (16:00 +0530)]
sf: Update sf read to support all sizes of flashes
This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.
The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1:
c956f600cbb0943d0afe1004cdb503f4fcd8f415)
With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s
sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagannadha Sutradharudu Teki [Thu, 30 May 2013 14:54:14 +0000 (20:24 +0530)]
sf: Update sf to support all sizes of flashes
Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility
The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.
As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagannadha Sutradharudu Teki [Wed, 19 Jun 2013 10:07:09 +0000 (15:37 +0530)]
sf: Read flash bank addr register at probe time
Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagannadha Sutradharudu Teki [Wed, 19 Jun 2013 10:01:23 +0000 (15:31 +0530)]
sf: Discover the bank addr commands
Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.
Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Thu, 13 Jun 2013 15:07:19 +0000 (20:37 +0530)]
sf: Add bank address register writing support
This patch provides support to program a flash bank address
register.
extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.
reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Axel Lin [Fri, 14 Jun 2013 13:13:32 +0000 (21:13 +0800)]
spi: mxc_spi: Use DIV_ROUND_UP at appropriate places
This change slightly improves readability.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Axel Lin [Fri, 14 Jun 2013 13:12:19 +0000 (21:12 +0800)]
spi: cf_qspi: Use DIV_ROUND_UP at appropriate place
This change slightly improves readability.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Jagannadha Sutradharudu Teki [Thu, 30 May 2013 11:04:19 +0000 (16:34 +0530)]
sf: winbond: Add support for W25QXXXFV
Add support for Winbond W25QXXXFV SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Mon, 27 May 2013 19:25:00 +0000 (00:55 +0530)]
sf: winbond: Add support for W25Q16DW
Add support for Winbond W25Q16DW SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Mon, 27 May 2013 19:19:26 +0000 (00:49 +0530)]
sf: winbond: Add support for W25Q128FW
Add support for Winbond W25Q128FW SPI flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Mon, 27 May 2013 19:11:58 +0000 (00:41 +0530)]
sf: winbond: Update the names for W25Q 0x40XX ID's flash parts
Use the exact names for W25Q 0x40XX ID's flash parts, as the same
sizes of flashes comes with different ID's. so-that the distinguishes
becomes easy with this change.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Jagannadha Sutradharudu Teki [Fri, 14 Jun 2013 15:33:51 +0000 (21:03 +0530)]
sf: spansion: Correct name of S25FL128S 64K Sector part
Corrected the name of S25FL128S 64K sector part SPI flash,
S25FL128S supported has been added in below commit
"sf: spansion: Add support for S25FL128S"
(sha1:
1bfb9f156aa66cca6bb9c773867a1f02a84b14be)
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Mike Dunn [Fri, 21 Jun 2013 16:12:28 +0000 (09:12 -0700)]
pxa: fix memory coherency problem after relocation
On the xscale, the icache must be invalidated and the write buffers drained
after writing code over the data bus, even if the caches are disabled. Tested
on the pxa270.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Mike Dunn [Fri, 21 Jun 2013 16:12:27 +0000 (09:12 -0700)]
pxa: use -mcpu=xscale compiler option
Pass '-mcpu=xscale' to the compiler instead of march and mtune. This will cause
gcc to define the __XSCALE__ macro.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Mike Dunn [Mon, 17 Jun 2013 17:47:28 +0000 (10:47 -0700)]
pxa: turn icache off in cpu_init_crit()
The comment in the low-level initialization function cpu_init_crit() says that
the caches are being disabled, but (oddly) the icache is actually turned on.
This is probably not a good idea prior to relocating code, so this patch turns
it off. Tested on the pxa270.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Mike Dunn [Tue, 18 Jun 2013 18:08:51 +0000 (11:08 -0700)]
pxa: palmtreo680 flash programming utility
This adds a userspace linux utility that writes the u-boot image to an mtd
partition on the docg4 nand flash.
A special utility is required to do this because u-boot is partially loaded by
an initial program loader (IPL) that is permanently programmed to the boot
region of the flash. This IPL expects the image to be written in a unique
format. The characteristics of this format can be summarized as follows:
- Flash blocks to be loaded must have a magic number in the oob bytes of the
first page of the block.
- Each page must be written redundantly in the subsequent page.
- The integrated flash controller's "reliable mode" is used, requiring that
alternate 2k regions (4 pages) are skipped when writing.
For these reasons, a u-boot image can not be written using nandwrite from
mtd-utils.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Mike Dunn [Tue, 18 Jun 2013 18:08:50 +0000 (11:08 -0700)]
pxa: add support for palmtreo680 board
This patch adds support for the Palm Treo 680 smartphone. A quick overview of
u-boot implementation on the treo 680...
The treo 680 has a Diskonchip G4 nand flash chip. This device has a 2k region
that maps to the system bus at the reset vector in a NOR-like fashion so that it
can be used as the boot device. The phone is shipped with this 2k region
configured as write-protected (can't be modified) and programmed with an initial
program loader (IPL). At power-up, this IPL loads the contents of two flash
blocks to SDRAM and jumps to it. The capacity of the two blocks is not large
enough to hold all of u-boot, so a u-boot SPL is used. To conserve flash space,
these two blocks and the necessary number of subsequent blocks are programmed
with a concatenated spl + u-boot image. That way, the IPL will also load a
portion of u-boot proper, and when the spl runs, it relocates the portion of
u-boot that the IPL has already loaded, and then resumes loading the remaining
part of u-boot before jumping to it.
The default_environment is used (CONFIG_ENV_IS_NOWHERE) because I didn't think
that having a writable environment was worth the cost of a flash block, although
adding it would be straightforward. I abuse the CONFIG_EXTRA_ENV_SETTINGS
option to specify the usbtty for the console (CONFIG_SYS_CONSOLE_IS_IN_ENV).
Support for the LCD is included, but currently it is only useful for displaying
the u-boot splash screen. But if u-boot is built without the usbtty console, it
does display the auto-boot progress nicely.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Tom Rini [Sat, 22 Jun 2013 11:38:12 +0000 (07:38 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm
Albert ARIBAUD [Tue, 11 Jun 2013 12:17:35 +0000 (14:17 +0200)]
arm: optimize relocate_code routine
Use section symbols directly
Drop support for R_ARM_ABS32 record types
Eliminate unneeded intermediate registers
Optimize relocation table iteration
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Albert ARIBAUD [Tue, 11 Jun 2013 12:17:34 +0000 (14:17 +0200)]
arm: make __rel_dyn_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain relocation symbols yet remain
unchanged.
__rel_dyn_start and __rel_dyn_end each requires
its own output section; putting them in relocation
sections changes their flags and breaks relocation.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Albert ARIBAUD [Tue, 11 Jun 2013 12:17:33 +0000 (14:17 +0200)]
arm: make __image_copy_{start, end} compiler-generated
This change is only done where needed: some linker
scripts may contain __image_copy_{start,end} yet
remain unchanged.
Also, __image_copy_end needs its own section; putting
it in relocation sections changes their flags and makes
relocation break.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Albert ARIBAUD [Tue, 11 Jun 2013 12:17:32 +0000 (14:17 +0200)]
arm: generalize lib/bss.c into lib/sections.c
File arch/arm/lib/bss.c was initially defined for BSS only,
but is now going to also contain definitions for other
section-boundary-related symbols, so rename it for better
accuracy.
Also, remove useless 'used' attributes.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Albert ARIBAUD [Tue, 11 Jun 2013 12:17:31 +0000 (14:17 +0200)]
remove all references to .dynsym
Discard all .dynsym sections from linker scripts
Remove all __dynsym_start definitions from linker scripts
Remove all __dynsym_start references from the codebase
Note: this touches include/asm-generic/sections.h, which
is not ARM-specific, but actual uses of __dynsym_start
are only in ARM, so this patch can safely go through
the ARM repository.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Albert ARIBAUD [Tue, 11 Jun 2013 12:17:30 +0000 (14:17 +0200)]
arm: ensure u-boot only uses relative relocations
Add a Makefile target ('checkarmreloc') which
fails if the ELF binary contains relocation records
of types other than R_ARM_RELATIVE.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Scott Wood [Thu, 20 Jun 2013 17:45:31 +0000 (12:45 -0500)]
nand: Don't call adjust_size_for_badblocks for erase
adjust_size_for_badblocks reduces the operation size to account
for the block skipping done by the read/write functions when an
interval (partition name or whole chip) is specified rather than a data
amount.
Erase does not do block skipping, except for erase.spread which takes
a data amount rather than an interval (and thus already does not call
adjust_size_for_badblocks). Calling adjust_size_for_badblocks when
block skipping is not done means that if bad blocks are present,
the "nand erase.part" and "nand erase.chip" commands will fail to erase
blocks at the end of the interval.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Harvey Chapman <hchapman@3gfp.com>
Acked-by: Heiko Schocher <hs@denx.de>
Ajay Kumar [Thu, 4 Apr 2013 14:25:19 +0000 (10:25 -0400)]
video: exynos_fb: Add the missing #else clause
This patch fixes a bug introduced while adding DT support
to Exynos FIMD driver:
commit
c23f3157d69bbb6c044256870f745f195b12431e
Author: Ajay Kumar <ajaykumar.rs@samsung.com>
Date: Thu Feb 21 23:53:01 2013 +0000
video: exynos_fb: add DT support for FIMD driver
Even though this part of code was missing, things were working
fine on Exynos5250 because, samsung_get_base_fimd() used
to give the correct base address for Exynos5250 FIMD.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Simon Glass [Sat, 11 May 2013 03:24:00 +0000 (20:24 -0700)]
exynos: Enable mmc for snow
Snow has an internal eMMC and an external SD card. Enable these in the
device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Chunhe Lan [Fri, 14 Jun 2013 08:21:48 +0000 (16:21 +0800)]
powerpc/85xx: Add P1023RDB board support
P1023RDB Specification:
-----------------------
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to Atheros AR8035 GETH PHY
PCIe:
Three mini-PCIe slots
USB:
Two USB2.0 Type A ports
I2C:
AT24C08 8K Board EEPROM (8 bit address)
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Thu, 13 Jun 2013 04:44:00 +0000 (10:14 +0530)]
powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
init_tlbs() initialize all the TLB entries required for the system.
So disable DEBUG TLB entry before TLB entries initialization.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 31 May 2013 15:48:04 +0000 (08:48 -0700)]
powerpc/pixis: Fix pixis help message
"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Chris Packham [Sun, 26 May 2013 22:51:46 +0000 (10:51 +1200)]
powerpc/CoreNet: Allow pbl images to take u-boot images != 512K
Instead of assuming that SYS_TEXT_BASE is 0xFFF80000 calculate the initial
pbl command offset by subtracting the image size from the top of the
24-bit address range. Also increase the size of the memory buffer to
accommodate a larger output image.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Axel Lin [Sun, 26 May 2013 07:00:30 +0000 (15:00 +0800)]
powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE
If a variable is used as array subscript, it's valid value range is
0 ... ARRAY_SIZE -1.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Ying Zhang [Mon, 20 May 2013 06:07:26 +0000 (14:07 +0800)]
Makefile: move the common makefile line to public area
Move the common makefile line shared by the SPL and non-SPL to the public area,
so that we can avoid excessive SPL symbols. Some of them will be used by the
SPL later.
This patch is on top of the patch "common/Makefile: Add new symbol
CONFIG_SPL_ENV_SUPPORT for environment in SPL".
Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Ying Zhang [Mon, 20 May 2013 06:07:25 +0000 (14:07 +0800)]
common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPL
There will need the environment in SPL for reasons other than network
support (in particular, hwconfig contains info for how to set up DDR).
Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT
for environment in common/Makefile.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Ying Zhang [Fri, 7 Jun 2013 09:25:16 +0000 (17:25 +0800)]
powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS
There will clear the BSS in the function clear_bss(), the reset address of
the BSS started from the __bss_start, and increased by four-byte increments,
finally stoped depending on the address is equal to the _bss_end. If the end
address __bss_end is not alignment to 4byte, it will be an infinite loop.
1. The reset action stoped depending on the reset address is greater
than or equal the end address of the BSS.
2. The end address of the BSS should be 4byte aligned. Because the reset unit
is 4 Bytes.
This patch is on top of the patch "powerpc/mpc85xx: support application
without resetvec segment in the linker script".
Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Ying Zhang [Mon, 20 May 2013 06:07:23 +0000 (14:07 +0800)]
powerpc/mpc85xx: support application without resetvec segment in the linker script
For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.
So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Fri, 17 May 2013 08:52:34 +0000 (14:22 +0530)]
board/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI define
PCIe TLB should be created with CONFIG_PCI defined
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Fri, 17 May 2013 08:10:52 +0000 (13:40 +0530)]
board/b4860qds: Relax NOR flash teadc timing parameter
Relax parameters to give address latching more time to setup.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Scott Wood [Wed, 15 May 2013 22:50:13 +0000 (17:50 -0500)]
powerpc/mpc85xx: work around erratum A-006593
Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".
The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1. This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Mingkai Hu [Thu, 16 May 2013 02:18:13 +0000 (10:18 +0800)]
fsl_ifc: add support for different IFC bank count
Calculate reserved fields according to IFC bank count
1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
error on some devices that does not have IFC controller.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:50 +0000 (16:30 +0800)]
powerpc/t4qds: Slave module for boot from SRIO and PCIE
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:49 +0000 (16:30 +0800)]
powerpc/t4qds: Enable master module for Boot from SRIO and PCIE
T4 can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:48 +0000 (16:30 +0800)]
powerpc/b4860qds: Slave module for boot from SRIO and PCIE
When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
7. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:47 +0000 (16:30 +0800)]
powerpc/b4860qds: Enable master module for boot from SRIO and PCIE
B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.
You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:46 +0000 (16:30 +0800)]
powerpc/boot: Change the macro of Boot from SRIO and PCIE master module
Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.
Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Liu Gang [Tue, 7 May 2013 08:30:45 +0000 (16:30 +0800)]
powerpc/doc: Update the README.srio-pcie-boot-corenet
1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet
file when the tabs are set to 8 characters. And the standard for
u-boot should be 8 character tabs! So this issue should be amended.
2. Add a NOTE for the ENV parameters of the Slave.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Tue, 7 May 2013 05:49:55 +0000 (11:19 +0530)]
powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL
e500v2 processor does not support 8K page size TLB entries.
So create new TLB entry only during NAND SPL boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Thu, 20 Jun 2013 19:54:33 +0000 (14:54 -0500)]
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT
All the other constants use lowercase 'x' in "MPC85xx", so we
duplicate that here.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Fabio Estevam [Sun, 21 Apr 2013 16:11:02 +0000 (13:11 -0300)]
powerpc: Use lower case for the core names
Freescale documentation presents the PowerPC core names in lower case, such as
"e300", "e500", "e600", etc.
Change the upper case occurrences into lower case so that the core names
reported in U-boot can match the ones from the documentation.
While at it also fix a checkpatch error:
ERROR: space prohibited before that close parenthesis ')'
#53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81:
+ printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 );
Reported-by: Heinz Wrobel <heinz.wrobel@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
York Sun [Fri, 19 Apr 2013 02:31:01 +0000 (19:31 -0700)]
powerpc/BSC9132: Add IFC bank count
BSC9132 has 3 IFC banks.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Priyanka Jain [Thu, 4 Apr 2013 09:10:32 +0000 (14:40 +0530)]
board/bsc9131rdb: Update default boot environment settings
BSC9131RDB has 1GB DDR.
Out of this, only 880MB is passed on to Linux via bootm_size.
Remaining
-16MB is reserved for PowerPC-DSP shared control area
-128MB is reserved for DSP private area.
Also 256MB, out of this 880MB is required for data communication between
PowerPC and DSP core.
For this bootargs are modified to pass parameter to create 1 hugetlb
page of 256MB via default_hugepagesz, hugepagesz and hugepages
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Priyanka Jain [Thu, 4 Apr 2013 04:01:54 +0000 (09:31 +0530)]
board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Priyanka Jain [Mon, 1 Apr 2013 06:42:45 +0000 (12:12 +0530)]
board/bsc9131rdb: Add targets for Sysclk 100MHz
BSC9131RDB supports Sysclk
-66MHz if jumper J16 is close (default state)
-100MHz if jumper J16 is open
Add targets
-BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz
-BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot at Sysclk 100MHz
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:58:40 +0000 (13:28 +0530)]
board/bsc9132qds:Add NAND boot support using new SPL format
- Add NAND boot target
- defines constants
- Add spl_minimal.c to initialise DDR
- update TLB, LAW entries as per NAND boot
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:58:25 +0000 (13:28 +0530)]
board/bsc9131rdb:Add NAND boot support using new SPL format
- Add NAND boot target
- defines constants
- Add spl_minimal.c to initialise DDR
- update TLB entries as per NAND boot
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:58:12 +0000 (13:28 +0530)]
board/p1010rdb:Add NAND boot support using new SPL format
- defines constants
- Add spl_minimal.c to initialise DDR
- update TLB entries as per NAND boot
- remove nand_spl support for P1010RDB
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:57:59 +0000 (13:27 +0530)]
powerpc/mpc85xx: new SPL support for IFC NAND
Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds
common/Makefile: Avoid compiling unnecssary files
fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
NAND flash and copying into DDR. It also transfer control from NAND SPL
to u-boot image present in DDR.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:57:44 +0000 (13:27 +0530)]
powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399
IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or
no NOR boot, do not compile its workaround.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Mingkai Hu [Fri, 12 Apr 2013 07:56:28 +0000 (15:56 +0800)]
powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_t
To avoid sign extension problem, use explicit casting to cast
the SDRAM size to type phys_size_t, or else, if the SDRAM size
is 2G(0x80000000), it will be extended to 0xffffffff80000000
when phys_size_t is type 'unsigned long long'.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Andy Fleming [Mon, 17 Jun 2013 20:10:28 +0000 (15:10 -0500)]
85xx: Change clock-frequency compatible to 2.0
Accidentally applied an earlier version of the patch, which set
the compatible to "fsl,qoriq-clockgen-2", lacking the final
".0".
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Simon Guinot [Tue, 18 Jun 2013 13:14:50 +0000 (15:14 +0200)]
net2big_v2: initialize LEDs at startup
This patch allows to configure the net2big_v2 LEDs at startup (through
the GPIO extension bus). The front blue LED is enabled and the SATA rear
LEDs are configured to blink in relation with the SATA activity.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Simon Guinot [Tue, 18 Jun 2013 13:14:49 +0000 (15:14 +0200)]
LaCie/common: add support for the CPLD GPIO bus
This patch adds support for the CPLD GPIO bus found on some LaCie boards
(as the 2Big/5Big Network v2 and the 2Big NAS). This parallel GPIO bus
exposes two registers (address and data). Each of this register is made
up of several dedicated GPIOs. An extra GPIO is used to notify the CPLD
that the registers have been updated.
Mostly this bus is used to configure the LEDs on LaCie boards.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Simon Guinot [Tue, 18 Jun 2013 13:14:48 +0000 (15:14 +0200)]
net2big_v2: initialize I2C fan at startup
This patch ensures minimal cooling for the net2big_v2 by automatically
starting the I2C fan (GMT G762) at low speed (2800 RPM).
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Albert ARIBAUD [Wed, 19 Jun 2013 21:58:01 +0000 (23:58 +0200)]
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Jim Lin [Fri, 17 May 2013 09:41:03 +0000 (17:41 +0800)]
NET: Fix system hanging if NET device is not installed
If we try to boot from NET device, NetInitLoop in net.c will be invoked.
If NET device is not installed, eth_get_dev() function will return
eth_current value, which is NULL.
When NetInitLoop is called, "eth_get_dev->enetaddr" will access
restricted memory area and therefore cause hanging.
This issue is found on Tegra30 Cardhu platform after adding
CONFIG_CMD_NET and CONFIG_CMD_DHCP in config header file.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Albert ARIBAUD [Wed, 19 Jun 2013 10:53:59 +0000 (12:53 +0200)]
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Conflicts:
spl/Makefile
Daniel Schwierzeck [Sat, 8 Jun 2013 21:00:15 +0000 (23:00 +0200)]
mtd: nand: fix initialization of BBT options
commit
dfe64e2c89731a3f9950d7acd8681b68df2bae03
Author: Sergey Lapin <slapin@ossfans.org>
Date: Mon Jan 14 03:46:50 2013 +0000
mtd: resync with Linux-3.7.1
changed the initialization of BBT options. Fix drivers
jz4740 and s3c2410 which have not been updated yet and
cause compile errors.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Dan Murphy [Thu, 13 Jun 2013 16:21:26 +0000 (11:21 -0500)]
arm: omap4: panda: Fix checkpatch on panda file
Fix the checkpatch warning on the panda.c file for leading
spaces.
Fix the CHECK warnings on the panda.c file for parenthesis alignment.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Dan Murphy [Thu, 13 Jun 2013 16:21:13 +0000 (11:21 -0500)]
arm: omap4: panda: Add reading of the board revision
Detect if we are running on a panda revision A1-A6,
or an ES panda board. This can be done by reading
the level of GPIOs and checking the processor revisions.
This should result in:
Panda 4430:
GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
GPIO171, GPIO101, GPIO182: 1 0 1 => A6
Panda ES:
GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
Set the board name appropriately for the board revision that
is detected.
Update the findfdt macro to load the a4 device tree binary.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
[trini: %s/CONTROL_PADCONF_CORE/(*ctrl)->control_padconf_core_base/ and
formatting for that]
Signed-off-by: Tom Rini <trini@ti.com>
Dan Murphy [Tue, 11 Jun 2013 16:22:30 +0000 (11:22 -0500)]
arm: dra7xx: Update the EXTRA_ENV_SETTINGS
Update the EXTRA_ENV_SETTING for the dra7xx.
The console needs to be set to ttyO0 and the
findfdt needs to be updated to load the
dra7xx-evm.dtb file.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Dan Murphy [Thu, 6 Jun 2013 21:30:38 +0000 (16:30 -0500)]
arm: omap5_uevm: Correct the console sys prompt for 5432
Correct the console sys prompt to display the correct processor
and the corrent board
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reported-by: Lubomir Popov <lpopov@mm-sol.com>
Reviewed-by: Tom Rini <trini@ti.com>
Dan Murphy [Thu, 6 Jun 2013 18:27:06 +0000 (13:27 -0500)]
arm: omap: Add check for fdtfile in the findfdt macro
In the omap4, omap5 and am335x common files add a check to ensure that the fdtfile is
defined after the findfdt macro has run. If the file is not defined then warn the user that the
dtb file is not defined.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Heiko Schocher [Tue, 4 Jun 2013 09:00:57 +0000 (11:00 +0200)]
arm, am33xx: move uart soft reset code to common place
move uart soft reset code to common place and call
this function from board code, instead of copy and paste
this code for every board.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Tom Rini <trini@ti.com>
[trini: Fix igep0033 build, remove 'regval' on pcm051]
Signed-off-by: Tom Rini <trini@ti.com>
Heiko Schocher [Tue, 4 Jun 2013 09:01:06 +0000 (11:01 +0200)]
arm, am335x: make mpu pll config configurable
upcoming support for siemens boards switches mpu pll clk in board
code. So make this configurable.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Heiko Schocher [Wed, 5 Jun 2013 05:47:56 +0000 (07:47 +0200)]
arm, am33xx: move rtc32k_enable() to common place
move rtc32k_enable() to common place so all am33xx boards can use it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Mike Dunn [Mon, 17 Jun 2013 17:44:55 +0000 (10:44 -0700)]
mtd: nand/docg4: fix driver after Linux resync
Commit
dfe64e2c89731a3f9950d7acd8681b68df2bae03:
mtd: resync with Linux-3.7.1
broke the docg4 driver. Specifically:
- some of the prototypes of the ecc methods changed
- the NAND_NO_AUTOINCR flag was removed
- the ecc.strength element was added.
This patch fixes these. Tested on the docg4 on my palmtre680 board.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Simon Glass [Sun, 16 Jun 2013 14:46:49 +0000 (07:46 -0700)]
image: Use ENOENT instead of ENOMEDIUM for better compatibility
This error may not be defined on some platforms such as MacOS so host
compilation will fail. Use one of the more common errors instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>