Marek Olšák [Mon, 8 Feb 2021 02:10:08 +0000 (21:10 -0500)]
nir: add many passes that lower and optimize 16-bit input/outputs and samplers
Added:
* a pass that renumbers bases of IO intrinsics
* a pass that converts mediump IO to 16 bits, optionally using the new
packed varying slots
* a pass that sets (forces) mediump in IO intrinsics (for testing)
* a pass that remaps VARYING_SLOT_VAR[0..15]_16BIT to VARYING_SLOT_VAR[0..31]
(if some shader stages don't want packed varyings)
* a pass that folds type conversions around texture opcodes into those
opcodes (e.g. tex(f2f32(coord), ..) is changed into tex accepting f16)
* a pass that changes (legalizes) sampler src and dst types based on specified
hw constraints (e.g. derivatives must be the same type as coordinates)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Tue, 9 Feb 2021 15:58:51 +0000 (10:58 -0500)]
nir: add new VARYING_SLOTs and shader info for packed 16-bit varyings
This allows mediump inputs and outputs to be trivially lowered into packed
16-bit varyings where 1 slot is occupied by 2 16-bit vec4s, without any
packing instructions in NIR and without any conflicts with 32-bit varyings.
The only thing that is changed is IO semantics in intrinsics to get packed
16-bit varyings.
This simplifies supporting 16-bit types for drivers that have 32-bit slots
everywhere except the fragment shader where they can do 16-bit interpolation
on either the low or high half of each slot.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Tue, 9 Feb 2021 16:08:11 +0000 (11:08 -0500)]
nir: add src and dest types to all IO loads and stores for mediump
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Mon, 8 Feb 2021 00:57:09 +0000 (19:57 -0500)]
compiler: move TEXTURE_COORD/VERTEX_GENERIC_ATTRIB limits into shader_enums.h
because they are used there.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Jesse Natalie [Mon, 12 Apr 2021 02:15:35 +0000 (19:15 -0700)]
nir_opt_deref: ptr_as_array(deref_cast<T*>(x))[0] isn't the same as x[0] if the cast has alignment
This breaks CLOn12's handling of CL CTS test_basic vector_creation for char3 (at least).
Removing this cast causes us to try to load from a deref with no alignment info.
Fixes:
99bb2a4d ("nir/opt_deref: Don't remove casts with alignment information")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
Jesse Natalie [Mon, 12 Apr 2021 02:13:44 +0000 (19:13 -0700)]
vtn: Support scoped control barriers for OpenCL too
The current handling for SPIR-V memory semantics is very specific to
the wording in the SPIR-V spec, which breaks its handling of OpenCL
(compared to what we had working downstream before merging upstream).
Update/relax the logic here to support CL's barrier(CLK_GLOBAL_MEM_FENCE);
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
Marek Olšák [Mon, 5 Apr 2021 00:19:55 +0000 (20:19 -0400)]
radeonsi: unify internal compute with SSBOs in si_launch_grid_internal_ssbos
just deduplicate the code
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 4 Apr 2021 23:37:01 +0000 (19:37 -0400)]
radeonsi: move binding the internal compute shader into si_launch_grid_internal
instead of doing it in each function
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 4 Apr 2021 21:01:01 +0000 (17:01 -0400)]
radeonsi: enable DCC for MSAA 4x and 8x on gfx9
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 4 Apr 2021 20:58:29 +0000 (16:58 -0400)]
radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9
MSAA 4x and 8x should only clear the first 2 samples because other samples
are uncompressed. The compute shader only clears that subset of DCC.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 20:14:23 +0000 (16:14 -0400)]
radeonsi: fix and enable full DCC with MSAA 2x on gfx9
This enables fast clear with any clear color (not just 0/1) for bpp >= 32.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Mon, 22 Mar 2021 23:43:53 +0000 (19:43 -0400)]
ac,radeonsi: rewrite DCC retiling without the DCC retile map
The retile map is removed and replaced by direct DCC address computations
in the retile shader using the new function ac_nir_dcc_addr_from_coord.
The RADV code is disabled.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Tue, 23 Mar 2021 01:21:30 +0000 (21:21 -0400)]
ac/surface: limit the number of swizzle modes that can have displayable DCC
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 19:52:44 +0000 (15:52 -0400)]
ac/surface: add a test of DccAddrFromCoord prototype outside of addrlib
The test takes over 2 minutes on a 12C/24T CPU with OpenMP.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Mon, 5 Apr 2021 18:01:37 +0000 (14:01 -0400)]
meson: add an optional OpenMP dependency for AMD tests
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 19:51:36 +0000 (15:51 -0400)]
amd/addrlib: expose DCC address equations to drivers
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Wed, 7 Apr 2021 21:20:53 +0000 (17:20 -0400)]
ac/surface/tests: fix a random segfault in the modifier test
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 20:05:40 +0000 (16:05 -0400)]
ac/surface/tests: test Sienna Cichlid and Navy Flounder
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Wed, 31 Mar 2021 11:58:28 +0000 (07:58 -0400)]
ac/surface: only apply the 3D swizzle mode tuning to gfx10+
This fixes an addrlib failure on gfx9.
Fixes:
b43f40166cd "ac/surface: select best swizzle mode for 3D sampler performance"
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Wed, 24 Mar 2021 02:53:00 +0000 (22:53 -0400)]
radeonsi: allow DCC_DECOMPRESS via CB with MSAA textures
The shader-based codepath doesn't support it.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Wed, 31 Mar 2021 10:50:14 +0000 (06:50 -0400)]
radeonsi: try to fix DCC coherency issues with DCC decompression
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Mon, 29 Mar 2021 06:24:39 +0000 (02:24 -0400)]
radeonsi: refine fast clears for small buffers, always use them for large HTILE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 20:57:15 +0000 (16:57 -0400)]
radeonsi: do Z-only or S-only HTILE clear using a compute shader doing RMW
This adds a clear_buffer compute shader that does read-modify-write to
update a subset of bits in HTILE.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 16:17:17 +0000 (12:17 -0400)]
radeonsi: when transitioning to TC-compat HTILE, try to do a proper clear
instead of always clearing to uncompressed.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 16:01:04 +0000 (12:01 -0400)]
radeonsi: enable DCC fast clears for non-zero mipmap levels and 0/1 clear values
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 07:43:44 +0000 (03:43 -0400)]
radeonsi: implement fast Z/S clears using clear_buffer on HTILE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 07:41:59 +0000 (03:41 -0400)]
radeonsi: indent the code for TC-compatibility HTILE transition
So that HTILE clears can be nicely inserted into a new else statement there.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 07:12:21 +0000 (03:12 -0400)]
radeonsi: add si_can_fast_clear_depth/stencil helpers
for later use
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 04:17:44 +0000 (00:17 -0400)]
radeonsi: clean up some mess around htile_stencil_disabled
Set the final value in si_texture_create_object, so that other places
don't have to derive it redundantly.
The only thing to remember is that HTILE stencil can be enabled when
stencil is not present, and it can be disabled when stencil is present
due to various workarounds.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 00:29:33 +0000 (20:29 -0400)]
radeonsi: parallelize Z/S conversion into TC-compatible with fast color clears
It's not really a fast clear, but it's the next logical step towards doing
HTILE clears here.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sat, 20 Mar 2021 23:59:06 +0000 (19:59 -0400)]
radeonsi: implement Z/S fast clear for non-zero mipmap levels
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sat, 20 Mar 2021 00:47:48 +0000 (20:47 -0400)]
radeonsi: implement per-level DCC and CMASK fast clears for gfx10+
Fast clears are only used for level 0. This enables clearing level 0
of CMASK and DCC on gfx10+ when there are multiple mipmap levels.
vi_dcc_clear_level can also clear any level now.
Mipmapped array textures are still cleared slowly.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 23:05:13 +0000 (19:05 -0400)]
radeonsi: allow trivial DCC clears for shared textures with DCC constant encode
This relaxes the existing restriction.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Thu, 18 Mar 2021 02:11:19 +0000 (22:11 -0400)]
radeonsi: restructure DCC disablement into a switch
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Tue, 16 Mar 2021 02:17:39 +0000 (22:17 -0400)]
radeonsi: don't cache FMASK transactions from CB in L2
FMASK is usually pretty large. It's better to leave the cache to shaders.
FMASK stores are still cached, but they can be evicted sooner, which is
the same as other color stores. Only DCC, HTILE, and CMASK are cached.
I haven't benchmarked this, but it seems like the right thing to do.
This only affected APUs.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Nanley Chery [Tue, 17 Sep 2019 23:16:04 +0000 (16:16 -0700)]
iris: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
With a resolution of 1600x1200, I measured FPS increases in:
* glxgears 18.04% +/- 0.65% (n=691)
* Nexuiz 3.58% +/- 0.09% (n=553)
compared to the master branch at commit
3f614c6f7cb97ffc4db2d6c9e222e744871e33d3.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Fri, 20 Sep 2019 01:13:46 +0000 (18:13 -0700)]
iris: Support RC_CCS_CC modifier in plane queries
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Tue, 17 Sep 2019 23:49:55 +0000 (16:49 -0700)]
iris: Support clear color plane imports for RC_CCS_CC
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Tue, 19 Mar 2019 21:11:34 +0000 (14:11 -0700)]
isl: Describe I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
v2. Simplify the diff. (Jason)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Tue, 1 Sep 2020 18:42:48 +0000 (11:42 -0700)]
drm-uapi: Update drm_fourcc.h for new TGL modifier
Pull in the header from drm-next commit
32c3d9b0f51ee1e6bb0160496b97e50b5caca4d0. Among other things, this
brings in the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Mon, 22 Feb 2021 18:54:30 +0000 (10:54 -0800)]
iris: Set BO maps to NULL in bo_free
bo_free is called on external BOs when there are no objects left which
reference them. The function unmaps the address range associated with
any maps which occured. However, if the BO is busy (not idle), it
doesn't mark the pointer to the start address as invalid. This can lead
to a segfault later on.
At the end of bo_free, these BOs are still present in the handle hash
table. If such a BO is reused (i.e., when a DMABUF with the same handle
is reimported) and the driver attempts to get another mapping, the
bufmgr will incorrectly assume that the map pointer is still valid and
reuse it. This leads to a segfault. Set the pointer to NULL to mark it
as invalid.
Enables iris to run and pass the piglit test,
ext_image_dma_buf_import-reimport-bug.
Cc: mesa-stable
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Mike Blumenkrantz [Wed, 7 Apr 2021 13:05:12 +0000 (09:05 -0400)]
aux/trace: do deep dumps of fb state for triggered traces
having the full surface info available here is very useful
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10093>
Mike Blumenkrantz [Wed, 7 Apr 2021 12:53:40 +0000 (08:53 -0400)]
aux/trace: dump current fb state on trigger-mode draw if it hasn't been seen yet
this info is important to have for a given frame, but it requires that the base
structs be copied and stored to the trace context for later use
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10093>
Mike Blumenkrantz [Wed, 7 Apr 2021 12:23:50 +0000 (08:23 -0400)]
aux/trace: enhance trigger mode to dump context states during bind
when dumping a single frame, the creation info for these states hasn't been
dumped yet, so always dump it during bind so it's visible
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10093>
Chia-I Wu [Sat, 10 Apr 2021 05:49:21 +0000 (22:49 -0700)]
venus: check vn_renderer_info::vk_xml_version
When crosvm does not support venus, it still advertises
VIRGL_RENDERER_CAPSET_VENUS but provides no or zeroed capset data.
vk_xml_version will be zero.
It is a good idea to verify vk_xml_version anyway.
v2: print required version suggested by Ryan
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10192>
Eric Anholt [Thu, 1 Apr 2021 23:17:32 +0000 (16:17 -0700)]
ci: bump bare-metal kernel to bring in an a530 stability fix
and while I'm here, drop a workaround for back when we had binary
snapshots of the a530 kernel without compression support.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10047>
James Park [Fri, 19 Mar 2021 08:47:21 +0000 (01:47 -0700)]
amd: Hide drm_fourcc.h on Windows
Declare missing definitions instead.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9708>
James Park [Fri, 4 Dec 2020 04:25:54 +0000 (20:25 -0800)]
amd: Hide amdgpu_drm.h on Windows
Declare missing definitions instead.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9708>
Icecream95 [Thu, 21 Jan 2021 03:23:49 +0000 (16:23 +1300)]
panfrost: Add fast path for graphics work group computation
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10158>
Icecream95 [Tue, 19 Jan 2021 10:40:26 +0000 (23:40 +1300)]
panfrost: Align BO size to 4096 bytes
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10158>
Icecream95 [Mon, 8 Feb 2021 09:50:27 +0000 (22:50 +1300)]
panfrost: Only add resource checksum BOs to the batch once
Previously panfrost_batch_add_bo was called MAX_MIP_LEVELS times on
the same batch.
Fixes:
cbf68b21fb2 ("panfrost: Move checksum_bo to panfrost_resource")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10158>
James Park [Tue, 23 Feb 2021 09:55:28 +0000 (01:55 -0800)]
ac/rgp: BSD elf library compatibility
Allow compilation on Windows using modified BSD elf library.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9210>
Thong Thai [Fri, 9 Apr 2021 14:26:59 +0000 (10:26 -0400)]
radeon: Add cropping to encoded H.265 when padding is used
Because the VCN encoder needs the surface to be memory aligned, the
resolution of the image passed to the encoder might be larger and have
extra padding added - this change crops the resulting output to
compensate for the extra padding that might have been added.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4559
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10137>
Vasily Khoruzhick [Thu, 8 Apr 2021 06:32:46 +0000 (23:32 -0700)]
lima: limit number of draws per job
Otherwise we may hit tile heap size limit if an app issues too many
draws per job.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10121>
Vasily Khoruzhick [Mon, 12 Apr 2021 15:10:29 +0000 (08:10 -0700)]
lima: use passed surface to get mipmap level for reload, not cbuf
lima_pack_reload_plbu_cmd() can be used for either cbuf or zsbuf, so
use passed surface other using cbuf unconditionally.
Fixes:
b8c31ac06d35 ("lima: fix glCopyTexSubImage2D")
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10121>
Erico Nunes [Sun, 28 Mar 2021 21:42:43 +0000 (23:42 +0200)]
lima: increase epsilon for depthrange near == far
When the application sets depthrange near == far, lima inserts an
'epsilon' difference of decreasing 'near' by 1 unit, to prevent
application bugs.
For some specific values of depthrange this does not seem to be
sufficient, presumably due to precision limitations.
Increase the difference by also incrementing the 'far' distance in
this case, to further avoid bugs.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9933>
Marek Olšák [Mon, 12 Apr 2021 05:54:07 +0000 (01:54 -0400)]
ac/surface: use named "color and "zs" structures in unions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Mon, 12 Apr 2021 05:48:02 +0000 (01:48 -0400)]
ac/surface: unify htile_* and dcc_* fields as meta_* fields
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Mon, 12 Apr 2021 04:54:37 +0000 (00:54 -0400)]
ac/surface: unify htile_levels and dcc_levels as meta_levels
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 21:08:23 +0000 (17:08 -0400)]
ac/surface: pack radeon_surf better
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 20:12:43 +0000 (16:12 -0400)]
ac/surface: overlap color and Z/S fields using a union in gfx9_surf_layout
to save space
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 18:59:54 +0000 (14:59 -0400)]
ac/surface: pack alignments by storing log2 in radeon_surf
Only one bit is set in alignments, so store the bit offset (log2) and
change the type from uint32_t to uint8_t.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 18:31:02 +0000 (14:31 -0400)]
ac/surface: pack radeon_surf::num_htile_levels better
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 18:11:26 +0000 (14:11 -0400)]
ac/surface: pack gfx9_surf_layout:resource_type better to save 8 bytes
Yes, this saves 8 bytes. See pahole for yourself.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 18:04:16 +0000 (14:04 -0400)]
ac/surface: pack gfx9_surf_meta_flags better
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 18:00:57 +0000 (14:00 -0400)]
ac/surface: inline and reorder gfx9_surf_flags for better packing
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 17:33:38 +0000 (13:33 -0400)]
ac/surface: change legacy_surf_level::offset to 32-bit offset_256B shifted by 8
Images are always aligned to 256B (enforced by register and descriptor
fields) and limited to 40-bit addresses. This saves some space.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 16:54:09 +0000 (12:54 -0400)]
ac/surface: overlap color and Z/S fields using a union in legacy_surf_layout
to save space
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 16:37:42 +0000 (12:37 -0400)]
ac/surface: split dcc level info from surface_info to save space
stencil level info doesn't have DCC
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Rhys Perry [Mon, 12 Apr 2021 14:36:59 +0000 (15:36 +0100)]
nir/loop_unroll: fix is_indirect_load() with load_global
load_global only has one source.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes:
dfe429eb414 ("nir/loop_unroll: unroll more aggressively if it can improve load scheduling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10186>
Jesse Natalie [Sat, 10 Apr 2021 19:32:13 +0000 (12:32 -0700)]
CI: Enable -werror for Windows
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10157>
Jesse Natalie [Sat, 10 Apr 2021 19:24:05 +0000 (12:24 -0700)]
driconf: Remove default values from string driconf entries
None of the call sites pass a string here, which produces warnings
for MSVC, for not passing an argument to a macro which requires it.
Looks like GCC/clang stringize an unpassed argument to ""
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10157>
Jesse Natalie [Sat, 10 Apr 2021 19:14:19 +0000 (12:14 -0700)]
meson: For MSVC, suppress warnings generated by useless delayloads
LLVM's tools delayload some OS DLLs to improve process startup times,
but they put the delayload in the exported linker args that Meson picks
up and then applies to all libraries that link against LLVM. Since our
binaries don't link against the OS libs that are being delayloaded, that
generates a "useless delayload" warning.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10157>
Jesse Natalie [Mon, 12 Apr 2021 15:38:57 +0000 (08:38 -0700)]
microsoft/clc: Update unit test to always use COMMON state for buffers
New Windows versions have new debug validation warning that for resources that
aren't actually UPLOAD/READBACK (which these aren't, thanks to the
GetCustomHeapProperties call), initial state that's not COMMON doesn't actually
do anything, which causes these tests to all fail because they verify that
they don't produce debug layer messages.
Reviewed-By: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10190>
Rhys Perry [Mon, 13 Jan 2020 14:32:18 +0000 (14:32 +0000)]
nir/lcssa: fix nondeterminism in predecessor iteration
set_foreach()'s order on a list of nir_block * isn't deterministic, so we
need to sort the predecessor list.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3364>
Rhys Perry [Thu, 8 Apr 2021 15:26:38 +0000 (16:26 +0100)]
nir: add nir_block_get_predecessors_sorted() helper
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3364>
Jason Ekstrand [Mon, 12 Apr 2021 15:09:02 +0000 (10:09 -0500)]
anv: Make memory type and queue family pointers const
These point to data inside the instance so no one should be modifying
them.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10184>
Leo Liu [Wed, 20 Jan 2021 00:01:00 +0000 (19:01 -0500)]
radeonsi: replace the hard coded video decode and encode caps
For the caps of max_width, max_height and max_level with those
that are available via querying the kernel.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10095>
Leo Liu [Tue, 23 Feb 2021 16:40:13 +0000 (11:40 -0500)]
ac: add function for querying video capabilities
It will be used to query caps of decode and encode
for hardware AMDGPU supports
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10095>
Leo Liu [Sat, 3 Apr 2021 19:07:42 +0000 (15:07 -0400)]
include/drm-uapi: bump AMDGPU headers
From drm-next:
commit
2cbcb78c9ee5520c8d836c7ff57d1b60ebe8e9b7
Merge:
06debd6e1b28 8c44390d8872
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Fri Mar 26 15:52:01 2021 +0100
Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.13-2021-03-23:
amdgpu:
...
UAPI:
- amdgpu: Add a new INFO ioctl interface to query video capabilities
rather than hardcoding them in userspace. This allows us to provide
fine grained asic capabilities (e.g., if a particular part is
bandwidth limited, we can limit the capabilities). Proposed userspace:
https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps
https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps
...
Danvet: A bunch of conflicts all over, but it seems to compile ... I
did put the call to dc_allow_idle_optimizations() on a single line
since it looked a bit too jarring to be left alone.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210324040147.1990338-1-alexander.deucher@amd.com
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10095>
Leo Liu [Sun, 11 Apr 2021 15:02:19 +0000 (11:02 -0400)]
ci: Fix meson-i386 build failed after libdrm bump version
libpciaccess-dev:$arch from STABLE_EPHEMERAL down to the main list of packages
in .gitlab-ci/container/cross_build.sh, and bumping the arm_build, i386_build,
ppc64el_build & s390x_build tags again.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Suggested-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
----
.gitlab-ci.yml | 8 ++++----
.gitlab-ci/container/cross_build.sh | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10095>
Leo Liu [Tue, 19 Jan 2021 22:29:33 +0000 (17:29 -0500)]
meson: bump drm amdgpu version to 2.4.105
To include the INFO ioctl query for video caps
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10095>
Ilia Mirkin [Sat, 10 Apr 2021 21:38:23 +0000 (17:38 -0400)]
nv50: enable ARB_framebuffer_no_attachments
This is a required part of ES3.1 and fairly trivial to enable. In
practice it's almost entirely useless since the only information one
would be able to obtain are queries.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10162>
Ilia Mirkin [Sat, 3 Apr 2021 05:13:16 +0000 (01:13 -0400)]
nv50/ir: fake SV_THREAD_KILL support
If we say that there are no helper invocations, it's suboptimal but
allows ES 3.1 to chug along.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10162>
Ilia Mirkin [Sat, 3 Apr 2021 05:10:14 +0000 (01:10 -0400)]
nv50: emulate indirect draws
This is helpful for allowing ES 3.1 to work, as this is required.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10162>
Ilia Mirkin [Sat, 3 Apr 2021 05:09:21 +0000 (01:09 -0400)]
nv50/ir: fix texture size for msaa textures
These are scaled up in the descriptor, which doesn't really know about
their MSAA-ness. So we have to shift them back down.
Cc: mesa-stable
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10162>
Rhys Perry [Wed, 7 Apr 2021 18:18:09 +0000 (19:18 +0100)]
radv: don't use fp16 for 8-bit division lowering before GFX9
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10081>
Rhys Perry [Wed, 7 Apr 2021 17:14:36 +0000 (18:14 +0100)]
aco: fix 16-bit f2{u8,i8} on GFX6/7
Not really tested.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10081>
Rhys Perry [Wed, 7 Apr 2021 17:06:46 +0000 (18:06 +0100)]
aco: fix 16-bit u2f32
This shouldn't sign-extend.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10081>
Rhys Perry [Wed, 7 Apr 2021 18:45:57 +0000 (19:45 +0100)]
nir/lower_idiv: make lowered divisions exact
I can't imagine any reasonable optimization which could break this, but
since it's lowered from an integer instructions, we shouldn't do anything
which could change the result.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10081>
Rhys Perry [Wed, 7 Apr 2021 18:17:46 +0000 (19:17 +0100)]
nir/lower_idiv: add options to use fp32 for 8-bit division lowering
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10081>
Rhys Perry [Wed, 7 Apr 2021 18:58:19 +0000 (19:58 +0100)]
radv: remove second nir_lower_idiv
nir_lower_idiv now lowers 8/16-bit divisions.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10081>
Alyssa Rosenzweig [Fri, 9 Apr 2021 23:18:48 +0000 (19:18 -0400)]
panfrost: Enable AFBC buffer sharing
This was hidden originally to workaround a bug in the RK3399 display
driver. The patch resolving this issue has been merged in the upstream
kernel, and in fact...
1. The issue was visible on 21.0 even with this workaround under certain
configurations (sway with an external monitor).
2. Even on buggy kernels, due to other platform details this is an
obscure bug to hit (not aware of any ways to trigger it OOTB with
current userspaces other than sway with an external monitor)
So why bother? Let's just delete the hack and let AFBC be used freely.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10148>
Alyssa Rosenzweig [Fri, 9 Apr 2021 23:14:14 +0000 (19:14 -0400)]
panfrost: Fix AFBC body_size for shared resources
Accidental read-before-write due to incorrect statement ordering. I love
SSA as much as anyone, but not everything is a parallel copy.
Fixes faults in glamor in 21.0 when using GIMP on v5.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Fixes:
e8b997e1758 ("panfrost: Add AFBC slice.body_size and slice.{row,surface}_stride fields")
Closes: #4389
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10148>
Mike Blumenkrantz [Fri, 9 Apr 2021 20:39:57 +0000 (16:39 -0400)]
zink: disable mutable formats for zs formats and scanout images
swapchain images are never going to be used as texture views, and zs formats
aren't compatible with any other formats
this enables implicit modifiers in some cases, and more work can be done in the future
to eliminate mutable format usage to further improve performance
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10180>
Mike Blumenkrantz [Fri, 9 Apr 2021 19:12:46 +0000 (15:12 -0400)]
zink: flag anv for mesa image create wsi
the image creation wsi is used, but the memory creation wsi isn't
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10180>
Mike Blumenkrantz [Fri, 9 Apr 2021 14:23:48 +0000 (10:23 -0400)]
zink: create separate linear tiling image for scanout
rendering onto a linear-tiled image is unbelievably slow if any sort of
blending is enabled, so instead always render to optimal tiling and then
copy to linear for scanout
this doubles performance for now and can be deleted in its entirety along
with the rest of the related hacks once real wsi support is implemented
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10180>
Juan A. Suarez Romero [Fri, 9 Apr 2021 08:59:14 +0000 (10:59 +0200)]
broadcom/compiler: use signed pointers for packed condition
`qpu.raddr_b` is an unsigned int, so it is always positive, even after
casting to signed int.
Fixes CID#1438117 "Operands don't affect result
(CONSTANT_EXPRESSION_RESULT)":
"result_independent_of_operands: (int)inst->qpu.raddr_b >= -16 is
always true regardless of the values of its operands. This occurs as
the logical first operand of "&&".
v2:
- Use signed pointers (Iago)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10131>
Danylo Piliaiev [Fri, 9 Apr 2021 15:02:26 +0000 (18:02 +0300)]
turnip: support copying both aspects of D32_SFLOAT_S8_UINT
We cannot copy both aspects at the same time, so copy them one by one.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10140>
Jesse Natalie [Sun, 11 Apr 2021 21:09:58 +0000 (14:09 -0700)]
vtn: Add a cap for CL drivers to support read-write images
This is a required CL2.0, optional CL3.0 feature
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10181>