Jagan Teki [Tue, 26 May 2020 03:34:29 +0000 (11:34 +0800)]
usb: dwc3: Enable AutoRetry feature in the controller
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).
Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with Retry=1 and Nump != 0.
Doing so will give controller a chance to recover from transient error
conditions.
Reference from below Linux commit,
commit <
b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature
in the controller")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 26 May 2020 03:33:48 +0000 (11:33 +0800)]
usb: dwc3: Add disable u2mac linestate check quirk
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.
When use this quirk, the controller implements a fixed 40-bit
TxEndDelay after the packet is given on UTMI and ignores the
linestate during the transmit of a token (during token-to-token
and token-to-data IPGAP).
On some rockchip platforms (e.g. rk3399), it requires to disable
the u2mac linestate check to decrease the SSPLIT token to SETUP
token inter-packet delay from 566ns to 466ns, and fix the issue
that FS/LS devices not recognized if inserted through USB 3.0 HUB.
Reference from below Linux commit,
commit <
65db7a0c9816> ("usb: dwc3: add disable u2mac linestate
check quirk")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Frank Wang [Tue, 26 May 2020 03:33:47 +0000 (11:33 +0800)]
usb: dwc3: add dis_u2_freeclk_exists_quirk
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.
Refer to commit
27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk")
in Linux Rockchip Kernel.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Frank Wang [Tue, 26 May 2020 03:33:46 +0000 (11:33 +0800)]
usb: dwc3: add dis_enblslpm_quirk
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit
ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Tue, 26 May 2020 03:33:45 +0000 (11:33 +0800)]
phy: rockchip: Add Rockchip USB TypeC PHY driver
Add USB TYPEC PHY driver for rockchip platform.
Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 26 May 2020 03:33:44 +0000 (11:33 +0800)]
phy: rockchip: Add Rockchip USB2PHY driver
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Frank Wang [Tue, 26 May 2020 03:32:08 +0000 (11:32 +0800)]
arm: mach-rockchip: bind sub-nodes for rk3399_syscon
There are some sub-nodes under the grf DT, so add bind callback
function in rk3399 syscon driver to scan them recursively.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 26 May 2020 03:32:07 +0000 (11:32 +0800)]
clk: rk3399: Enable/Disable TCPHY clocks
Enable/Disable TCPHY clock for rk3399 platform.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 26 May 2020 03:32:06 +0000 (11:32 +0800)]
clk: rk3399: Set empty for TCPHY assigned-clocks
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
So, mark them as empty in clock otherwise device probe on
those typec phy driver would fail.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 26 May 2020 03:32:05 +0000 (11:32 +0800)]
clk: rk3399: Enable/Disable the USB2PHY clk
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Walter Lozano [Fri, 22 May 2020 14:14:57 +0000 (11:14 -0300)]
doc: rockchip: Remove list of supported boards
As documentation is being moved to doc/boards/rockchip create a warning
message and remove the redundant list of supported boards.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Walter Lozano [Fri, 22 May 2020 14:14:56 +0000 (11:14 -0300)]
doc: board: rockchip: Add missing supported boards
Update the list of supported boards with the information available
on doc/README.rockchip.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Walter Lozano [Fri, 22 May 2020 14:14:55 +0000 (11:14 -0300)]
doc: board: rockchip: Improve supported board list format
As an additional step to move documentation to doc/boards/rockchip
improve format of the supported board list to make it more readable.
Additionally, add the configuration files used to build them based on
doc/README.rockchip.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Marcin Juszkiewicz [Mon, 25 May 2020 14:44:49 +0000 (16:44 +0200)]
rockchip: enable USB OHCI host for RockPro64
U-Boot has video output enabled so time to get keyboard working.
=> usb reset;usb tree
resetting USB...
Bus usb@
fe380000: USB EHCI 1.00
Bus usb@
fe3a0000: USB OHCI 1.0
Bus usb@
fe3c0000: USB EHCI 1.00
Bus usb@
fe3e0000: USB OHCI 1.0
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus usb@
fe380000 for devices... 1 USB Device(s) found
scanning bus usb@
fe3a0000 for devices... 1 USB Device(s) found
scanning bus usb@
fe3c0000 for devices... 1 USB Device(s) found
scanning bus usb@
fe3e0000 for devices... 3 USB Device(s) found
scanning bus dwc3 for devices... cannot reset port 1!?
2 USB Device(s) found
scanning usb for storage devices... 2 Storage Device(s) found
USB device tree:
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (12 Mb/s, 0mA)
U-Boot Root Hub
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (12 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Hub (12 Mb/s, 100mA)
| ALCOR Generic USB Hub
|
+-3 Mass Storage (12 Mb/s, 200mA)
Kingston DT 101 G2
001478544887BB3157380157
1 Hub (5 Gb/s, 0mA)
| U-Boot XHCI Host Controller
|
+-2 Mass Storage (5 Gb/s, 76mA)
ADATA ADATA USB Flash Drive
1520405012240002
Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Mark Kettenis [Sun, 24 May 2020 21:10:34 +0000 (23:10 +0200)]
rk3399: Enable NVMe distro bootcmd
Include NVME in the list of boot targets if CONFIG_NVME is enabled.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Mark Kettenis [Sun, 24 May 2020 20:32:51 +0000 (22:32 +0200)]
pci: Make Rockchip PCIe voltage regulators optional
The vpcie*-supply properties are optional and these are absent on
boards like the ROCKPro64 and Firefly RK3399 where the voltage is
supplied by always-on regulators that are already enabled upon
boot. Make these regulators optional and properly check their
presence before attempting to enable them.
Makes PCIe work on un U-Boot on the boards mentioned above.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Jagan Teki [Sun, 24 May 2020 17:32:13 +0000 (23:02 +0530)]
doc: rockchip: Document eMMC program steps
Document eMMC partition creation and program steps for
rockchip platforms.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sun, 24 May 2020 17:32:12 +0000 (23:02 +0530)]
nanopc-t4: Enable USB Gadget
Enable DWC3 core, gadget for nanopc-t4 board.
This would help to use fastboot by default.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sun, 24 May 2020 17:32:11 +0000 (23:02 +0530)]
arm64: dts: rk3399-nanopi4: Add u-boot,spl-boot-order
Add u-boot,spl-boot-order as sdhci and sdmmc for booting
from eMMC and SD card.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sun, 24 May 2020 16:43:15 +0000 (22:13 +0530)]
clk: rk3399: Fix eMMC get_clk reg offset
Actual eMMC get_clk register is clksel_con22 instead of
clksel_con21.
Fix it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sun, 24 May 2020 14:56:18 +0000 (20:26 +0530)]
rockchip: Fix spl mmc boot device ofpath
Linux v5.7-rc1 dts(i) sync has changed the sdmmc node from
dwmmc@
fe320000 to mmc@
fe320000 and this ofpath is being
used in rockchip spl bootdevice code.
So, update the ofpath with a new node name and prefix "same-as-spl"
to missing u-boot,spl-boot-order.
Bug log:
U-Boot SPL 2020.07-rc2-00256-g9c5fef5774 (May 24 2020 - 20:20:43 +0530)
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices
Fixes:
167efc2c7a46 ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux"
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Wed, 27 May 2020 14:56:25 +0000 (10:56 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix SPI boot on ds414 (Ezra)
- Fix PHY mode definition on armada-3720-uDPU (Jakov)
- Convert CRS305-1G-4S to generic version (Luka)
Tom Rini [Wed, 27 May 2020 14:55:55 +0000 (10:55 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Use device tree for FSP-M and FSP-S configuration on Intel Apollo Lake
- Add SMBIOS cbmem entry parsing for coreboot
- Various clean-ups to CBFS implementation
Simon Glass [Sun, 24 May 2020 23:38:24 +0000 (17:38 -0600)]
cbfs: Don't require the CBFS size with cbfs_init_mem()
The size is not actually used since it is present in the header. Drop this
parameter. Also tidy up error handling while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:23 +0000 (17:38 -0600)]
cbfs: Allow reading a file from a CBFS given its base addr
Currently we support reading a file from CBFS given the address of the end
of the ROM. Sometimes we only know the start of the CBFS. Add a function
to find a file given that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:22 +0000 (17:38 -0600)]
cbfs: Change file_cbfs_find_uncached() to return an error
This function currently returns a node pointer so there is no way to know
the error code. Also it uses data in BSS which seems unnecessary since the
caller might prefer to use a local variable.
Update the function and split its body out into a separate function so we
can use it later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:21 +0000 (17:38 -0600)]
cbfs: Return the error code from file_cbfs_init()
We may as well return the error code and use it directly in the command
code. CBFS still uses its own error enum which we may be able to remove,
but leave it for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:20 +0000 (17:38 -0600)]
cbfs: Record the start address in cbfs_priv
The start address of the CBFS is used when scanning for files. It makes
sense to put this in our cbfs_priv struct and calculate it when we read
the header.
Update the code accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:19 +0000 (17:38 -0600)]
cbfs: Use void * for the position pointers
It doesn't make sense to use u8 * as the pointer type for accessing the
CBFS since we do not access it as bytes, but via structures. Change it to
void *, which allows us to avoid a cast.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:18 +0000 (17:38 -0600)]
cbfs: Unify the two header loaders
These two functions have mostly the same code. Pull this out into a common
function.
Also make this function zero the private data so that callers don't have
to do it. Finally, update cbfs_load_header_ptr() to take the base of the
ROM as its parameter, which makes more sense than passing the address of
the header within the ROM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:17 +0000 (17:38 -0600)]
cbfs: Adjust cbfs_load_header_ptr() to use cbfs_priv
This function is strange at the moment in that it takes a header pointer
but then accesses the cbfs_s global. Currently clients have their own priv
pointer, so update the function to take that as a parameter instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:16 +0000 (17:38 -0600)]
cbfs: Adjust file_cbfs_load_header() to use cbfs_priv
This function is strange at the moment in that it takes a header pointer
but then accesses the cbfs_s global. Currently clients have their own priv
pointer, so update the function to take that as a parameter instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:15 +0000 (17:38 -0600)]
cbfs: Adjust return value of file_cbfs_next_file()
At present this uses a true return to indicate it found a file. Adjust it
to use 0 for this, so it is consistent with other functions.
Update its callers accordingly and add a check for malloc() failure in
file_cbfs_fill_cache().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:14 +0000 (17:38 -0600)]
cbfs: Use bool type for whether initialised
At present this uses an int type. U-Boot now supports bool so use this
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:13 +0000 (17:38 -0600)]
cbfs: Use ulong consistently
U-Boot uses ulong for addresses but there are a few places in this driver
that don't use it. Convert this driver over to follow this convention
fully.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 24 May 2020 23:38:12 +0000 (17:38 -0600)]
cbfs: Rename the result variable
At present the result variable in the cbfs_priv is called 'result' as is
the local variable in a few functions. Change the latter to 'ret' which is
more common in U-Boot and avoids confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Christian Gmeiner [Tue, 19 May 2020 09:01:59 +0000 (11:01 +0200)]
cbfs: drop file_cbfs_result declaration
It is not definded anywhere.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.gpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Christian Gmeiner [Thu, 14 May 2020 13:16:22 +0000 (15:16 +0200)]
x86: coreboot: add SMBIOS cbmem entry parsing
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bernhard Messerklinger [Mon, 18 May 2020 10:33:35 +0000 (12:33 +0200)]
x86: apl: Use devicetree for FSP-S configuration
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bernhard Messerklinger [Mon, 18 May 2020 10:33:34 +0000 (12:33 +0200)]
x86: apl: Use devicetree for FSP-M configuration
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
[sjg: Fix a build error for coral]
Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: Add __maybe_unused to fsp_update_config_from_dtb()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bernhard Messerklinger [Mon, 18 May 2020 10:33:33 +0000 (12:33 +0200)]
x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 7 May 2020 14:12:52 +0000 (08:12 -0600)]
x86: mtrr: Drop the mask display when changing an mtrr
We don't need to print this information since it is shown when the MTRRs
are displayed. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Luka Kovacic [Tue, 26 May 2020 18:17:50 +0000 (20:17 +0200)]
arm: mvebu: Convert CRS305-1G-4S board to CRS3xx-98DX3236
Convert the CRS305-1G-4S board to CRS3xx-98DX3236 to enable easier
implementation of new CRS3xx series boards, based on Marvell Prestera
98DX3236.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Jakov Petrina [Tue, 12 May 2020 10:02:47 +0000 (12:02 +0200)]
arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500
Commit
f49ac7e1c4 switched the default PHY speed to 3.125Gbit to resolve
issues with SFP modules. However, U-Boot does not have a "2500base-x"
phy-mode.
Resolve this by using "sgmii-2500" instead.
Signed-off-by: Jakov Petrina <jakov.petrina@sartura.hr>
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Ezra Buehler [Sat, 9 May 2020 20:05:39 +0000 (22:05 +0200)]
arm: mvebu: ds414: define CONFIG_SYS_U_BOOT_OFFS
Without CONFIG_SYS_U_BOOT_OFFS set to CONFIG_SYS_SPI_U_BOOT_OFFS, U-Boot
will be located at address 0x16000. But, SPL will try to load the
payload from 0x24000 causing the boot to hang.
Signed-off-by: Ezra Buehler <ezra@easyb.ch>
Reviewed-by: Stefan Roese <sr@denx.de>
Ezra Buehler [Sat, 9 May 2020 20:05:38 +0000 (22:05 +0200)]
arm: mvebu: ds414: add u-boot,dm-pre-reloc to spi0
Without this U-Boot-specific property, booting on the Synology DS414
(or DS214+) fails in SPL. The spi0 DT node is not scanned, as a result
the SPI flash cannot be found.
Signed-off-by: Ezra Buehler <ezra@easyb.ch>
Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Tue, 26 May 2020 19:27:04 +0000 (15:27 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- sifive: fix palmer's email address.
- Move all SMP related SBI calls to SBI_v01.
Tom Rini [Tue, 26 May 2020 12:32:25 +0000 (08:32 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Pragnesh Patel [Thu, 30 Apr 2020 14:42:03 +0000 (20:12 +0530)]
sifive: fix palmer's email address
Fix Palmer's email address
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Atish Patra [Tue, 21 Apr 2020 21:51:57 +0000 (14:51 -0700)]
riscv: Move all SMP related SBI calls to SBI_v01
SMP support for S-mode U-Boot is enabled only if SBI_V01 is enabled.
There is no point in supporting SMP related (IPI and fences) SBI calls
when SBI_V02 is enabled.
Modify all the SMP related SBI calls to be defined only for SBI_V01.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Tue, 26 May 2020 00:34:01 +0000 (20:34 -0400)]
Prepare v2020.07-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 25 May 2020 18:09:42 +0000 (14:09 -0400)]
Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Enable DM_ETH on omap3_logic board
- Enable Caches in SPL for K3 platforms
- Enable backup boot mode support for J721E
- Update the DDR timings for AM654 EVM
- Add automated tests for RX-51
Tom Rini [Mon, 25 May 2020 15:56:57 +0000 (11:56 -0400)]
Merge branch '2020-05-25-misc-fixes'
- A few minor Kconfig migrations / corrections
- DFU doc fixes/improvements
- Bugfix for ARMv8, env userspace building, more NULL checks in generic
PHY code
Michael Walle [Fri, 22 May 2020 12:07:38 +0000 (14:07 +0200)]
sandbox: move compression option to Kconfig
CONFIG_BZIP2 and CONFIG_GZIP_COMPRESSED are Kconfig options. Select them
by CONFIG_SANDBOX instead of setting them in configs/sandbox.h.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michael Walle [Fri, 22 May 2020 12:07:37 +0000 (14:07 +0200)]
cmd: zip: fix implicit declaration warning
Fix the following warning:
cmd/zip.c: In function ‘do_zip’:
cmd/zip.c:30:6: warning: implicit declaration of function ‘gzip’; did you mean ‘do_zip’? [-Wimplicit-function-declaration]
if (gzip((void *) dst, &dst_len, (void *) src, src_len) != 0)
^~~~
do_zip
Include gzip.h header which declares the gzip() function.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michael Walle [Fri, 22 May 2020 12:07:36 +0000 (14:07 +0200)]
cmd: zip: automatically pull in gzip()
Move the CONFIG_GZIP_COMPRESSED from a config.h macro to a Kconfig menu
item. It is not selectable by a user because there is no reason to do
so. Instead it will be automatically selected by the stuff which uses
gzip(), like the zip command.
Remove it from the config_whitelist.txt. Also remove
CONFIG_GZIP_COMPRESS_DEF_SZ as this was never used on any board. The
default seems to be sane, otherwise it should be added as a Kconfig
option.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michael Walle [Fri, 22 May 2020 12:07:35 +0000 (14:07 +0200)]
cmd: unzip: automatically select CONFIG_GZIP
unzip calls gzwrite() which is provided in lib/gunzip.c. Make sure it is
automatically pulled in if the user selects CMD_UNZIP.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Heinrich Schuchardt <xypron.glkp@gmx.de>
Marek Vasut [Thu, 21 May 2020 23:10:14 +0000 (01:10 +0200)]
env: Convert ENV_ACCESS_IGNORE_FORCE to Kconfig
Convert ENV_ACCESS_IGNORE_FORCE to Kconfig, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Romain Naour [Thu, 21 May 2020 21:22:06 +0000 (23:22 +0200)]
tools/env/fw_env.h: remove env.h
As reported by Nicolas Carrier on the Buildroot mailing list [1],
there is a new build issue while building a program which interacts with
the u-boot environment. This program uses the headers of the ubootenv
library provided by uboot-tools.
This is a recent change from uboot [2] adding "#include <env.h>" to
fw_env.h. Adding env.h require a board configuration to build since
it also include compiler.h (and others uboot internal includes).
env.h include seems not needed since env_set() is not used in fw_env tool.
Nicolas removed env.h from fw_env tool and fixed it's build issue.
This problem is present since uboot v2019.10.
[1] http://lists.busybox.net/pipermail/buildroot/2020-April/280307.html
[2] https://gitlab.denx.de/u-boot/u-boot/-/commit/
9fb625ce05539fe6876a59ce1dcadb76b33c6f6e
Reported-by: Nicolas Carrier <nicolas.carrier@orolia.com>
Signed-off-by: Romain Naour <romain.naour@gmail.com>
Tom Rini [Thu, 21 May 2020 20:26:03 +0000 (16:26 -0400)]
Convert CONFIG_CMD_MMC to Kconfig
This converts the following to Kconfig:
CONFIG_CMD_MMC
Signed-off-by: Tom Rini <trini@konsulko.com>
Vignesh Raghavendra [Wed, 20 May 2020 17:05:41 +0000 (22:35 +0530)]
phy: Fix possible NULL pointer deference
It is possible that users of generic_phy_*() APIs may pass a valid
struct phy pointer but phy->dev can be NULL, leading to NULL pointer
deference in phy_dev_ops().
So call generic_phy_valid() to verify that phy and phy->dev are both
valid.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Heinrich Schuchardt [Sun, 24 May 2020 10:02:14 +0000 (12:02 +0200)]
MAINTAINERS: add dfu.h and dfu.rst to DFU
include/dfu.h and doc/api/dfu.rst belong to the device firmware update
sub-system. So let's add them to DFU in MAINTAINERS.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Heinrich Schuchardt [Sat, 23 May 2020 12:24:40 +0000 (14:24 +0200)]
doc: dfu: describe more DFU function
Add some of the missing DFU function descriptions.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Heinrich Schuchardt [Sat, 23 May 2020 11:48:07 +0000 (13:48 +0200)]
doc: dfu: fix typos in README.dfu
Fix some typos.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Heinrich Schuchardt [Sat, 23 May 2020 10:01:08 +0000 (12:01 +0200)]
doc: dfu: add DFU to HTML documentation
Add the device firmware update functions to the generated HTML
documentation.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Heinrich Schuchardt [Sat, 23 May 2020 09:36:49 +0000 (11:36 +0200)]
doc: dfu: describe eMMC partition number parameter
In dfu_alt_info for eMMC the eMMC partition number can be specified.
The separator in dfu_alt_info is a semicolon not a comma.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Heinrich Schuchardt [Wed, 20 May 2020 21:24:52 +0000 (23:24 +0200)]
MAINTAINERS: add doc/driver-model/ to DRIVER MODEL
The documentation should rest with the same maintainer as the code.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Peng Fan [Mon, 11 May 2020 08:41:07 +0000 (16:41 +0800)]
armv8: cache_v8: fix mmu_set_region_dcache_behaviour
The enum dcache_optoion contains a shift left 2 bits in the armv8 case
already. The PMD_ATTRINDX(option) macro will perform a left shift of 2
bits. Perform a right shift so that in the end we get the correct
value.
[trini: Reword the commit message]
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Sat, 23 May 2020 02:58:50 +0000 (22:58 -0400)]
Merge git://git.denx.de/u-boot-usb
- DM support for OMAP
- DWC3 fix
- Typo fix in eth/r8152
Tom Rini [Sat, 23 May 2020 02:58:16 +0000 (22:58 -0400)]
Merge branch 'net' of git://git.denx.de/u-boot-socfpga
- ks8851 cleanups and DM migration
Marek Vasut [Wed, 25 Mar 2020 18:08:59 +0000 (19:08 +0100)]
net: ks8851: Add Kconfig entries
Convert CONFIG_KS8851_MLL and CONFIG_KS8851_MLL_BASEADDR to Kconfig
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 17:00:35 +0000 (18:00 +0100)]
net: ks8851: Add DM support
Add support for U-Boot DM and DT probing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 17:47:10 +0000 (18:47 +0100)]
net: ks8851: Receive one packet per recv call
Instead of reading out the entire FIFO and possibly overwriting U-Boot
memory, read out one packet per recv call, pass it to U-Boot network
stack, and repeat. It is however necessary to cache RXFC value, because
reading that one out clears it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 16:54:45 +0000 (17:54 +0100)]
net: ks8851: Split non-DM specific bits from common code
Split network handling functions into non-DM specific parts and
common code in preparation for conversion to DM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 16:35:00 +0000 (17:35 +0100)]
net: ks8851: Pass around driver private data
Introduce a private data structure for this driver with embedded
struct eth_device and pass it around. This prepares the driver to
work with both DM and non-DM systems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 16:25:29 +0000 (17:25 +0100)]
net: ks8851: Checkpatch cleanup
Fix various checkpatch complaints.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 17:15:46 +0000 (18:15 +0100)]
net: ks8851: Clean up chip ID readout
There is only one chip ID in the table of chip IDs for this chip.
Read out the chip ID instead and mask off the last "revision" bit
to check the chip ID, this works for all chips in the family. Then
drop the chip ID passing around.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 16:23:11 +0000 (17:23 +0100)]
net: ks8851: Remove type_frame_head
The packet status and length information should be extracted from the
FIFO per-packet. Adjust the code such that it reads the packet meta
data and then the packet afterward, if applicable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 16:18:55 +0000 (17:18 +0100)]
net: ks8851: Trim down struct ks_net
Most of the entries in the structure are useless, remove them. Inline
the rest of uses where applicable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 16:02:51 +0000 (17:02 +0100)]
net: ks8851: Use 16bit RXQCR access
Per KS8851-16MLL, the RXQCR is a 16bit register. Use 16bit accessors
to it consistently and drop the ks_wrreg8() function altogether, as
it is not used anymore.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 16:02:21 +0000 (17:02 +0100)]
net: ks8851: Remove RXQCR cache
The cached RXQCR value is never updated, remove the cache and just use
the bits in the cache directly in the code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 25 Mar 2020 15:52:38 +0000 (16:52 +0100)]
net: ks8851: Replace malloc()+memset() with calloc()
Replace combination of malloc()+memset() with calloc() as the behavior
is exactly the same and the amount of code is reduced. Moreover, remove
printf() in the fail path, as it is useless, and return proper -ENOMEM
return code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Fri, 22 May 2020 14:28:38 +0000 (10:28 -0400)]
Merge tag 'u-boot-rockchip-
20200522' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix rk3288 chromebook veyron support;
- Add pcie driver support for rk3399;
- other fixes for rk3399 boards
Tom Rini [Fri, 22 May 2020 14:28:26 +0000 (10:28 -0400)]
Merge tag 'imx8qxp-fixes' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- Fix i.MX8QXP boot hang when getting CPU temperature
Tom Rini [Fri, 22 May 2020 14:27:24 +0000 (10:27 -0400)]
Merge tag 'efi-2020-07-rc3-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-07-rc3 (2)
Problems fixed with these patches are:
* UEFI sub-system not working with virtio block devices
* Missing SATA support in UEFI sub-system
* A superfluous debug statement
Tom Rini [Fri, 22 May 2020 14:27:06 +0000 (10:27 -0400)]
Merge tag 'uniphier-v2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2020.07
- De-assert write protect for Denali NAND driver
- Clean up include directives
- Migrate to DM_ETH, and remove legacy board_eth_init()
Hayes Wang [Fri, 22 May 2020 08:54:11 +0000 (16:54 +0800)]
eth/r8152: fix typo in register name
The PAL_BDC_CR should be PLA_BDC_CR.
Signed-off-by: Hayes Wang <hayeswang@realtek.com>
Chunfeng Yun [Thu, 14 May 2020 05:55:11 +0000 (13:55 +0800)]
usb: dwc3: fix NULL pointer issue
The phy_bulk pointer *usb_phys is used before allocated,
fix it by using a phy_bulk variable instead in
xhci_dwc3_platdata struct
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Adam Ford [Sat, 16 May 2020 06:19:53 +0000 (01:19 -0500)]
usb: ehci-omap: Add Support for DM_USB and OF_CONTROL
The omap3.dtsi file shows the usbhshost node with two sub-nodes
for ohci and ehci. This patch file creates the usbhshost, and
pulls the portX-mode information. It then locates the EHCI
sub-node, and initializes the EHCI controller with the info
pulled from the usbhshost node.
There is still more to do since there isn't an actual link
between the 'phys' reference and the corresponding phy driver,
and there is no nop-xceiv driver yet.
In the meantime, the older style reference to
CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull
the phy out of reset until the phy driver is completed and the
phandle reference is made.
Signed-off-by: Adam Ford <aford173@gmail.com>
Kurt Miller [Wed, 13 May 2020 19:55:20 +0000 (15:55 -0400)]
rockchip: rk3328: rock64 - fix gen3 SPL hang
Use the same approach as ROC-RK3328-CC which enables SPL GPIO,
pinctl and regulator support. This allows the gen3 board to
boot through SPL and does not break gen2 in the process.
Signed-off-by: Kurt Miller <kurt@intricatesoftware.com>
Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Urja Rannikko [Wed, 13 May 2020 19:15:23 +0000 (19:15 +0000)]
defconfig: veyron: no need for CONFIG_SPL_PINCTRL_FULL
Veyrons do not need full pinctrl support for SPL.
The full pinctrl support does nothing when enabled with OF_PLATDATA,
thus was already unused.
This frees about 4kB of SPL size.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Urja Rannikko [Wed, 13 May 2020 19:15:22 +0000 (19:15 +0000)]
rockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATA
gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang
after
f0921f5098 ("fdt: Sync up to the latest libfdt").
We use the same test that is used in spl_common_init on whether to call
fdtdec_setup to unconditionally avoid linking in the fdt-using code
when not necessary and thus reduce SPL size.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Urja Rannikko [Wed, 13 May 2020 19:15:21 +0000 (19:15 +0000)]
rockchip: veyron: move board_early_init_f to _r (after reloc)
Previously veyron_init() was called in board_init() context, which is
called after relocation. Moving it to veyron.c used board_early_init_f
which is called way earlier, and causes veyron_init to hang.
Using board_early_init_r instead fixes this.
Fixes:
b678f2790c ("rockchip: rk3288: Move veyron_init() back to veyron.c")
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Urja Rannikko [Wed, 13 May 2020 19:15:20 +0000 (19:15 +0000)]
rockchip: spl: veyron speedy boots from SPI
Apparently speedy was forgotten from this list of veyron devices.
Fixes:
49105fb7ed ("rockchip: add common spl board file")
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heinrich Schuchardt [Sat, 9 May 2020 19:31:03 +0000 (21:31 +0200)]
tools: value checks in rkcommon_check_params()
Building with -Wtype-limits yields
tools/rkcommon.c: In function ‘rkcommon_check_params’:
tools/rkcommon.c:158:27: warning: comparison of
unsigned expression < 0 is always false [-Wtype-limits]
158 | if (spl_params.init_size < 0)
| ^
tools/rkcommon.c:165:28: warning: comparison of
unsigned expression < 0 is always false [-Wtype-limits]
165 | if (spl_params.boot_size < 0)
|
Fix the value checks.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sat, 9 May 2020 16:56:24 +0000 (22:26 +0530)]
rockchip: Enable PCIe/M.2 on rock960 board
Due to board limitation some SSD's would work
on rock960 PCIe M.2 only with 1.8V IO domain.
So, this patch enables grf io_sel explicitly to
make PCIe/M.2 to work.
Cc: Tom Cubie <tom@radxa.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sat, 9 May 2020 16:56:23 +0000 (22:26 +0530)]
rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2
Enable PCIe/M.2 support on
- NanoPC-T4
- ROC-RK3399-PC Mezzanine boards.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sat, 9 May 2020 16:56:22 +0000 (22:26 +0530)]
pci: Add Rockchip PCIe PHY controller driver
Yes, it is possible to have a dedicated UCLASS PHY driver
for this Rockchip PCIe PHY but there are some issues on
Generic PHY framework to support the same.
The Generic PHY framework is unable to get the PHY if
the PHY parent is of a different uclass.
Say if we try to get the PCIe PHY then the phy-uclass
will look for PHY in the first instance if it is not
in the root node it will try to probe the parent by
assuming that the actual PHY is inside the parent PHY
of UCLASS_PHY. But, in rk3399 hardware representation
PHY like emmc, usb and pcie are part of syscon which
is completely a different of UCLASS_SYSCON.
Example:
grf: syscon@
ff770000 {
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
pcie_phy: pcie-phy {
compatible = "rockchip,rk3399-pcie-phy";
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
#phy-cells = <1>;
resets = <&cru SRST_PCIEPHY>;
drive-impedance-ohm = <50>;
reset-names = "phy";
status = "disabled";
};
};
Due to this limitation, this patch adds a separate PHY
driver for Rockchip PCIe. This might be removed in future
once Generic PHY supports this limitation.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sat, 9 May 2020 16:56:21 +0000 (22:26 +0530)]
pci: Add Rockchip PCIe controller driver
Add Rockchip PCIe controller driver for rk3399 platform.
Driver support Gen1 by operating as a Root complex.
Thanks to Patrick for initial work.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Jagan Teki [Sat, 9 May 2020 16:56:20 +0000 (22:26 +0530)]
clk: rk3399: Enable/Disable the PCIEPHY clk
Enable/Disable the PCIEPHY clk for rk3399.
CLK is clear in both enable and disable functionality.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>