aco: fix out-of-bounds access when moving s_mem(real)time across SMEM

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8224
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21138>

lavapipe: disable VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BLEND_BIT for int formats

this is unsupported and undefined by the spec

cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21099>

v3dv: ensure we apply binning syncs to secondary command buffers

Currently, we postpone binning syncs until we record draw calls
and can validate if any of them require accessing protected
resources in the binning stage, however, if the draw calls are
recorded in a secondary command buffer and the barriers have
been recorded in the primary command buffer, we won't apply the
binning sync in the secondary when we record the draw calls
and so we must apply it when we execute the secondary in the
primary.

Fixes flakyness in:
dEQP-VK.api.command_buffers.record_many_draws_secondary_2

cc: mesa-stable

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21162>

v3dv: ensure at least V3D_CL_MAX_INSTR_SIZE bytes in last CL instruction

The CLE parser in the sim will read this many bytes for each instruction
in a CL, so we should ensure we have at least that many bytes available
in the BO when reading the last instruction, otherwise we can trigger
a GMP violation. It is not clear whether this behavior applies to real
hardware too.

cc: mesa-stable

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21162>

pvr: remove start/stop transfer flags

These are ignored by the pvrsrvkm KMD and don't exist in the new KMD.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Luigi santivetti <luigi.santivetti@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21132>

meson: Ignore unused variables when assertions are disabled

Fixes: 46b099e3
("meson: Ignore unused variables in release builds")

46b099e3 has some issues:
- it doesn't enable unused variables warning on release builds
with assertions enabled;
- it doesn't disable unused variables warning on debug builds
with assertions disabled;
- it doesn't disable unused variables warning when building
with MSVC and assertions are disabled regardless of buildtype,
see #8147. 3/4 regressions reported there have this limitation
alone as root cause.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21154>

radv: use amd common force_vrs option

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21010>

radv: move radv_consider_force_vrs above radv_fill_shader_info

It will be used by radv_fill_shader_info, no function change.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21010>

anv: use malloc for host only descriptor sets

On integrated products this makes almost no difference but on discrete
it's pretty important.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Chuansheng Liu <chuansheng.liu@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21131>

radv/vcn: enable dynamic dpb tier 2 for h264/h265 on navi21+

navi21 can do separate image support, using tier 2 DPB messages.

This enables support for doing that in the vulkan video driver.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

radv/video: add h265 decode UVD support

Add support for h265 decode on older UVD GPUs

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

radv: add vcn h265 decode.

This adds support for HEVC decode in VCN

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

radv/video: add h264 support for uvd

This adds support for the older UVD h264 decoder.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

radv/video: add initial h264 decoder for VCN

This adds support for H264 decode on VCN hardware.

It uses the full DPB method, and relies on the application
to allocate an arrayed texture for the DPB to be stored into.

RADV_PERFTEST=video_decode is required to enable this.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

radv/video: add initial frameworking.

This just adds the basic commands and objects, and hooks up some
of the queues and extensions.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

radv: add video decoder register setup.

This just assigns the correct registers depending on the gpu family.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

radv: adding video decode queue support

This adds the video queue interactions to radv and builds
on the winsys code previously added.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

ac: add name to codec info struct

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

radv: add new upload alloc aligned api

The video buffers need to have objects aligned at certain ranges,
this enhances the uploader to allow an alignment to be specified.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

radv: remove the status query mark it unsupported.

The current firmware can't support the status query requirements.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20388>

freedreno+ir3: Move storage_16bit to compiler options

This isn't a thing in gl.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21152>

anv: Make a batch decoder for each queue family

The decoder context needs to know what engine it's associated with.
Nowadays, we have render, compute, blitter, even video engines being
used from the same driver.  Rather than trying to have a single decoder
and thwacking the engine field back and forth between calls, we make
one per queue family, and stash a pointer in anv_queue for easy access.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21149>

v3d/v3dv: use shader_info->var_copies_lowered

Instead of passing allow_copies as a parameter for v3d_optimize_nir
(so manually doing that tracking).

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19338>

anv: use shader_info->var_copies_lowered

Instead of passing allow_copies as a parameter for brw_nir_optimize
(so manually doing that tracking).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19338>

radv: use shader_info->var_copies_lowered

Instead of passing allow_copies as a parameter for radv_optimize_nir
(so manually doing that tracking).

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19338>

nir: track if var copies lowering was called

In general we should only call it once, and then we should avoid to
call any lowering that introduce back copies. So far we were tracking
that manually out of the nir shader on several places.

Ideally we would like to add a nir_validate rule, but right now there
are some exceptions to this rule. For example right now the Intel
compiler calls nir_lower_io_to_temporaries as part of linking
tess_ctrl/mesh/task sahders.

One option would be to allow drivers to reset the value, but for now
let's not add that validation rule.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19338>

loader: unregister special event in loader_dri3_drawable_fini

This was inadvertently removed in 98a6cfd3953 and causes continuous
memory leaks as events are being received after the context has been
unbound.

Fixes: 3170b63314f ("loader: Add infrastructure for tracking active CRTC resources")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8238
Signed-off-by: Yuxuan Shui <yshuiv7@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21128>

r300: set register file to none if swizzles are constant only

In constant folding when converting multiply by zero to mov.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21141>

fix: gallivm: limit usage of LLVMContextSetOpaquePointers() to LLVM 15

LLVMContextSetOpaquePointers() was a temporary workaround offered to
allow transitioning to opaque pointers. Mesa is ready for this now with
recent versions of LLVM (16+). Therefore we limit the workaround of
using LLVMContextSetOpaquePointers() to LLVM 15 now, that this C
interface was removed in LLVM 17.

Reference: https://github.com/llvm/llvm-project/commit/1270879376025457e266572c7cccc51eb5de9276
Suggested-by: Dave Airlie <airlied@redhat.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8183
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21124>

radv: Use common ycbcr conversion lowering

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20731>

vulkan,nir: Refactor ycbcr conversion state into a struct

This will be useful for RADV since it hashes the state.

v3dv changes:
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20731>

radv: Remove radv_indirect_unaligned_dispatch

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21071>

radv: Use an ordered dispatch for BVH encoding

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21071>

radv: Implement ordered compute dispatches

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21071>

radv: Make radv_compute_dispatch non-static

To avoid adding yet another radv_*_dispatch helper.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21071>

Revert "ci: disable Collabora's LAVA lab for maintance"

This reverts commit 60d7e15a7e61c6d51c3fa8e26839793782a12fb4.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20903>

radeonsi/ci: Skip slow traces on raven

Two traces timed out during Collabora's LAVA farm re-enablement.
Possibly, some commit made them slower during farm downtime.

- https://gitlab.freedesktop.org/mesa/mesa/-/jobs/35934124

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20903>

radeonsi/ci: Update stoney test expectations

Some jobs failed during the re-enablement of Collabora's LAVA farm.

The trace job radeonsi-stoney-traces:amd64 produced some traces with
almost unnoticeable lighting spread difference, so I updated all the
traces.

Now the test spec@ext_texture_lod_bias@lodbias is failing after running
a couple of times.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20903>

intel/dev: Add another EHL pci id

described as "32 Execution Unit (EU) Super SKU" in:
Intel Atom x6000E Series, and Intel Pentium and Celeron N and
J Series Processors for IoT Applications
Datasheet, Volume 1
Document Number: 636112-1.6

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21129>

intel/dev: remove invalid EHL pci id

removed in linux
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21129>

zink: fix max acquired image count

according to spec, the maximum number of acquired images can be calculated with

swapchain_size - VkSurfaceCapabilitiesKHR::minImageCount + 1

the previous calculation was both wrong and occurring in the wrong place,
so this corrects both issues

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21095>

zink: clear null image surfaces to 0

GL Spec says that imageLoad from incomplete images must return 0.
This is not really spec compliant as for proper behavior nullDescriptor
and robustImageAccess2 is needed.
A workaround for lack of either of these requires a shader variant.
Clearing the null surface and hoping the app doesn't write to the image
is closer to spec, while avoiding a shader recompile.

KHR-GL46.shader_image_load_store.incomplete_textures tests this.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21135>

radv: do not insert fast-linked libraries to the shaders cache

Similar to fast-linked pipelines that aren't added to the cache.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21133>

zink: fix leak when rebinding same image surface

simple way to reproduce this is to run these 4 together:
KHR-GL46.gpu_shader5.images_array_indexing
KHR-GL46.shader_image_load_store.advanced-allMips
KHR-GL46.shader_image_load_store.advanced-sso-simple
KHR-GL46.shader_image_load_store.incomplete_textures

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21134>

zink: only save frag const buffers when used by blit

fixes upload manager constant buffer leak.
zink only needs to save the const buffer for stencil fallback blits.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21134>

radv/llvm: use the ring_offsets shader arg

Besides being nicer, this also fixes load_sample_positions_amd with LLVM.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>

ac/llvm: let ring_offsets be accessed like a normal arg

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>

ac: move ring_offsets to ac_shader_args

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>

radv: set state.vbo_misaligned_mask_invalid in radv_bind_vs_input_state

Found by inspection. Something probably hangs because of this, but I don't
know what.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: c199a5160a0 ("radv: bind the VS input state for prologs created with GPL")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20913>

pvr: add padding bytes when allocating buffer memory

We need to pad VkBuffers to ensure we don't read beyond a page boundary.

An alternative to this approach would be to allocate an additional virtual
page when binding memory to the buffer, and to map this to the first
physical address, so both the first and last virtual page point to the same
physical location. This would be less expensive in terms of memory usage,
but more complex and invasive, hence the simpler approach has been taken
for now.

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21101>

pvr: Set SPMSCRATCHBUFFER flag.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>

pvr: Update comment about ZS and MSAA buffers for pvrsrvkm submission.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>

pvr: Acquire scratch buffer on framebuffer creation.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>

pvr: Add SPM scratch buffer infrastructure.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>

intel/ds: track end of pipe bits

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

anv: rename a few internal functions to highlight gfx use

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

anv: rename RT pipeline function helper

Making it clear this is intended for RT pipelines only.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/fs: make alpha_to_coverage a tristate

That way in some cases we can do this dynamically.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/fs: Rework dynamic coarse handling

Use 2 flags for PI & RT messages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/fs: Break out yet another FB write helper

This new helper, do_emit_fb_writes() does the actual walk over all the
render targets to emit each of the different FB writes.  We want this in
a helper because we're about to go a bit crazy with coarse.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/fs/validate: Assert SEND [extended] descriptors are uniform

This is required by code-gen since it generates a 1-wide OR and it'll
blow up if the register width > 1.  It's also way better than the "your
register is the wrong size" assert you get from the more generic
validation check.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/compiler: Convert wm_prog_key::multisample_fbo to a tri-state

This allows us to communicate to the back-end that we don't actually
know if the framebuffer is multisampled or not.  No drivers set anything
but ALWAYS/NEVER and we still have a few ALWAYS/NEVER assumptions but
those should be asserted.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/compiler: Convert wm_prog_key::persample_interp to a tri-state

This allows for the possibility that we may not know at compile time if
sample shading is enabled through the API.  While we're here, also
document exactly what this bit means so we don't confuse ourselves.

v2: Fixup coarse pixel values (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/fs: Make per-sample and coarse dispatch tri-state

Whenever one of them is BRW_SOMETIMES, we depend on dynamic flag pushed
in as a push constant.  In this case, we have to often have to do the
calculation both ways and SEL the result.  It's a bit more code but
decouples MSAA from the shader key.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/compiler: Convert brw_wm_aa_enable to brw_sometimes

There are other cases where we want a tri-state logic like this.  May as
well have one enum for all the cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/fs: Return early in a couple builtin setup helpers

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/compiler: Use SHADER_OPCODE_SEND for PI messages

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

nir: Remove nir_lower_io_force_sample_interpolation

It's no longer used.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/nir: Lower barycentrics to per-sample in a dedicated pass

This is more similar to what we do for single-sample and it should be
more clear going forward once our lowering gets more complex.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

intel/compiler: Document wm_prog_key::persample_interp

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>

amd: don't hardcode real VGPR allocation granularity on gfx10.3 and gfx11

That's how it really works.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>

amd,util: fix how lod bias is converted to fixed-point

according to internal docs

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>

amd/surface: clean up is_dcc_supported_by_L2

no functional change, though this removes "<=" for navi10, which was
never true in the "<" case

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>

radeonsi: clean up si_set_mutable_tex_desc_fields

- sink code into existing branches
- remove unnecessary clearing of fields
- no functional change

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>

amd: define new SET_*_REG_PAIRS packets

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>

radeonsi/gfx11: don't add alpha to mrt0 format for A2C if exporting via mrtz

If alpha-to-coverage is exported via mrtz, don't upgrade the mrt0 format
to one with an alpha channel.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>

radeonsi/gfx11: don't add mrt0 export for alpha-to-coverage if mrtz is present

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>

nir/lower_clip: Only emit 1 discard

If we have multiple clip planes, rather than emit multiple discards we can just
OR together the discard criteria. Then a nir_opt_algebraic rule kicks in to
optimize out the flt/.../flt/ior/.../ior into fmin/.../fmin/flt, generating
much less code at the end.

Written while debugging an unrelated issue with the clip lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21103>

zink: conditionally enable PIPE_CAP_NULL_TEXTURES

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>

radeonsi: set PIPE_CAP_NULL_TEXTURES

fixes #8163

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>

gallium: add PIPE_CAP_NULL_TEXTURES

this allows drivers to indicate that they support sampling from null
textures instead of using fallback textures

for now, this is only used for depth-based fallback textures

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>

radv: Scalarize global IO with LLVM enabled

Fixes the "atomic store operand must have integer, pointer, or floating point type!" error with RADV_DEBUG=llvm,checkir.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20840>

ac/llvm: Fix validation error with global io

Fixes: afd645f0576 ("ac/llvm: remove LLVMBuildGEP usages")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20521>

radv/llvm: Use the shader names as module name

This makes it easier to identify which (if any) shaders fail validation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20521>

radv/rq: Use 16 stack entries if there is only one ray query

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21120>

meson: Fix Asahi build on macOS

!19950 introduced a dependency between NIR and Vulkan headers, and the
Vulkan headers try to include X11 headers we cannot find on macOS.

Disable this (we have no plans for Vulkan on the macOS testing platform
anyway).

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21059>

agx: Don't scalarize preambles in NIR

Scalarizing preambles in NIR isn't really necessary, we can do it more
efficiently in the backend. This makes the final NIR a lot less annoying to
read; the backend IR was already nice to read thanks to all the scalarized moves
being copypropped. Plus, this is a lot simpler.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>

agx: Lower uniform sources with a dedicated pass

Move the decision of "can I copyprop this uniform?" from copyprop to a
standalone lowering pass. This is more straightforward and will enable the next
patch. This has the side effect of sinking load_preamble instructions, for a
nice reduction in register pressure. Instruction count increase is from
rematerializing some moves, which should be more than balanced out by the
reduced register pressure.

total instructions in shared programs: 1523285 -> 1523317 (<.01%)
instructions in affected programs: 1148 -> 1180 (2.79%)
helped: 0
HURT: 13
HURT stats (abs)   min: 1.0 max: 4.0 x̄: 2.46 x̃: 2
HURT stats (rel)   min: 0.69% max: 7.69% x̄: 3.65% x̃: 2.61%
95% mean confidence interval for instructions value: 1.78 3.14
95% mean confidence interval for instructions %-change: 2.16% 5.15%
Instructions are HURT.

total bytes in shared programs: 10444532 -> 10444724 (<.01%)
bytes in affected programs: 7386 -> 7578 (2.60%)
helped: 0
HURT: 13
HURT stats (abs)   min: 6.0 max: 24.0 x̄: 14.77 x̃: 12
HURT stats (rel)   min: 0.63% max: 7.14% x̄: 3.40% x̃: 2.48%
95% mean confidence interval for bytes value: 10.68 18.85
95% mean confidence interval for bytes %-change: 2.02% 4.78%
Bytes are HURT.

total halfregs in shared programs: 419444 -> 416434 (-0.72%)
halfregs in affected programs: 27080 -> 24070 (-11.12%)
helped: 634
HURT: 0
helped stats (abs) min: 1.0 max: 30.0 x̄: 4.75 x̃: 2
helped stats (rel) min: 2.90% max: 54.55% x̄: 13.13% x̃: 8.51%
95% mean confidence interval for halfregs value: -5.08 -4.41
95% mean confidence interval for halfregs %-change: -14.03% -12.23%
Halfregs are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>

agx: Run DCE twice

Needed to combine fsat with vectors due to nir_lower_blend changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>

agx: Allow uniform sources on phis

The parallel copy lowering has been able to handle uniform sources since 98f0ebf2647 ("agx:
Pass agx_index to agx_copy"), and uniform sources work fine with phis. It's not
super common but there's no need to restrict them. This is a small instruction
count win and will greatly simplify the lowering later in this series.

total instructions in shared programs: 1523806 -> 1523285 (-0.03%)
instructions in affected programs: 17088 -> 16567 (-3.05%)
helped: 38
HURT: 1
helped stats (abs) min: 1.0 max: 44.0 x̄: 13.95 x̃: 7
helped stats (rel) min: 0.42% max: 18.64% x̄: 4.73% x̃: 1.26%
HURT stats (abs)   min: 9.0 max: 9.0 x̄: 9.00 x̃: 9
HURT stats (rel)   min: 8.57% max: 8.57% x̄: 8.57% x̃: 8.57%
95% mean confidence interval for instructions value: -17.95 -8.77
95% mean confidence interval for instructions %-change: -6.35% -2.43%
Instructions are helped.

total bytes in shared programs: 10447658 -> 10444532 (-0.03%)
bytes in affected programs: 118850 -> 115724 (-2.63%)
helped: 38
HURT: 1
helped stats (abs) min: 6.0 max: 264.0 x̄: 83.68 x̃: 45
helped stats (rel) min: 0.36% max: 16.51% x̄: 4.14% x̃: 1.09%
HURT stats (abs)   min: 54.0 max: 54.0 x̄: 54.00 x̃: 54
HURT stats (rel)   min: 7.30% max: 7.30% x̄: 7.30% x̃: 7.30%
95% mean confidence interval for bytes value: -107.68 -52.62
95% mean confidence interval for bytes %-change: -5.55% -2.13%
Bytes are helped.

total halfregs in shared programs: 419446 -> 419444 (<.01%)
halfregs in affected programs: 29 -> 27 (-6.90%)
helped: 1
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>

xlib: fix glXDestroyContext in Gallium frontends

when glx is built with -Dglx=xlib, the mishandle in
glXDestroyContext causes glmark2 to exit unexpectedly.

Error: Glmark2 needs OpenGL(ES) version >= 2.0 to run (but version string is: '(null)')!
Error: Failed to add vertex shader from file None:
Error:   Failed to create the new program
[build] <default>: Set up failed

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3985

Signed-off-by: Luc Ma <luc@sietium.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21067>

zink: fix cap check for arb sparse texture2

arb_sparse_texture2 also enables multisampled sparse textures.
bring back the check for msaa support.

fixes #8229

Fixes: 4f8ba2b9aae ("zink: fix sparse residency query and minLOD feature checks")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21121>

nir/print: Pretty-print color0/1_interp

These are an enum. Furthermore, their 0 state is INTERP_MODE_NONE which we
shouldn't bother printing at all.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>

nir/print: Pretty-print I/O semantic locations

Instead of printing the raw location number, which is pretty hard to interpret,
let's print the name of the location. Example output:

   vec4 16 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=0,
   component=0, dest_type=float16 /*144*/, io location=VARYING_SLOT_VAR0 slots=1
   mediump /*8388768*/)

One of the "regressions" from moving to purely lowered I/O with all variables
removed is a lack of debuggability, since otherwise these location strings don't
show up anywhere in the printed shader! By contrast this should make the lowered
I/O nice to read like the early I/O.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>

nir/print: Extract get_location_str

Locations show up in two places: variables and lowered I/O semantics. We want to
reuse the logic in both places, so extract it out. The extracted logic is IMO
easier to read, too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>

agx: Implement barriers

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>

agx: Implement compute ID intrinsics

These NIR intrinsics map to vectors of special registers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>

asahi: Identify more compute-related XML

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>

asahi: Implement load_ssbo_address/get_ssbo_size

More uniforms that get pushed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>

asahi: Add compute batches

Add a specialized agx_batch for compute commands (queued to the CDM instead of
the VDM for graphics). This uses a sentinel value for the width.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>