Chia-I Wu [Mon, 16 Feb 2015 20:45:03 +0000 (04:45 +0800)]
ilo: always set up BLEND_STATE on Gen8
There is now an DW0 that seems to be always referenced.
Chia-I Wu [Mon, 16 Feb 2015 20:54:17 +0000 (04:54 +0800)]
ilo: fix alpha test on Gen8
Shoudl use GEN8_BLEND_DW0_ALPHA_TEST_ENABLE instead of
GEN6_RT_DW1_ALPHA_TEST_ENABLE (and others).
Ben Widawsky [Mon, 16 Feb 2015 04:06:59 +0000 (20:06 -0800)]
i965/simd8vs: Fix SIMD8 atomics
The short version: we need to set bits in R0.7 which provide a mask to be used
for PS kill samples/pixels. Since the VS has no such concept, we just need to
set all 1.
The longer version...
Execution for SIMD8 atomics is defined as follows:
SIMD8: The low 8 bits of the execution mask are ANDed with 8 bits of the
Pixel/Sample Mask from the message header. For the typed messages, the Slot
Group in the message descriptor selects either the low or high 8 bits. For the
untyped messages, the low 8 bits are always selected. The resulting mask is used
to determine which slots are read into the destination GRF register (for read),
or which slots are written to the surface (for write). If the header is not
present, only the low 8 bits of the execution mask are used.
The message header for untyped messages is defined in R0.7 "This field contains
the 16-bit pixel/sample mask to be used for SIMD16 and SIMD8 messages. All 16
bits are used for SIMD16 messages. For typed SIMD8 messages, Slot Group selects
which 8 bits of this field are used. For untyped SIMD8 messages, the low 8 bits
of this field are used." Furthermore, "The message header for the untyped
messages only needs to be delivered for pixel shader threads, where the
execution mask may indicate pixels/samples that are enabled only due to
derivative (LOD) calculations, but the corresponding slot on the surface must
not be accessed." We're not using a pixel shader here, but AFAICT, this mask is
used for all stages.
This leaves two options, Remove the header, or make the VS code emit the correct
thing for the header. I believe one of the goals of using SIMD8 VS was to get as
much code reuse as possible, and so I chose the latter. Since the VS has no such
thing as kill instructions, the mask is derived simple as all 1's.
v2:
Add a comment to the code (stolen from Curro on the mailing list)
Change the control flow style (Curro + Jason)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87258
Cc: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Brian Paul [Mon, 16 Feb 2015 15:38:56 +0000 (08:38 -0700)]
mesa: move assertion after declarations in texstore.c
To fix MSVC build.
Brian Paul [Tue, 10 Feb 2015 19:17:18 +0000 (12:17 -0700)]
mesa: silence uninitialized var warning in get_tex_rgba_uncompressed()
Reviewed-by: Matt Turner <mattst88@gmail.com>
Neil Roberts [Tue, 25 Nov 2014 17:52:27 +0000 (17:52 +0000)]
meta: Fix saving the results of the current occlusion query
When restoring the current state in _mesa_meta_end it was previously trying to
copy the on-going sample count of the current occlusion query into the new
query after restarting it so that the driver will continue adding to the
previous value. This wouldn't work for two reasons. Firstly, the query might
not be ready yet so the Result member will usually be zero. Secondly the saved
query is stored as a pointer to the query object, not a copy of the struct, so
it is actually restarting the exact same object. Copying the result value is
just copying between identical addresses with no effect. The call to
_mesa_BeginQuery will have always reset it back to zero.
This patch fixes it by making it actually wait for the query object to be
ready before grabbing the previous result. The downside of doing this is that
it could introduce a stall but I think this situation is unlikely so it might
not matter too much. A better solution might be to introduce a real
suspend/resume mechanism to the driver interface. This could be implemented in
the i965 driver by saving the depth count multiple times like it does in the
i945 driver.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88248
Reviewed-by: Carl Worth <cworth@cworth.org>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Francisco Jerez [Thu, 12 Feb 2015 08:20:49 +0000 (10:20 +0200)]
i965/vec4: Override destination register writemask in sampler message send.
This line was removed by accident in commit
16b911257440afbd77a6eb762e28df62e3c19bc7 causing a regression in the
ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_vert Khronos conformance
test. It's necessary because the swizzle_result() code below expects
all four components of the vector to be valid.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89094
Tested-by: Lu Hua <huax.lu@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Fri, 13 Feb 2015 07:29:32 +0000 (08:29 +0100)]
i965: Fix a crash in the texture gradient lowering pass with cube samplers
We need to swizzle the rhs to match the number of components in the writemask,
otherwise we'll hit an assertion in ir_assignment.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Iago Toral Quiroga [Fri, 13 Feb 2015 11:56:26 +0000 (12:56 +0100)]
mesa: Fix element count for byte-swaps in texstore, readpix and texgetimage
Some old format conversion code in pack.c implemented byte-swapping like this:
GLint comps = _mesa_components_in_format(dstFormat);
GLint swapSize = _mesa_sizeof_packed_type(dstType);
if (swapSize == 2)
_mesa_swap2((GLushort *) dstAddr, n * comps);
else if (swapSize == 4)
_mesa_swap4((GLuint *) dstAddr, n * comps);
where n is the pixel count. But this is incorrect for packed formats,
where _mesa_sizeof_packed_type is already returning the size of a pixel
instead of the size of a single component, so multiplying this by the
number of components in the format results in a larger element count
for _mesa_swap than we want.
Unfortunately, we followed the same implementation for byte-swapping
in the rewrite of the format conversion code for texstore, readpixels
and texgetimage.
This patch computes the correct element counts for _mesa_swap calls
by computing the bytes per pixel in the image and dividing that by the
swap size to obtain the number of swaps required per pixel. Then multiplies
that by the number of pixels in the image to obtain the swap count that
we need to use.
Also, when handling byte-swapping in texstore_rgba, we were ignoring
the image's depth. This patch fixes this too.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Iago Toral Quiroga [Fri, 13 Feb 2015 09:23:26 +0000 (10:23 +0100)]
mesa: Handle transferOps in texstore_rgba
In the recent rewrite of the format conversion code we did not handle this.
This patch adds the missing support.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89068
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Matt Turner [Fri, 9 Jan 2015 06:56:44 +0000 (22:56 -0800)]
i965/fs: Handle U/UW-type immediates in the generator.
Matt Turner [Fri, 9 Jan 2015 06:55:16 +0000 (22:55 -0800)]
i965/fs: Handle W/UW-type immediates in dump_instructions().
Matt Turner [Fri, 13 Feb 2015 18:46:32 +0000 (10:46 -0800)]
i965: Let dump_instructions() work before calculate_cfg().
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Matt Turner [Fri, 13 Feb 2015 18:34:39 +0000 (10:34 -0800)]
i965/fs: Call calculate_cfg() before optimize().
The CFG is fundamental to the FS IR, not merely a piece of optimization.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Matt Turner [Thu, 5 Feb 2015 02:08:30 +0000 (18:08 -0800)]
i965: Optimize multiplication by -1 into a negated MOV.
instructions in affected programs: 968 -> 942 (-2.69%)
helped: 4
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Thu, 5 Feb 2015 02:08:21 +0000 (18:08 -0800)]
i965: Add an is_negative_one() method.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Thu, 12 Feb 2015 02:01:49 +0000 (02:01 +0000)]
i965/vec4/vp: Use vec4_visitor::CMP.
... instead of emit(BRW_OPCODE_CMP, ...). In commit
6b3a301f I changed
vec4_visitor::CMP to set the destination's type to that of src0. In the
following commit (
2335153f) I removed an apparently now unnecessary work
around for Gen8 that did the same thing.
But there was a single place that emitted a CMP instruction without
using the vec4_visitor::CMP function. Use it there.
And change dst_null_d to dst_null_f for good measure, since ARB vp
doesn't have integers.
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89032
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chia-I Wu [Sun, 15 Feb 2015 05:21:51 +0000 (13:21 +0800)]
ilo: fix some state pointer commands on Gen8
3DSTATE_CC_STATE_POINTERS seems to be ignored when bit 0 of DW1 is not set.
Follow i965 and set the bit for 3DSTATE_CC_STATE_POINTERS and
3DSTATE_BLEND_STATE_POINTERS. Add gen checks for all state pointer commands.
Ilia Mirkin [Sat, 14 Feb 2015 06:43:31 +0000 (01:43 -0500)]
nvc0: allow holes in xfb target lists
Tested with a modified xfb-streams test which outputs to streams 0, 2,
and 3.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Sat, 14 Feb 2015 06:27:19 +0000 (01:27 -0500)]
st/mesa: treat resource-less xfb buffers as if they weren't there
If a transform feedback buffer's size is 0, st_bufferobj_data doesn't
end up creating a buffer for it. There's no point in trying to write to
such a buffer, so just pretend as if it's not really there.
This fixes arb_gpu_shader5-xfb-streams-without-invocations on nvc0.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Sat, 14 Feb 2015 04:21:36 +0000 (23:21 -0500)]
nvc0: bail out of 2d blits with non-A8_UNORM alpha formats
This fixes the teximage-colors uploads with GL_ALPHA format and
non-GL_UNSIGNED_BYTE type.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sat, 14 Feb 2015 20:16:03 +0000 (12:16 -0800)]
i965/nir: Don't support gl_FrontFacing as an input variable
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Sat, 14 Feb 2015 20:10:32 +0000 (12:10 -0800)]
nir: Make gl_FrontFacing a system_value
GLSL IR labels gl_FrontFacing as an input variable and not a system value.
This commit makes NIR silently translate gl_FrontFacing to a system value
so that it properly gets translated into a load_system_value intrinsic.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Sat, 14 Feb 2015 20:09:31 +0000 (12:09 -0800)]
i965/nir: Add support for nir_intrinsic_load_front_face
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Mon, 9 Feb 2015 22:22:14 +0000 (14:22 -0800)]
nir/lower_phis_to_scalar: Fix some logic in is_phi_scalarizable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Shawn Starr [Sat, 14 Feb 2015 02:16:17 +0000 (21:16 -0500)]
clover: Use Legacy PassManager for LLVM trunk (3.7)
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Shawn Starr <shawn.starr@rogers.com>
Chia-I Wu [Fri, 13 Feb 2015 22:28:12 +0000 (06:28 +0800)]
ilo: fix JIP/UIP on Gen8
UIP is in DW2 and JIP is in DW3 on Gen8. Also, the units are in bytes.
Chia-I Wu [Fri, 13 Feb 2015 22:25:27 +0000 (06:25 +0800)]
ilo: do not set GEN6_THREADCTRL_SWITCH
It is not needed on Gen6+, and it appears to be broken on Gen8.
Chia-I Wu [Fri, 13 Feb 2015 19:07:51 +0000 (03:07 +0800)]
ilo: correct ISA UIP/JIP decoding for Gen8
JIP is int32_t and UIP is in DW2 on Gen8.
Chia-I Wu [Fri, 13 Feb 2015 19:05:47 +0000 (03:05 +0800)]
ilo: prepare for 64-bit immediates decoding
Replace imm32 by imm64. Add more ways (UD, D, etc) to access the immediate.
Chia-I Wu [Fri, 13 Feb 2015 18:23:53 +0000 (02:23 +0800)]
ilo: cleanup ISA DW1 decoding
Decode the higher and lower 16 bits separately.
Chia-I Wu [Fri, 13 Feb 2015 18:18:55 +0000 (02:18 +0800)]
ilo: cleanup ISA DW0 decoding
Add disasm_inst_decode_dw0_opcode_gen6() to decode the opcode. Simplify
branch_ctrl/acc_wr_ctrl decoding.
Chia-I Wu [Thu, 12 Feb 2015 20:04:18 +0000 (04:04 +0800)]
ilo: update some outdated gen checks
Update gen checks for 3DSTATE_POLY_STIPPLE_OFFSET,
3DSTATE_POLY_STIPPLE_PATTERN, 3DSTATE_LINE_STIPPLE, and
3DSTATE_AA_LINE_PARAMETERS.
Chia-I Wu [Thu, 12 Feb 2015 19:59:45 +0000 (03:59 +0800)]
ilo: fix rectlist length on Gen8
5 PIPE_CONTROLs, 2 3DSTATE_WM_HZ_OP, and depth buffer setup require 65 DWords.
Chia-I Wu [Thu, 12 Feb 2015 19:54:32 +0000 (03:54 +0800)]
ilo: fix 3DSTATE_VF_TOPOLOGY
The pipe primitive type was wrongly translated twice.
Jose Fonseca [Fri, 13 Feb 2015 13:51:28 +0000 (13:51 +0000)]
os,llvmpipe: Set rasterizer thread names on Linux.
To help identify llvmpipe rasterizer threads -- especially when there
can be so many.
We can eventually generalize this to other OSes, but for that we must
restrict the function to be called from the current thread. See also
http://stackoverflow.com/a/7989973
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Fri, 13 Feb 2015 09:46:44 +0000 (09:46 +0000)]
uti/u_atomic: Don't test p_atomic_add with booleans.
Add another class of tests.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=89112
I failed to spot this in my previous change, because bool was a typedef
for char on the system I tested.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tapani Pälli [Thu, 12 Feb 2015 12:33:53 +0000 (14:33 +0200)]
mesa: fix OES_texture_float texture render target behavior
Current implementation allowed usage of unsized type texture GL_FLOAT
and GL_HALF_FLOAT as a render target as this was 'expected behavior' by
WEBGL_oes_texture_float and is also allowed by the oes-texture-float
WebGL test. However this broke some ES3 conformance tests that do not
accept such behavior. Patch sets such an fbo incomplete as expected by
the ES3 conformance tests. Textures with sized types like RGBA32F will
still continue to work as render targets.
v2: code style cleanups (Ian Romanick, Matt Turner)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88905
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Eric Anholt [Thu, 12 Feb 2015 22:17:21 +0000 (14:17 -0800)]
vc4: Make SF be a flag on the QIR instructions.
Right now the places that used to emit a mov.sf just put the SF on the
previous instruction when it generated the source of the SF value. Even
without optimization to push the sf up further (and kill thus potentially
kill more MOVs), this gets us:
total uniforms in shared programs: 13455 -> 13457 (0.01%)
uniforms in affected programs: 3 -> 5 (66.67%)
total instructions in shared programs: 40296 -> 40198 (-0.24%)
instructions in affected programs: 12595 -> 12497 (-0.78%)
Eric Anholt [Wed, 11 Feb 2015 22:55:42 +0000 (14:55 -0800)]
r200: Drop unused variable.
Quiets compiler warning since
e7f2f2dea5acdbd1a12ed88914e64a38a97432f0.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Eric Anholt [Wed, 11 Feb 2015 22:54:33 +0000 (14:54 -0800)]
i965: Quiet another compiler warning about uninitialized values.
The compiler can't tell that we're always going to hit the first if block
on the first time through the loop.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Wed, 11 Feb 2015 22:53:08 +0000 (14:53 -0800)]
i965: Move some asserts to unreachable.
If execution was supposed to be supported in this case, we'd run into
trouble from completely uninitialized sat_imm values.
v2: Drop the '!' before the string.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Wed, 11 Feb 2015 22:50:35 +0000 (14:50 -0800)]
i965: Shut up a compiler warning about uninitialized var.
We always pass this argument, even if it won't be used by the particular
texture op.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Carl Worth [Thu, 12 Feb 2015 18:14:24 +0000 (10:14 -0800)]
Revert use of Mesa IR optimizer for ARB_fragment_programs
Commit
f82f2fb3dc770902f1657ab1c22e6004faa3afab added use of the Mesa
IR optimizer for both ARB_fragment_program and ARB_vertex_program, but
only justified the vertex-program portions with measured performance
improvements.
Meanwhile, the optimizer was seen to generate hundreds of unused
immediates without discarding them, causing failures.
Discard the use of the optimizer for now to fix the regression. (In
the future, we anticpate things moving from Mesa IR to NIR for better
optimization anyway.)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82477
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
CC: "10.3 10.4 10.5" <mesa-stable@lists.freedesktop.org>
Jose Fonseca [Thu, 12 Feb 2015 19:31:20 +0000 (19:31 +0000)]
util/u_atomic: Use lower-case variables in _Interlocked* helpers.
Jose Fonseca [Wed, 11 Feb 2015 15:30:39 +0000 (15:30 +0000)]
util/u_atomic: Add _InterlockedExchangeAdd8/16 for older MSVC.
We need to build certain parts of Mesa (namely gallium, llvmpipe, and
therefore util) with Windows SDK 7.0.7600, which includes MSVC 2008.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Wed, 11 Feb 2015 15:21:25 +0000 (15:21 +0000)]
util/u_atomic: Test p_atomic_add() for 8bit integers.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Ilia Mirkin [Thu, 12 Feb 2015 11:16:27 +0000 (06:16 -0500)]
docs: add ARB_draw_indirect to ES 3.1 list
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Axel Davy [Wed, 14 Jan 2015 19:36:04 +0000 (20:36 +0100)]
egl: Soften several HAVE_DRM_PLATFORM to HAVE_LIBDRM
To fix build when libdrm is not found,
commit
a594cec7e3ef275c386054127a357110a19dd823 did put several
parts of egl code under #ifdef HAVE_DRM_PLATFORM.
HAVE_DRM_PLATFORM means the egl drm platform is being built.
What should have been used instead is HAVE_LIBDRM.
At a few locations, the HAVE_DRM_PLATFORM introduced
have already been replaced by HAVE_LIBDRM, this patch
replaces the remaining occurences.
This patch makes for example EGL_EXT_image_dma_buf_import
be advertised by egl under x11 when the drm egl platform
is not built, whereas previously it required the drm egl
platform to be built.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Tue, 10 Feb 2015 15:11:09 +0000 (15:11 +0000)]
auxiliary/vl: bring back the VL code for the dri targets
With commit
c642e87d9f4(auxiliary/vl: rework the build of the VL code)
we split out the VL code into a separate static library that was meant
to be used by the VL targets alone - va, vdpau, xvmc.
The commit failed to consider the way we handle vdpau-gl interop and
broke it. Bring back the functionality by keeping the vl <> vl_stub
separation as requrested by Christian.
v2: Update the omx target as well. Update mesa-stable email address.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86837
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Andy Furniss <adf.lists@gmail.com>
Emil Velikov [Tue, 10 Feb 2015 14:14:16 +0000 (14:14 +0000)]
configure: rework wayland_scanner handling(fix make distcheck)
Currently having the wayland-scanner is optional, which causes problems
when autotools parses through the makefiles, and tries to generate all
the BUILT_SOURCES.
As the config option --with-egl-platform=wayland is not the default, we
won't end up setting the WAYLAND_SCANNER variable, which in turn will
cause some files to not get generated.
There has been a wayland-scanner package as of wayland 1.2 which
provides a variable for the scanner binary, so let's use that one and
fall back to manually searching via AC_PATH_PROG when needed.
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Tue, 10 Feb 2015 13:10:18 +0000 (13:10 +0000)]
nir: add missing header to the sources list
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Sat, 7 Feb 2015 19:20:16 +0000 (19:20 +0000)]
nir: resolve nir.h dependency list (fix make distcheck)
Use nir/nir_opcodes.h as is (w/o the absolute path), as it is the target
name used to generate the actual file. Otherwise the target is missing,
the file won't get generated and the build will fail.
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Martin Peres [Thu, 12 Feb 2015 09:24:37 +0000 (11:24 +0200)]
docs: update GL3.txt to state my current work on the dsa extension
Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
Ben Widawsky [Wed, 11 Feb 2015 01:22:45 +0000 (17:22 -0800)]
i965/vs/skl: Use vec4 datatypes for message header
We're using a SIMD4x2 sampler message, which has execsize 4, and so the
register width must be <= 4. Use <4,4,1> regioning instead of <8,8,1>
regioning to access the same data but avoid tripping the assert.
Fixes the following piglit tests:
spec/glsl-1.20/compiler/structure-and-array-operations/array-selection.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-basic.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-struct.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-function.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-array.vert
glslparsertest/glsl2/condition-07.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-variable.vert
v2: Better commit message courtesy of Ken.
I had a discussion with Ken, and we both question how we end up with a mov and
execsize 4. For now though, this fixes the piglit tests, so we can worry about
it later.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chia-I Wu [Tue, 27 Jan 2015 11:48:39 +0000 (19:48 +0800)]
ilo: update screen init for Gen8
This is very preliminary and is only tested with glxgears. All information
about Gen8 is derived from i965 and beignet.
Chia-I Wu [Wed, 11 Feb 2015 06:31:54 +0000 (14:31 +0800)]
ilo: update outdated render command emissions for Gen8
Chia-I Wu [Wed, 11 Feb 2015 06:21:42 +0000 (14:21 +0800)]
ilo: update rectlist command emission for Gen8
Chia-I Wu [Tue, 27 Jan 2015 12:11:27 +0000 (20:11 +0800)]
ilo: update draw command emission for Gen8
Chia-I Wu [Tue, 27 Jan 2015 12:10:46 +0000 (20:10 +0800)]
ilo: update surface state emission for Gen8
Chia-I Wu [Tue, 27 Jan 2015 12:10:19 +0000 (20:10 +0800)]
ilo: update dynamic state emission for Gen8
Chia-I Wu [Tue, 27 Jan 2015 12:00:48 +0000 (20:00 +0800)]
ilo: update outdated gen assertions for Gen8
Chia-I Wu [Mon, 26 Jan 2015 09:12:33 +0000 (17:12 +0800)]
ilo: add new WM related helpers for Gen8
Chia-I Wu [Mon, 9 Feb 2015 23:13:11 +0000 (07:13 +0800)]
ilo: update VS related functions for Gen8
Chia-I Wu [Mon, 9 Feb 2015 23:10:20 +0000 (07:10 +0800)]
ilo: update VF related functions for Gen8
Chia-I Wu [Sun, 25 Jan 2015 10:05:04 +0000 (18:05 +0800)]
ilo: update SAMPLER_STATE for Gen8
Chia-I Wu [Mon, 26 Jan 2015 07:52:06 +0000 (15:52 +0800)]
ilo: update SAMPLER_BORDER_COLOR_STATE for Gen8
Chia-I Wu [Mon, 26 Jan 2015 07:35:14 +0000 (15:35 +0800)]
ilo: update depth clear value for Gen8
Chia-I Wu [Tue, 27 Jan 2015 08:34:45 +0000 (16:34 +0800)]
ilo: update ilo_zs_surface for Gen8
Chia-I Wu [Tue, 27 Jan 2015 06:58:32 +0000 (14:58 +0800)]
ilo: update ilo_view_surface for Gen8
Chia-I Wu [Sun, 25 Jan 2015 07:12:52 +0000 (15:12 +0800)]
ilo: update texture layout for Gen8
Chia-I Wu [Sun, 25 Jan 2015 10:20:43 +0000 (18:20 +0800)]
ilo: update ilo_blend_state and related functions for Gen8
Chia-I Wu [Mon, 26 Jan 2015 07:28:15 +0000 (15:28 +0800)]
ilo: update ilo_dsa_state and related functions for Gen8
Chia-I Wu [Mon, 26 Jan 2015 05:34:51 +0000 (13:34 +0800)]
ilo: update multisample related states for Gen8
Chia-I Wu [Mon, 26 Jan 2015 10:06:00 +0000 (18:06 +0800)]
ilo: update WM and PS related functions for Gen8
Chia-I Wu [Mon, 26 Jan 2015 16:08:48 +0000 (00:08 +0800)]
ilo: update SBE related functions for Gen8
Chia-I Wu [Mon, 26 Jan 2015 15:12:55 +0000 (23:12 +0800)]
ilo: update SF related functions for Gen8
Chia-I Wu [Tue, 27 Jan 2015 11:57:40 +0000 (19:57 +0800)]
ilo: update CLIP related functions for Gen8
Chia-I Wu [Mon, 26 Jan 2015 08:23:29 +0000 (16:23 +0800)]
ilo: update SF_CLIP_VIEWPORT for Gen8
Chia-I Wu [Mon, 26 Jan 2015 08:37:38 +0000 (16:37 +0800)]
ilo: update streamout related functions for Gen8
Chia-I Wu [Mon, 26 Jan 2015 08:08:23 +0000 (16:08 +0800)]
ilo: update 3DSTATE_{DS,HS,GS} for Gen8
Chia-I Wu [Mon, 26 Jan 2015 07:51:41 +0000 (15:51 +0800)]
ilo: update 3DSTATE_CONSTANT_x for Gen8
Chia-I Wu [Tue, 27 Jan 2015 16:20:09 +0000 (00:20 +0800)]
ilo: update 3DSTATE_URB_x for Gen8
Chia-I Wu [Tue, 27 Jan 2015 16:07:15 +0000 (00:07 +0800)]
ilo: update 3DSTATE_PUSH_CONSTANT_ALLOC_x for Gen8
Chia-I Wu [Mon, 26 Jan 2015 07:34:34 +0000 (15:34 +0800)]
ilo: update render engine common helpers for Gen8
Chia-I Wu [Sun, 25 Jan 2015 08:19:14 +0000 (16:19 +0800)]
ilo: update BLT helpers for Gen8
Chia-I Wu [Sun, 25 Jan 2015 07:25:33 +0000 (15:25 +0800)]
ilo: update MI helpers for Gen8
Chia-I Wu [Sun, 25 Jan 2015 10:04:25 +0000 (18:04 +0800)]
ilo: add functions for Gen8 relocs
Extend ilo_builder_writer_reloc() for Gen8 memory addressing. Add new
wrappers, ilo_builder_surface_reloc64(() and ilo_builder_batch_reloc64().
Chia-I Wu [Fri, 23 Jan 2015 17:12:04 +0000 (01:12 +0800)]
ilo: update the toy compiler for Gen8
Based on what we know from the classic driver.
Chia-I Wu [Fri, 23 Jan 2015 07:44:53 +0000 (15:44 +0800)]
ilo: update genhw headers
Accumulated changes for various renames and additions, including Gen8
definitions. Some of the dynamic state __SIZE no longer means the size of an
element, but the size of an array of elements. The changes can be seen in
ilo_render_dynamic.c.
Chia-I Wu [Mon, 26 Jan 2015 06:58:16 +0000 (14:58 +0800)]
ilo: clean up ilo_gpe_init_dsa()
Add dsa_get_stencil_enable_gen6(), dsa_get_depth_enable_gen6(), and
dsa_get_alpha_enable_gen6() to be called from ilo_gpe_init_dsa().
Chia-I Wu [Sun, 25 Jan 2015 17:08:31 +0000 (01:08 +0800)]
ilo: clean up ilo_gpe_init_blend()
Make ilo_blend_state more space efficient and forward-looking.
Chia-I Wu [Mon, 26 Jan 2015 06:00:25 +0000 (14:00 +0800)]
ilo: clean up sample patterns
Use signed int for sample positions and add helpers to access them. Call them
patterns instead of positions.
Matt Turner [Fri, 30 Jan 2015 21:42:19 +0000 (13:42 -0800)]
glsl: Optimize (f2i(trunc x)) into (f2i x).
total instructions in shared programs: 5950326 -> 5949286 (-0.02%)
instructions in affected programs: 88264 -> 87224 (-1.18%)
helped: 692
Matt Turner [Wed, 28 Jan 2015 18:09:14 +0000 (10:09 -0800)]
glsl: Optimize round-half-up pattern.
Hurts some Psychonauts shaders, but after the next patch (which this
enables) they're fewer instructions than before this patch.
Matt Turner [Fri, 30 Jan 2015 21:50:28 +0000 (13:50 -0800)]
glsl: Add trunc() to ir_builder.
Matt Turner [Sat, 24 Jan 2015 05:58:51 +0000 (21:58 -0800)]
i965: Add LINTERP/CINTERP to can_do_cmod().
LINTERP is implemented as a PLN instruction or a LINE+MAC. PLN and MAC
can do conditional mod. CINTERP is just a MOV.
total instructions in shared programs: 5952103 -> 5950284 (-0.03%)
instructions in affected programs: 324573 -> 322754 (-0.56%)
helped: 1819
We lose the SIMD16 in one Unigine Heaven shader which appears six times
in shader-db.
Matt Turner [Wed, 11 Feb 2015 02:45:18 +0000 (18:45 -0800)]
program: Remove _mesa_nop_vertex_program/_mesa_nop_fragment_program.
Dead since
commit
284ce20901b0c2cfab1d952cc129b8f3cd068f12
Author: Eric Anholt <eric@anholt.net>
Date: Fri Aug 20 10:52:14 2010 -0700
Remove remnants of the old glsl compiler.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 11 Feb 2015 05:43:32 +0000 (21:43 -0800)]
nir: Recognize open-coded fmin/fmax.
And unfortunately other shaders do the same thing but with >=/<= which
we can't apply this optimization to because of NaNs.
instructions in affected programs: 23309 -> 22938 (-1.59%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Sat, 7 Feb 2015 01:12:59 +0000 (17:12 -0800)]
nir: Add algebraic opt for int comparisons with identical operands.
No change on shader-db on i965.
v2: Reword the comment due to feedback from Erik Faye-Lund
Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v1)
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> (v1)