Jose Fonseca [Thu, 2 Apr 2015 10:25:06 +0000 (11:25 +0100)]
glx: Include util/macros.h instead of redefining PRINTFLIKE.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Thu, 2 Apr 2015 10:24:26 +0000 (11:24 +0100)]
util/ralloc: Fix `extern "C"` usage.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jose Fonseca [Thu, 2 Apr 2015 09:09:38 +0000 (10:09 +0100)]
mesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.
I'm not sure what was the original intention, but currently
USE_EXTERNAL_DXTN_LIB always ends up defined, one way or another.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Emil Velikov [Sun, 12 Apr 2015 22:16:42 +0000 (23:16 +0100)]
docs: add news item and link release notes for mesa 10.5.3
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Sun, 12 Apr 2015 22:10:42 +0000 (23:10 +0100)]
docs: Add 256 sums for the 10.5.3 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
65776421fe59a0ffd5388c0968c9b0b1c1b230ed)
Emil Velikov [Sun, 12 Apr 2015 21:29:06 +0000 (22:29 +0100)]
Add release notes for the 10.5.3 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
c4b8bff6e24c6661a8a05ec05f8ed5762e95021b)
Emil Velikov [Thu, 2 Apr 2015 08:37:12 +0000 (08:37 +0000)]
docs: remove the --with-max-{width,height} note
Missed out with commit
d99135b2e9b(configure: nuke
--with-max-{width,height})
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Emil Velikov [Wed, 1 Apr 2015 16:46:09 +0000 (17:46 +0100)]
configure.ac: remove deprecated --with-libclc-path
The option was deprecated with commit
959e83d6507(clover: Adapt libclc's
INCLUDEDIR and LIBEXECDIR to make use of the new introduced libclc.pc.)
back in 2012 with mesa 9.2.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Kenneth Graunke [Sat, 24 Jan 2015 10:05:56 +0000 (02:05 -0800)]
i965/nir: Make INTEL_DEBUG=ann work with NIR.
Now that we store a copy of the NIR shader, and don't immediately free
it, we can use it in annotations as well.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:15:09 +0000 (15:15 -0700)]
i965: Create NIR during LinkShader() and ProgramStringNotify().
Previously, we translated into NIR and did all the optimizations and
lowering as part of running fs_visitor. This meant that we did all of
that work twice for fragment shaders - once for SIMD8, and again for
SIMD16. We also had to redo it every time we hit a state based
recompile.
We now generate NIR once at link time. ARB programs don't have linking,
so we instead generate it at ProgramStringNotify time.
Mesa's fixed function vertex program handling doesn't bother to inform
the driver about new programs at all (which is rather mean), so we
generate NIR at the last minute, if it hasn't happened already.
shader-db runs ~9.4% faster on my i7-5600U, with a release build.
v2: Check NirOptions != NULL in ProgramStringNotify(). Don't bother
using _mesa_program_enum_to_shader_stage as we already know it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Wed, 8 Apr 2015 00:13:45 +0000 (17:13 -0700)]
nir: Store num_direct_uniforms in the nir_shader.
Storing this here is pretty sketchy - I don't know if any driver other
than i965 will want to use it. But this will make it a lot easier to
generate NIR code at link time. We'll probably rework it anyway.
(Ian suggested making nir_assign_var_locations_scalar_direct_first
simply modify the nir_shader's fields, rather than passing pointers
to them. If this stays long term, we should do that. But Jason and
I suspect we'll be reworking this area again in the near future.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:05:12 +0000 (15:05 -0700)]
i965: Move lower_output_reads to brw_link_shader().
This makes it so emit_nir_code() doesn't modify the GLSL IR.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Sat, 11 Apr 2015 17:11:13 +0000 (10:11 -0700)]
glsl: Mark path as unreachable.
Matt Turner [Sat, 11 Apr 2015 16:54:38 +0000 (09:54 -0700)]
i965: Remove useless null check.
If it were null, we'd have just derefernced it two lines above.
Matt Turner [Sat, 11 Apr 2015 16:49:36 +0000 (09:49 -0700)]
i965/fs/nir: Mark fallthrough.
Matt Turner [Sat, 11 Apr 2015 16:47:39 +0000 (09:47 -0700)]
i965: Remove useless reg_offset >= 0 tests.
Commit
eb9bd3a1 changed the type of this field to uint16_t.
Rob Clark [Sat, 11 Apr 2015 14:04:50 +0000 (10:04 -0400)]
freedreno/ir3/nir: couple little fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 10 Apr 2015 19:57:29 +0000 (15:57 -0400)]
freedreno/ir3/nir: handle system values
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 10 Apr 2015 00:32:14 +0000 (20:32 -0400)]
freedreno/ir3/nir: handle txs and query_levels tex ops
These correspond to the tgsi TXQ opcode
(plus sneak in a fix for two-sided color)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 9 Apr 2015 20:44:38 +0000 (16:44 -0400)]
freedreno/ir3/nir: split out tex helpers
We'll need these in one or two other spots.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 9 Apr 2015 16:55:49 +0000 (12:55 -0400)]
freedreno/ir3/nir: simplify emit_tex()
Just build up arrays for src0/src1, and use create_collect()..
Also add back missing .3d flag for 3d/cube textures.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 8 Apr 2015 18:10:00 +0000 (14:10 -0400)]
freedreno/ir3/cp: handle indirect properly
I noticed some cases where we where trying to copy-propagate indirect
src's into places they cannot go, like 2nd src for cat3 (mad, etc).
Expand out valid_flags() to be aware of relativ flag, and fix up a few
related spots.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 8 Apr 2015 15:04:37 +0000 (11:04 -0400)]
freedreno/ir3/sched: avoid getting stuck on addr conflicts
When we get in a scenario where we cannot schedule any more instructions
due to address register conflict, clone the instruction that writes the
address register, and switch the remaining unscheduled users for the
current address register over to the new clone.
This is simpler and more robust than the previous attempt (which tried
and sometimes failed to ensure all other dependencies of users of the
address register were scheduled first).. hint it would try to schedule
instructions that were not actually needed for any output value.
We probably need to do the same with predicate register, although so far
it isn't so heavily used so we aren't running into problems with it
(yet).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 8 Apr 2015 00:41:48 +0000 (20:41 -0400)]
freedreno/ir3/nir: add variable-indexing support
A bit fugly.. try and make this cleaner.. note if we hoist all the
get_addr() out of the loop we can drop the hashtable and just use
create_addr()..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 6 Apr 2015 15:42:57 +0000 (11:42 -0400)]
freedreno/ir3/asm: change assert to warning
It probably *should* be an assert, but for now TGSI f/e isn't very good
about dealing w/ CONST vs ABS/NEG. So for debug builds, print a warning
instead of crashing with an assert for now.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 6 Apr 2015 14:54:30 +0000 (10:54 -0400)]
freedreno/ir3/nir: set first_driver_param
Without this, a3xx breaks.. a4xx would too if it had already implemented
support for passing driver params.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 6 Apr 2015 14:48:11 +0000 (10:48 -0400)]
freedreno/ir3/cp: support to swap mad src's
For a normal MAD (ie. not MADSH), if first source is gpr and second
source is const, we can swap the first two sources to avoid needing a
mov instruction.
This gives back the biggest advantage TGSI f/e had over NIR f/e for
common shaders, since TGSI f/e had this logic in the f/e. Note that
doing this in copy-prop step has the advantage that it will also work
for cases like:
MOV TEMP[b], CONST[x]
MAD TEMP[d], TEMP[a], TEMP[b], TEMP[c]
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 10 Apr 2015 20:39:30 +0000 (16:39 -0400)]
nir: fix bit of cargo-culting in lower_idiv
I guess I was looking too much at how lower_system_values worked when
writing lower_idiv.
Since ttn wasn't emitting load_var for sysvals and the only drivers
using lower_idiv were using ttn, I think nothing was broken as a result.
But might as well fix this before it becomes a problem.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Rob Clark [Sat, 4 Apr 2015 12:13:44 +0000 (08:13 -0400)]
nir: split out lower_sub from lower_negate
Originally you had to have one or the other. But actually I don't want
either. (Or rather I want whatever is the minimum # of instructions.)
TODO: not sure where the best place to insert a check that driver hasn't
set *both* lower_negate and lower_sub?
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 10 Apr 2015 19:01:16 +0000 (15:01 -0400)]
gallium/ttn: add support for system values
So far just the system values that freedreno supports, so we may add
more later.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Fri, 10 Apr 2015 18:19:22 +0000 (14:19 -0400)]
gallium/ttn: fix TXD
With TXD we also have the ddx/ddy sources (before the sampler).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Thu, 9 Apr 2015 19:41:31 +0000 (15:41 -0400)]
gallium/ttn: add TXQ support (v2)
Split out from ttn_tex() since it is kind of a weird instruction that
maps to two NIR opcodes, and it was cleaner this way.
v2: query_levels doesn't take any args
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Thu, 9 Apr 2015 19:16:17 +0000 (15:16 -0400)]
gallium/ttn: split out helper to get texture info
We'll need this as well for TXQ. Split this out first to reduce noise
in the next patch.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Tue, 7 Apr 2015 15:38:23 +0000 (11:38 -0400)]
gallium/ttn: add support for temp arrays
Since the rest of NIR really would rather have these as variables rather
than registers, create a nir_variable per array. But rather than
completely re-arrange ttn to be variable based rather than register
based, keep the registers. In the cases where there is a matching var
for the reg, ttn_emit_instruction will append the appropriate intrinsic
to get things back from the shadow reg into the variable.
NOTE: this doesn't quite handle TEMP[ADDR[]] when the DCL doesn't give
an array id. But those just kinda suck, and should really go away.
AFAICT we don't get those from glsl. Might be an issue for some other
state tracker.
v2: rework to use load_var/store_var with deref chains
v3: create new "burner" reg for temporarily holding the (potentially
writemask'd) dest after each instruction; add load_var to initialize
temporary dest in case not all components are overwritten
v4: review comments: asserts and use ttn_src_for_indirect() in
ttn_array_deref() so we can drop later patch converting to use vec1 for
addr reg (since ttn_src_for_indirect() handles the imov to vec1 from
tgsi addr component that we want)
v5: rebase: new requirements about parent mem ctx for derefs
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Wed, 8 Apr 2015 17:17:30 +0000 (13:17 -0400)]
gallium/ttn: minor cleanup
Extract tgsi_dst->Index into a local.. split out from 'gallium/ttn: add
support for temp arrays' for noise reduction..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Jason Ekstrand [Fri, 10 Apr 2015 23:24:11 +0000 (16:24 -0700)]
i965: Use NIR by default for fragment shaders
GLSL IR vs. NIR shader-db results on i965:
total instructions in shared programs: 2889747 -> 2890782 (0.04%)
instructions in affected programs: 2425446 -> 2426481 (0.04%)
helped: 3698
HURT: 5341
GLSL IR vs. NIR shader-db results on g4x:
total instructions in shared programs: 2547252 -> 2550440 (0.13%)
instructions in affected programs: 1984482 -> 1987670 (0.16%)
helped: 2844
HURT: 4776
GLSL IR vs. NIR shader-db results on Iron Lake:
total instructions in shared programs: 4053381 -> 4063828 (0.26%)
instructions in affected programs: 3026601 -> 3037048 (0.35%)
helped: 4110
HURT: 8331
GAINED: 1287
LOST: 9
GLSL IR vs. NIR shader-db results on Sandy Bridge:
total instructions in shared programs: 5307041 -> 5236666 (-1.33%)
instructions in affected programs: 3442908 -> 3372533 (-2.04%)
helped: 11829
HURT: 5604
GAINED: 33
LOST: 18
GLSL IR vs. NIR shader-db results on Ivy Bridge:
total instructions in shared programs: 4926333 -> 4857017 (-1.41%)
instructions in affected programs: 3144042 -> 3074726 (-2.20%)
helped: 11559
HURT: 4774
GAINED: 46
LOST: 25
GLSL IR vs. NIR shader-db results on Bay Trail:
total instructions in shared programs: 4926333 -> 4857017 (-1.41%)
instructions in affected programs: 3144042 -> 3074726 (-2.20%)
helped: 11559
HURT: 4774
GAINED: 46
LOST: 25
GLSL IR vs. NIR shader-db results on Haswell:
total instructions in shared programs: 4392487 -> 4293476 (-2.25%)
instructions in affected programs: 2800180 -> 2701169 (-3.54%)
helped: 13073
HURT: 3383
GAINED: 46
LOST: 23
GLSL IR vs. NIR shader-db results on Broadwell (FS only):
total instructions in shared programs: 4378113 -> 4283025 (-2.17%)
instructions in affected programs: 2743209 -> 2648121 (-3.47%)
helped: 12470
HURT: 3609
GAINED: 64
LOST: 27
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Fri, 10 Apr 2015 06:26:49 +0000 (23:26 -0700)]
i965: Don't set NirOptions for stages that will use the vec4 backend.
We've started using NirOptions != NULL to mean "we're using NIR for this
stage." However, when INTEL_USE_NIR=1, we set it for a bunch of stages
that still use the vec4 backend, and thus definitely aren't using NIR.
For example, if INTEL_USE_NIR=1 we disable the GLSL IR cubemap
normalization pass, even for vertex shaders and geometry shaders. This
is wrong, but breaks a very uncommon case.
When I started deleting GLSL IR for stages where we claimed to be using
NIR, this bug quickly became apparent.
For now, only set it for fragment shaders, and vertex shaders if
brw->scalar_vs is set.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Nick Sarnie [Fri, 10 Apr 2015 16:45:57 +0000 (12:45 -0400)]
gallivm: Fix build since llvm-3.7.0svn r234495
Revert
50e9fa2ed69cb5f76f66231976ea789c0091a64d as LLVM reverted their
change.
Signed-off-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Ville Syrjälä [Tue, 31 Mar 2015 12:01:24 +0000 (15:01 +0300)]
i965/disasm: Print the type after the swizzle also for 3src src operands
The disassembly currently has the swizzle after the type for 3src source
operands, and the other way around for 2src. Flip the type and swizzle
around for 3src so that the output matches 2src.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 23:28:10 +0000 (16:28 -0700)]
i965: Move brw_link_shader's GLSL IR transformations into a helper.
This function was getting a bit large and unwieldy.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 23:29:32 +0000 (16:29 -0700)]
i965: Change brw_shader to gl_shader in brw_link_shader().
Nothing actually wanted brw_shader fields - we just had to type
shader->base all over the place for no reason.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:50:54 +0000 (15:50 -0700)]
nir: Constify nir_lower_sampler's gl_shader_program pointer.
Now that we're not generating linker errors, we don't actually modify
this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:46:56 +0000 (15:46 -0700)]
nir: Remove linker_error calls from nir_lower_samplers().
These should never happen. Plus, NIR passes really shouldn't be
reporting linker errors - this is past link time.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:14:16 +0000 (15:14 -0700)]
nir: Make nir_lower_samplers take a gl_shader_stage, not a gl_program *.
We don't actually need a gl_program struct. We only used it to
translate prog->Target (i.e. GL_VERTEX_PROGRAM) to the gl_shader_stage
(i.e. MESA_SHADER_VERTEX). We may as well just pass that.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:18:43 +0000 (15:18 -0700)]
nir: Move gl_shader_stage enum from mtypes.h to shader_enums.h.
I want to use this in some code that doesn't currently include mtypes.h.
It seems like a better place for it anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:16:51 +0000 (15:16 -0700)]
nir: Fix #include guards in shader_enums.h.
This header was originally going to be called pipeline.h, but it got
renamed at the last minute. Make the include guards match.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:07:33 +0000 (15:07 -0700)]
nir: Constify prog_to_nir's gl_program pointer.
prog_to_nir should not modify the incoming Mesa IR program - just
translate it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Vinson Lee [Thu, 9 Apr 2015 05:51:57 +0000 (22:51 -0700)]
gallivm: Fix build since llvm-3.7.0svn r234460.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89963
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Roland Scheidegger [Sat, 4 Apr 2015 14:49:08 +0000 (16:49 +0200)]
draw: (trivial) don't print the shader twice with GALLIVM_DEBUG=tgsi (or ir)
Neither the shader nor the key change when doing elts or linear variant, so
this was just annoying (probably mildly useful at some point when we printed
the IR per function too).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Wed, 8 Apr 2015 22:49:11 +0000 (00:49 +0200)]
gallivm: don't use control flow when doing indirect constant buffer lookups
llvm goes crazy when doing that, using way more memory and time, though there's
probably more to it - this points to a very much similar issue as fixed in
8a9f5ecdb116d0449d63f7b94efbfa8b205d826f. In any case I've seen a quite
plain looking vertex shader with just ~50 simple tgsi instructions (but with a
dozen or so such indirect constant buffer lookups) go from a terribly high
~440ms compile time (consuming 25MB of memory in the process) down to a still
awful ~230ms and 13MB with this fix (with llvm 3.3), so there's still obvious
improvements possible (but I have no clue why it's so slow...).
The resulting shader is most likely also faster (certainly seemed so though
I don't have any hard numbers as it may have been influenced by compile times)
since generally fetching constants outside the buffer range is most likely an
app error (that is we expect all indices to be valid).
It is possible this fixes some mysterious vertex shader slowdowns we've seen
ever since we are conforming to newer apis at least partially (the main draw
loop also has similar looking conditionals which we probably could do without -
if not for the fetch at least for the additional elts condition.)
v2: use static vars for the fake bufs, minor code cleanups
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Wed, 1 Apr 2015 20:36:09 +0000 (14:36 -0600)]
glsl: check for forced_language_version in is_version()
This is a follow-on fix from the earlier "glsl: allow ForceGLSLVersion
to override #version directives" change. Since we're not changing
the language_version field, we have to check forced_language_version
here.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Neil Roberts [Fri, 6 Mar 2015 19:11:19 +0000 (19:11 +0000)]
i965/skl: Fix the order of the arguments for the LD sampler message
In Skylake the order of the arguments for sample messages with the LD
type are u, v, lod, r whereas previously they were u, lod, v, r.
This fixes 144 Piglit tests including ones that directly use
texelFetch and also some using the meta stencil blit path which
appears to use texelFetch in its shader.
v2: Fix sampling 1D textures
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Zhenyu Wang [Tue, 7 Apr 2015 05:48:38 +0000 (13:48 +0800)]
i965: Fix depth field setting in surface state for raw buffer on Gen7/8
On Gen7/8 for RAW surface format, the depth field (surf[3]) in surface
state means [30:21] bits of number of entries which is different from
other surface format which uses [26:21] bits field.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Dave Airlie [Wed, 8 Apr 2015 00:31:14 +0000 (10:31 +1000)]
u_tile: fix warnings about incompatible casts.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Glenn Kennard [Tue, 7 Apr 2015 01:00:20 +0000 (03:00 +0200)]
r600g/sb: Enable SB for geometry shaders
Add SV_GEOMETRY_EMIT special variable type to track the
implicit dependencies between CUT/EMIT_VERTEX/MEM_RING
instructions so GCM/scheduler doesn't reorder them.
Mark emit instructions as unkillable so DCE doesn't eat them.
Enable only for evergreen/cayman as there are a few
unexplained GS piglit regressions on R6xx/R7xx with SB
enabled otherwise.
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Glenn Kennard [Thu, 26 Mar 2015 01:56:50 +0000 (02:56 +0100)]
r600g/sb: Update last_cf for loops
CF_END could end up emitted in the middle of a shader on cayman
when there was a loop at the very end.
Fixes glsl-1.50-geometry-end-primitive and
ext_transform_feedback-geometry-shaders-basic piglit tests.
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 6 Apr 2015 23:52:41 +0000 (09:52 +1000)]
u_tile: fix stencil texturing tests under softpipe
arb_stencil_texturing-draw failed under softpipe because we got a float
back from the texturing function, and then tried to U2F it, stencil
texturing returns ints, so we should fix the tiling to retrieve
the stencil values as integers not floats.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Tue, 7 Apr 2015 19:33:17 +0000 (12:33 -0700)]
nir: Make nir_*_instr_create take a nir_shader instead of a void * context
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Sat, 28 Mar 2015 02:50:29 +0000 (19:50 -0700)]
nir: Implement a nir_sweep() pass.
This pass performs a mark and sweep pass over a nir_shader's associated
memory - anything still connected to the program will be kept, and any
dead memory we dropped on the floor will be freed.
The expectation is that this will be called when finished building and
optimizing the shader. However, it's also fine to call it earlier, and
many times, to free up memory earlier.
v2: (feedback from Jason Ekstrand)
- Skip sweeping impl->start_block, as it's already in the CF list.
- Don't sweep SSA defs (they're owned by their defining instruction)
- Don't steal phi sources (they're owned by nir_phi_instr).
- Don't steal tex->src (it's owned by the tex_inst itself)
- Don't sweep dereference chains (top-level dereferences are owned by
the instruction; sub-dereferences are owned by the parent deref).
- Don't sweep sources and destinations (SSA defs are handled as part of
the defining instruction, and registers are handled as part of
function implementations).
- Just steal instructions; don't walk them (no longer required).
v3: (feedback from Jason Ekstrand)
- Steal indirect sources from nir_src/nir_dest.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Fri, 3 Apr 2015 04:24:38 +0000 (21:24 -0700)]
nir: Allocate dereferences out of their parent instruction or deref.
Jason pointed out that variable dereferences in NIR are really part of
their parent instruction, and should have the same lifetime.
Unlike in GLSL IR, they're not used very often - just for intrinsic
variables, call parameters & return, and indirect samplers for
texturing. Also, nir_deref_var is the top-level concept, and
nir_deref_array/nir_deref_record are child nodes.
This patch attempts to allocate nir_deref_vars out of their parent
instruction, and any sub-dereferences out of their parent deref.
It enforces these restrictions in the validator as well.
This means that freeing an instruction should free its associated
dereference chain as well. The memory sweeper pass can also happily
ignore them.
v2: Rename make_deref to evaluate_deref and make it take a nir_instr *
instead of void *. This involves adding &instr->instr everywhere.
(Requested by Jason Ekstrand.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Sat, 28 Mar 2015 17:02:17 +0000 (10:02 -0700)]
nir: Allocate nir_ssa_def::uses/if_uses out of the instruction.
We can't allocate them out of the nir_ssa_def itself, because it may not
be ralloc'd (for example, nir_dest embeds a nir_ssa_def).
However, allocating them out of the instruction should work.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Thu, 2 Apr 2015 23:15:11 +0000 (16:15 -0700)]
nir: Allocate nir_phi_src values out of the nir_phi_instr.
Phi sources are part of the phi instruction and should have the same
lifetime.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 07:32:55 +0000 (00:32 -0700)]
nir: Allocate nir_call_instr::params out of the nir_call itself.
The lifetime of the params array needs to be match the nir_call_instr
itself. So, allocate it using the instruction itself as the context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Sun, 29 Mar 2015 10:45:16 +0000 (03:45 -0700)]
i965: Add the ability to render to I8/L8 and I16/L16 UNORM formats.
This allows those formats to work with the meta PBO upload path.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Mon, 6 Apr 2015 23:09:35 +0000 (16:09 -0700)]
i965: Use SET_FIELD in 3DSTATE_STREAMOUT packets.
Suggested by Topi Pohjolainen.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jason Ekstrand [Tue, 7 Apr 2015 04:04:42 +0000 (21:04 -0700)]
nir/lower_tex_projector: Don't use designated initializers
These don't work in MSVC or in older versions of GCC
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89899
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Tapani Pälli [Thu, 2 Apr 2015 09:59:55 +0000 (12:59 +0300)]
glsl: relax input->output validation for SSO programs
Commit 18004c3 introduced more restrictive validation to linker
between inputs and outputs. This patch skips the additional check
for programs that utilize GL_ARB_separate_shader_objects, there
inputs and outputs might not make exact match during linking but
only when constructing the final pipeline.
This made some of the GL_ARB_program_interface_query tests shaders
fail to link, these tests can be used to verify the change.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ilia Mirkin [Sun, 5 Apr 2015 21:40:44 +0000 (17:40 -0400)]
nv50,nvc0: limit the y-tiling of 3d textures to the first level's tiling
We limit y-tiling to 0x20 when depth is involved. However the function is
run for each miplevel, and the hardware expects miplevel 0 to have the
highest tiling settings. Perform the y-tiling limit on all levels of a
3d texture, not just the ones that have depth.
Fixes:
texelFetch fs sampler3D 98x129x1-98x129x9
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Nick Tenney <nick.tenney@gmail.com> # GT216
Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>
Dave Airlie [Tue, 31 Mar 2015 05:18:47 +0000 (15:18 +1000)]
r600g: fix op3 abs issue
This code to handle absolute values on op3 srcs was a bit too simple,
it really needs a temp reg per src, not one per channel, make it
easier and let sb clean up the mess.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89831
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Iago Toral Quiroga [Mon, 9 Mar 2015 14:17:03 +0000 (15:17 +0100)]
i965: Do not render primitives in non-zero streams then TF is disabled
Haswell hardware seems to ignore Render Stream Select bits from
3DSTATE_STREAMOUT packet when the SOL stage is disabled even if
the PRM says otherwise. Because of this, all primitives are sent
down the pipeline for rasterization, which is wrong. If SOL is
enabled, Render Stream Select is honored and primitives bound to
non-zero streams are discarded after stream output.
Since the only purpose of primives sent to non-zero streams is to
be recorded by transform feedback, we can simply discard all geometry
bound to non-zero streams then transform feedback is disabled
to prevent it from ever reaching the rasterization stage.
Notice that this patch introduces a small change in the behavior we
get when a geometry shader emits more vertices than the maximum declared:
before, a vertex that was emitted to a non-zero stream when TF was
disabled would still count for the purposes of checking that we don't
exceed the maximum number of output vertices declared by the shader. With
this change, these vertices are completely ignored and won't increase
the output vertex count, making more room for other (hopefully more
useful) vertices.
Fixes piglit test arb_gpu_shader5-emitstreamvertex_nodraw on Haswell
and Broadwell.
v2 (Ken): Drop is_haswell check in favor of doing this unconditionally.
Broadwell needs the workaround as well, and it doesn't hurt to do it in
general. Also tweak comments - the Haswell PRM does actually mention
this ("Command Reference: Instructions" page 797).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83962
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Fri, 27 Mar 2015 00:21:10 +0000 (17:21 -0700)]
i965: Add forgotten multi-stream code to Gen8 SOL state.
Fixes Piglit's arb_gpu_shader5-xfb-streams-without-invocations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Sat, 4 Apr 2015 09:00:52 +0000 (02:00 -0700)]
i965: Fix instanced geometry shaders on Gen8+.
Jordan added this in commit
741782b5948bb3d01d699f062a37513c2e73b076 for
Gen7 platforms. I missed this when adding the Broadwell code.
Fixes Piglit's spec/arb_gpu_shader5/invocation-id-{basic,in-separate-gs}
with MESA_EXTENSION_OVERRIDE=GL_ARB_gpu_shader5 set.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Thu, 2 Apr 2015 07:55:45 +0000 (00:55 -0700)]
i965: Free dead GLSL IR one last time.
While working on NIR's memory allocation model, I realized the GLSL IR
memory model was broken.
During glCompileShader, we allocate everything out of the
_mesa_glsl_parse_state context, and reparent it to gl_shader at the end.
During glLinkProgram, we allocate everything out of a temporary context,
then reparent it to the exec_list containing the linked IR.
But during brw_link_shader - the driver's final opportunity to do
lowering and optimization - we just allocated everything out of the
permanent context given to us by the linker. That memory stayed
forever.
Notably, passes like brw_fs_channel_expressions cause us to churn the
majority of the code, so we really want to free dead IR here.
Saves 125MB of memory when replaying a Dota 2 trace on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Fri, 20 Feb 2015 23:11:49 +0000 (15:11 -0800)]
i965: Implement SIMD16 texturing on Gen4.
This allows SIMD16 mode to work for a lot more programs. Texturing is
also more efficient in SIMD16 mode than SIMD8. Several messages don't
actually exist in SIMD8 mode, so we did SIMD16 messages and threw away
half of the data. Now we compute real data in both halves.
Also, the SIMD16 "sample" message doesn't require all three coordinate
components to exist (like the SIMD8 one), so we can shorten the message
lengths, cutting register usage a bit.
I chose to implement the visitor functionality in a separate function,
since mixing true SIMD16 with SIMD8 code that uses SIMD16 fallbacks
seemed like a mess. The new code bails on a few cases where we'd
have to do two SIMD8 messages - we just fall back to SIMD8 for now.
Improves performance in "Shadowrun: Dragonfall - Director's Cut" by
about 20% on GM45 (measured with LIBGL_SHOW_FPS=1 while standing around
in the first mission).
v2: Add ir_txf to the has_lod case (caught by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Fri, 20 Feb 2015 22:09:17 +0000 (14:09 -0800)]
i965: Use SIMD16 instead of SIMD8 on Gen4 when possible.
Gen5+ systems allow you to specify multiple shader programs - both SIMD8
and SIMD16 - and the hardware will automatically dispatch to the most
appropriate one, given the number of subspans to be processed.
However, that is not the case on Gen4. Instead, you program a single
shader. If you enable multiple dispatch modes (SIMD8 and SIMD16), the
shader is supposed to contain a series of jump instructions at the
beginning. The hardware will launch the shader at a small offset,
hitting one of the jumps.
We've always thought that sounds like a pain, and weren't clear how it
affected performance - is it worth having multiple shader types? So,
we never bothered with SIMD16 until now.
This patch takes a simpler approach: try and compile a SIMD16 shader.
If possible, set the no_8 flag, telling the hardware to just use the
SIMD16 variant all the time.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Sat, 10 Jan 2015 21:31:48 +0000 (13:31 -0800)]
i965: Respect the no_8 flag on Gen4-5.
This flag means to ignore the SIMD8 program and only use the SIMD16 one.
It was originally meant for repdata clear shaders, but I plan to use it
for other things on Gen4 as well.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Sat, 4 Apr 2015 01:30:57 +0000 (18:30 -0700)]
i965/fp: Set coord_components correctly for cube textures.
I've no idea why this was 4. It certainly seems wrong.
Prevents assertion failures in fp-incomplete-tex with some upcoming
patches of mine.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Ian Romanick [Thu, 26 Mar 2015 00:23:40 +0000 (17:23 -0700)]
glsl/cse: Maintain a list of free ae_entry objects
The CSE algorithm will continuously allocate new ae_entry objects. As
each new basic block is exited, all of the previously allocated objects
are dumped. Instead, put them in a free list and re-use them in the
next basic block. Reduce, reuse, recycle!
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Matt Turner [Thu, 2 Apr 2015 01:25:02 +0000 (18:25 -0700)]
nir: Remove fsin_reduced/fcos_reduced.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Thu, 2 Apr 2015 01:23:58 +0000 (18:23 -0700)]
st/mesa: Remove unused emit_scs().
Was only used by the sin_reduced/cos_reduced cases, which themselves
were impossible to reach.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Thu, 2 Apr 2015 01:22:52 +0000 (18:22 -0700)]
program: Remove unused emit_scs().
Was only used by the sin_reduced/cos_reduced cases, which themselves
were impossible to reach.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Thu, 2 Apr 2015 01:21:41 +0000 (18:21 -0700)]
i965/vec4: Remove emit_scs() prototype.
This has never existed.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Thu, 2 Apr 2015 00:44:16 +0000 (17:44 -0700)]
glsl: Remove never used sin_reduced/cos_reduced.
These were added in commit
f2616e56, presumably in preparation for
translating ARB vp/fp into GLSL IR. That never happened, and neither did
a lowering pass that actually generated these instructions.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 17 Mar 2015 18:12:23 +0000 (19:12 +0100)]
glsl: Update the #line behaviour on GLSL 3.30+ and GLSL ES+
From GLSL 3.30 and GLSL ES 1.00 on, after processing the line
directive (including its new-line), the implementation should
behave as if it is compiling at the line number passed as
argument. In previous versions, it behaved as if compiling
at the passed line number + 1.
Partially fixes https://bugs.freedesktop.org/show_bug.cgi?id=88815
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Antia Puentes [Tue, 17 Mar 2015 18:28:25 +0000 (19:28 +0100)]
glsl: respect the source number set by #line <line> <source>
From GLSL 1.30.10, section 3.3 (Preprocessor):
"#line line source-string-number ... After processing this directive
(including its new-line), the implementation will behave as if it is
compiling at ... source string number source-string-number. Subsequent
source strings will be numbered sequentially, until another #line
directive overrides that numbering."
In the previous implementation the source number was always zero.
Subsequent source strings are still not numbered sequentially, because
in the glShaderSource implementation we are concatenating the source code
strings into one long string.
Partially fixes https://bugs.freedesktop.org/show_bug.cgi?id=88815
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Tue, 3 Feb 2015 11:34:29 +0000 (12:34 +0100)]
i965: Make sure we always mark array surfaces as such
Even if they only have one slice, otherwise textureSize() won't
produce correct results for the depth value.
Fixes 10 dEQP tests in this category:
dEQP-GLES3.functional.shaders.texture_functions.texturesize.sampler2darray*
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
Rob Clark [Thu, 12 Mar 2015 21:18:33 +0000 (17:18 -0400)]
freedreno/ir3: add NIR compiler
The NIR compiler frontend is an alternative to the TGSI f/e, producing
the same ir3 IR and using the same backend passes for scheduling, etc.
It is not enabled by default yet, as there are still some regressions.
To enable, use 'FD_MESA_DEBUG=nir'. It is enough to use with, for
example, xonotic or supertuxkart.
With the NIR f/e, scalarizing and a number of other lowering steps
happen in NIR, so we don't have to do them in ir3. Which simplifies the
f/e and allows the lowered instructions to pass through other
optimization stages.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 4 Mar 2015 01:36:39 +0000 (20:36 -0500)]
freedreno/a3xx: don't decode srgb on mem2gmem
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 4 Apr 2015 06:53:52 +0000 (02:53 -0400)]
freedreno/a3xx: pass sprite coord mode through to program emit
Use the correct sprite replacement depending on the flip of the coord
mode, using either T or 1-T depending on whether we have an upper-left or
lower-left coordinate origin. This fixes all the point sprite piglits.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 31 Mar 2015 15:51:00 +0000 (11:51 -0400)]
freedreno/a3xx: add UBO support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 4 Apr 2015 17:37:45 +0000 (13:37 -0400)]
freedreno/ir3: insert nop between sfu/mem operations
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 4 Apr 2015 02:29:44 +0000 (22:29 -0400)]
freedreno: dirty context when reallocating a bound bo
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 3 Apr 2015 06:15:17 +0000 (02:15 -0400)]
freedreno: keep track of buffer valid ranges
Copies nouveau_buffer and radeon_buffer. This allows a write to proceed
to an uninitialized part of a buffer even when the GPU is using the
previously-initialized portions.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 3 Apr 2015 00:48:44 +0000 (20:48 -0400)]
freedreno: mark resources as being read so that writes flush the queue
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 4 Apr 2015 03:39:38 +0000 (23:39 -0400)]
freedreno: don't bother setting resource timestamps
Waiting on a bo being ready is handled in fd_bo_cpu_prep. No need to
keep separate timestamps around.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 3 Apr 2015 06:25:58 +0000 (02:25 -0400)]
freedreno: add a reading flag to indicate gpu is reading rsc
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 3 Apr 2015 02:28:21 +0000 (22:28 -0400)]
freedreno: fix resource flushing confusion
A resource flush is an upload of a hypothetically-staging texture to the
GPU. For a UMA system, this will largely be a no-op or
cache-maintenance. Move the render flush logic into transfer_map where
it belongs, and clear out the transfer_flush function.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 3 Apr 2015 02:26:03 +0000 (22:26 -0400)]
freedreno: remove tex_resource
pipe_sampler_view already contains a texture, remove the redundant
tex_resource member which pointed at the same thing.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rob Clark [Wed, 1 Apr 2015 16:31:46 +0000 (12:31 -0400)]
freedreno/ir3: handle FRAG IN's without interpolation specified
Fallback to picking based on semantic name.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 1 Apr 2015 14:52:29 +0000 (10:52 -0400)]
freedreno/ir3/cmdline: add @const headers for immediates
Since NIR f/e currently encodes immediates in instructions (rather than
passing via const), we need to ensure that when const's are used the get
initialized to the proper values. Otherwise comparing NIR to TGSI
compiler, it will use proper immediate values in one case, and randomly
initialize values in the other. Which confuses ir3test.
Signed-off-by: Rob Clark <robclark@freedesktop.org>