Marek Olšák [Wed, 10 Aug 2022 00:10:09 +0000 (20:10 -0400)]
radeonsi: simplify radeonsi_zerovram implementation
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Pierre-Eric Pelloux-Prayer [Fri, 9 Sep 2022 13:18:17 +0000 (15:18 +0200)]
egl/wayland: fix glthread crashes
glthread unmarshalling thread cannot run concurrently with code that alloc
the back bo or the code that perform the swaps.
Ensure this by running dri2_flush_drawable_for_swapbuffers early.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Marek Olšák [Wed, 24 Aug 2022 06:21:00 +0000 (02:21 -0400)]
frontend/dri: sync glthread when calling from the app side
The comments explain the reasons.
This is a prerequisite for glthread to be used by native drivers, swrast,
and zink.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Marek Olšák [Tue, 23 Aug 2022 02:28:58 +0000 (22:28 -0400)]
frontend/dri: make the backgroundCallable extension optional
It's only needed by X11/DRI2. This allows glthread to be used by android,
drm, wayland, and device (EGL backend).
This is the only solution to allow the egl/drm backend to work with glthread
without ugly hacks between libgbm and libEGL.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Marek Olšák [Tue, 23 Aug 2022 20:59:18 +0000 (16:59 -0400)]
glthread: work around GL_INVALID_OPERATION with OpenGL ES 1.x draws
GLES1 only has (Multi)Draw{Array,Elements}, but glthread converts them
to the more complicated versions and then calls them through the dispatch,
which generated GL_INVALID_OPERATION.
Luckily, we can export them with the Internal prefix, so they are unlikely
to be used by apps by accident.
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Marek Olšák [Tue, 23 Aug 2022 19:55:35 +0000 (15:55 -0400)]
glthread: fix glGetIntegerv(GL_CLIENT_ACTIVE_TEXTURE)
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Marek Olšák [Tue, 23 Aug 2022 19:41:52 +0000 (15:41 -0400)]
glthread: always sync for glShaderSource because invalid params can crash
If an invalid parameter is received along with an invalid pointer and we
ignore the invalid parameter and dereference the pointer, we crash.
Since we can't fully validate all parameters (such as whether "shader"
is a valid object ID), remove the custom code.
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Marek Olšák [Tue, 23 Aug 2022 19:40:01 +0000 (15:40 -0400)]
glthread: generate errors for glGet functions between glBegin/End
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Marek Olšák [Tue, 23 Aug 2022 19:02:48 +0000 (15:02 -0400)]
glthread: fix draws not compiled into a display list should generate an error
Before it just crashed if indices were invalid.
Cc: stable
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Marek Olšák [Tue, 23 Aug 2022 18:57:56 +0000 (14:57 -0400)]
mesa: fix glDrawRangeElementsBaseVertex should be compiled into display list
It's defined in terms of glDrawRangeElements, which is compiled into display
lists.
Cc: stable
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18223>
Lionel Landwerlin [Tue, 6 Sep 2022 18:18:17 +0000 (21:18 +0300)]
anv: add support for EXT_mutable_descriptor_type
v2: Update docs/features.txt (Tapani)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18688>
Lionel Landwerlin [Tue, 20 Sep 2022 22:20:40 +0000 (01:20 +0300)]
anv: clear descriptorsets if AllocateDescriptorSets fails
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7285
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18719>
Lionel Landwerlin [Tue, 12 Jul 2022 15:58:07 +0000 (18:58 +0300)]
anv: trace xfb queries
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17467>
Lionel Landwerlin [Fri, 1 Jul 2022 07:52:45 +0000 (10:52 +0300)]
intel/utrace: make blorp tracepoints more readable
With the operation name and some formats.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17467>
Lionel Landwerlin [Fri, 1 Jul 2022 07:51:39 +0000 (10:51 +0300)]
blorp: defined operations for debug purposes
We add a mapping for blorp_op -> intel_snapshot
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17467>
Lionel Landwerlin [Fri, 1 Jul 2022 07:49:15 +0000 (10:49 +0300)]
anv: add missing tracepoint
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
3501a3f9ed92 ("anv: Convert to 100% dynamic rendering")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17467>
Georg Lehmann [Sat, 17 Sep 2022 18:52:24 +0000 (20:52 +0200)]
aco: Use v_fmaak/v_fmamk if two operands are the same literal.
Foz-DB Navi21:
Totals from 5744 (4.26% of 134913) affected shaders:
VGPRs: 237128 -> 237056 (-0.03%); split: -0.04%, +0.01%
CodeSize:
16654484 ->
16620668 (-0.20%); split: -0.23%, +0.03%
MaxWaves: 152838 -> 152846 (+0.01%)
Instrs: 3063214 -> 3058572 (-0.15%); split: -0.17%, +0.02%
Latency:
23935195 ->
23934827 (-0.00%); split: -0.03%, +0.03%
InvThroughput: 5478562 -> 5478160 (-0.01%); split: -0.01%, +0.01%
VClause: 60432 -> 60435 (+0.00%); split: -0.02%, +0.03%
SClause: 121032 -> 120896 (-0.11%); split: -0.20%, +0.09%
Copies: 147865 -> 143144 (-3.19%); split: -3.59%, +0.40%
PreSGPRs: 195722 -> 195661 (-0.03%); split: -0.06%, +0.03%
PreVGPRs: 182849 -> 182787 (-0.03%)
Foz-DB Vega10:
Totals from 5290 (3.92% of 135041) affected shaders:
SGPRs: 357952 -> 359616 (+0.46%); split: -0.11%, +0.57%
VGPRs: 204048 -> 203928 (-0.06%); split: -0.08%, +0.02%
CodeSize:
14043176 ->
14003100 (-0.29%); split: -0.29%, +0.00%
MaxWaves: 39401 -> 39398 (-0.01%); split: +0.01%, -0.02%
Instrs: 2636739 -> 2631246 (-0.21%); split: -0.21%, +0.00%
Latency:
25264088 ->
25256482 (-0.03%); split: -0.05%, +0.02%
InvThroughput:
12039643 ->
12039346 (-0.00%); split: -0.00%, +0.00%
VClause: 55603 -> 55584 (-0.03%); split: -0.04%, +0.00%
SClause: 101577 -> 101342 (-0.23%); split: -0.30%, +0.07%
Copies: 213344 -> 207929 (-2.54%); split: -2.58%, +0.05%
Branches: 34053 -> 34054 (+0.00%)
PreSGPRs: 172405 -> 172260 (-0.08%)
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18645>
Danylo Piliaiev [Tue, 20 Sep 2022 16:50:20 +0000 (19:50 +0300)]
tu: Expose Vulkan 1.3
We have all required functionality implemented, and DXVK now requires
Vulkan 1.3.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18709>
Connor Abbott [Fri, 26 Aug 2022 16:09:27 +0000 (18:09 +0200)]
tu: Initial implementation of VK_EXT_graphics_pipeline_library
Now that the state for each pipeline is split into pieces, we can mostly
implement it by stitching together the pieces. One TODO is that we could
do more to split up the pre-rast and FS commands into separate draw
states so that we have to emit less commands when fast linking,
currently we compile the variants but delay emitting the commands until
link time, but note that even the Gallium driver doesn't currently do
this. Given the strict SSO model (e.g. with separate VPC registers for
each stage) it may even be possible to do most of the linking ahead of
time with only a few fixups for corner cases.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Fri, 16 Sep 2022 14:13:31 +0000 (16:13 +0200)]
tu: Abstract driver-specific const state
Right now, we pass around the push constant state in a lot of places,
but we'll want to add other driver-managed constants. Add a struct which
we can add to, and separate out the total driver-reserved constants from
the size of push constants.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Tue, 30 Aug 2022 15:42:30 +0000 (17:42 +0200)]
tu: Use vk_pipeline_shader_stage_to_nir
This will be necessary for graphics pipeline libraries where pipeline
stages can have the SPIR-V inline.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Wed, 24 Aug 2022 16:21:34 +0000 (18:21 +0200)]
tu: Split up prim order computation
With pipeline libraries, computing this might have to be delayed because
it depends on multiple pieces of state and there's no way to disentangle
them. Therefore we have to store the requisite state in the pipeline and
combine it later.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Wed, 24 Aug 2022 13:34:27 +0000 (15:34 +0200)]
tu: Move no_earlyz computation to blend/msaa state
This removes the last dependency of FS outputs on blend/MSAA state.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Wed, 24 Aug 2022 13:00:15 +0000 (15:00 +0200)]
tu: Emit *_OUTPUT_CNTL1 as part of blend state
This further decouples the fragment shader from the blend state.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Wed, 24 Aug 2022 11:56:04 +0000 (13:56 +0200)]
tu, ir3: Determine dual-src blend from shader for FS outputs
The other state in this register comes from the FS, so determine whether
dual-source blending is enabled from the FS too, in order to avoid
entangling FS state and output state that with graphics pipeline library
can be in different pipelines.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Wed, 24 Aug 2022 11:36:44 +0000 (13:36 +0200)]
tu: Don't use output state to compute render components
If there are disabled attachments that are nevertheless written to, they
should already be disabled in the blend state, via the same mechanism as
color_write_enable, so there should be no reason to mix the FS state and
blend state like this. This helps unentangle state that in graphics
pipeline library can be provided in different pipelines.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Mon, 22 Aug 2022 18:59:52 +0000 (20:59 +0200)]
tu, ir3: Move multi_pos_output to ir3_shader_variant
This means it has to be rederived rather than passed from the place
where we actually do the optimization, but it eliminates the clutter of
having to pass it around in turnip, which will only get worse with
graphics pipeline libraries.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Mon, 22 Aug 2022 18:00:12 +0000 (20:00 +0200)]
tu: Don't use layer_zero/view_zero in shader key
Instead force gl_Layer and gl_Viewport to 0 by setting registers.
Using the shader key would be against the spirit of GPL if it lead to
linking needing a recompile.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Mon, 22 Aug 2022 15:45:54 +0000 (17:45 +0200)]
tu: Nuke tu_pipeline_cache
This is just a leftover from the never-finished pipeline cache copied
from another driver, we use vk_pipeline_cache now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Fri, 19 Aug 2022 13:41:23 +0000 (15:41 +0200)]
ir3: Don't use msaa key for a6xx+
In the compiler, this was only used to replace some inputs in the
non-MSAA case which apparently no longer need to be replaced anymore,
probably because we clarified some registers related to them and started
setting them better. In the pipeline libraries case we may not have
access to the sample locations state when compiling the FS (although we
do know whether sample shading is enabled), so this removes a
problematic state dependency in turnip.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Thu, 18 Aug 2022 10:31:34 +0000 (12:31 +0200)]
tu: Split out primtype calculation for tess
With pipeline libraries, we may not know the HW primtype if the user
passes a primtype of PATCHES because the tess shaders and input assembly
state may be in different pipelines. We need to split out the patch
control points and only determine the final primtype once everything has
been merged. In preparation for this, and for dynamic patch control
points, calculate the final primtype dynamically. We already had a
draw-time workaround for dynamic primtype we can now remove, so this
actually reduces the amount of draw-time work we have to do anyway.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Thu, 18 Aug 2022 09:57:36 +0000 (11:57 +0200)]
tu: Make MSAA emission always dynamic
This wasn't taking into account the dynamic primitive topology, and it
was suboptimal with dynamic rendering, because we don't know when
compiling the pipeline whether variable multisample rate is being used.
It's going to be even more difficult to support the current approach
with graphics pipeline library because the MSAA state is derived from
mulisample state, rasterization state, input assembly state, and
tessellation state, which may be in different pipelines. Just set it
dynamically based on the pipeline and re-emit it when the pipeline's
MSAA or rectangular/bresenham state differs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Wed, 7 Sep 2022 15:39:32 +0000 (17:39 +0200)]
tu: Always set RB_BLIT_GMEM_MSAA_CNTL when clearing GMEM
We weren't setting it in the CmdClearAttachments case. With this, we can
stop setting it in tu6_emit_msaa(), which only happened to work and
would break things in the next commit when we move it to a draw state.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Wed, 7 Sep 2022 15:31:21 +0000 (17:31 +0200)]
tu: Rename RB_MSAA_CNTL to RB_BLIT_GMEM_MSAA_CNTL
Based on experiments and what the blob does, this actually controls the
number of samples in GMEM for CP_EVENT_WRITE::BLIT. Rename it
accordingly.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Thu, 18 Aug 2022 09:54:41 +0000 (11:54 +0200)]
tu: Group pipeline state based on VkPipeline*StateCreateInfo
This will help us to merge state when combining pipelines.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Thu, 18 Aug 2022 09:02:22 +0000 (11:02 +0200)]
tu: Remove unused need_indirect_descriptor_sets
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Wed, 31 Aug 2022 12:05:56 +0000 (14:05 +0200)]
tu: Fix case where vertex input is set but not vertex buffers
Some CTS tests, in particular,
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.independent_pipeline_layout_sets.*,
do the following:
1. Create a pipeline with a vertex input struct that defines a single
attribute pointing to vertex buffer #0, but a vertex shader that
doesn't use any attributes.
2. Bind the pipeline, but don't call vkCmdBindVertexBuffers(), then
draw.
Other drivers handle this just fine because the vertex input registers
are never used. However we have an optimization in turnip where we
pre-calculate the size of the vertex buffer draw state when the vertex
input draw state is bound, which results in a vertex buffer draw state
with non-zero size but zero iova, resulting in hangs. While it's
questionable whether this is allowed, it's easy enough to just disable
the draw state in that case.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Connor Abbott [Wed, 7 Sep 2022 15:16:40 +0000 (17:16 +0200)]
tu: Also set SP_FS_MRT_REG for unused attachments
This fixes some flakes with
dEQP-VK.pipeline.monolithic.multisample.alpha_to_coverage_unused_attachment.samples_2.alpha_opaque
on a650 with some other patches on top. I believe this is also the
source of the flakes on a630.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18554>
Samuel Pitoiset [Thu, 15 Sep 2022 14:01:36 +0000 (16:01 +0200)]
radv: emit the rasterization samples through an user SGPR if needed
When the main FS needs sample positions and the number of samples
isn't known at compile time with GPL.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18677>
Samuel Pitoiset [Mon, 19 Sep 2022 13:08:52 +0000 (15:08 +0200)]
radv: add barycentric_at_sample lowering when the number of samples is dynamic
Use two different paths (static vs dynamic) to avoid running more NIR
pass to remove dead CF code when static is used.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18677>
Samuel Pitoiset [Mon, 19 Sep 2022 13:07:04 +0000 (15:07 +0200)]
nir,radv: pass the number of samples to load_sample_positions_amd
This will be used to lower it when it's dynamic.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18677>
Samuel Pitoiset [Thu, 15 Sep 2022 12:48:17 +0000 (14:48 +0200)]
radv: lower nir_load_rasterization_samples_amd in ABI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18677>
Samuel Pitoiset [Thu, 15 Sep 2022 12:47:03 +0000 (14:47 +0200)]
nir: add nir_load_rasterization_samples_amd
This will be used to load the number of rasterization samples when a
fragment shader is compiled inside a library without the MSAA state.
RADV needs to know the number of samples for loading sample positions
with interpolateAtSample().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18677>
Samuel Pitoiset [Thu, 15 Sep 2022 11:53:43 +0000 (13:53 +0200)]
radv: declare shader arguments for the number of samples for FS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18677>
Samuel Pitoiset [Thu, 15 Sep 2022 11:36:51 +0000 (13:36 +0200)]
radv: add radv_pipeline_key::dynamic_rasterization_samples
With GPL, it's possible to build the main FS without the multisample
state, but the number of rasterization samples is required for
lowering interpolateAtSample(). In this rare situation, the number of
samples will be passed through a new user SGPR.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18677>
Samuel Pitoiset [Thu, 15 Sep 2022 12:25:11 +0000 (14:25 +0200)]
radv: constify radv_lookup_user_sgpr()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18677>
Samuel Pitoiset [Tue, 20 Sep 2022 06:37:10 +0000 (08:37 +0200)]
radv: acquire pstate on-demand when capturing with RGP
AMDGPU pstate is per-device, not per Vulkan logical devices. The same
AMDGPU device is shared accross logical devices because the driver
creates only one winsys per fd. The kernel only allows one context
at a time per AMDGPU device, otherwise it returns -EBUSY.
Fixes this by acquiring pstate on-demand to avoid this multiple
logical device problem.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17712>
Samuel Pitoiset [Tue, 20 Sep 2022 06:24:07 +0000 (08:24 +0200)]
radv: rename radv_thread_trace_set_pstate() to radv_device_set_pstate()
Setting pstate is used for RGP captures and performance counters, so
this name is more generic. Also make it non static.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17712>
Marcin Ślusarz [Thu, 8 Sep 2022 13:27:53 +0000 (15:27 +0200)]
intel/compiler: add support for 8/16 bits task payload loads
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18501>
Marcin Ślusarz [Thu, 8 Sep 2022 13:01:10 +0000 (15:01 +0200)]
intel/compiler: refactor brw_nir_lower_mem_access_bit_sizes
Change dup_mem_intrinsic return type.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18501>
Marcin Ślusarz [Wed, 7 Sep 2022 10:44:38 +0000 (12:44 +0200)]
intel/compiler/task: use shared memory for small task payload loads & stores
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18501>
Marcin Ślusarz [Wed, 7 Sep 2022 10:43:10 +0000 (12:43 +0200)]
nir/lower_task_shader: lower small stores & loads to shared when requested
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18501>
Danylo Piliaiev [Tue, 20 Sep 2022 17:20:00 +0000 (20:20 +0300)]
turnip: Implement VK_EXT_mutable_descriptor_type
Trivial promotion from VALVE, just rename enums and types.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18710>
Tapani Pälli [Tue, 20 Sep 2022 10:11:26 +0000 (13:11 +0300)]
anv: remove primitive_topology from 3DPRIMITIVE calls
Field is ignored on BDW+, 3DSTATE_VF_TOPOLOGY is used to set topology.
We still want to preserve topology information in state because
of other upcoming changes that require it.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18698>
Tapani Pälli [Tue, 20 Sep 2022 07:59:25 +0000 (10:59 +0300)]
intel/common: clamp sample location coordinate range
Applications may use out-of-range values, driver is responsible for
clamping to implementation-dependent sample location coordinate
range.
Without clamp we hit assert when packing 3DSTATE_SAMPLE_PATTERN if
application attempts to use bigger value than 0.9375.
util_bitpack_ufixed: Assertion `min <= v && v <= max' failed.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18696>
Jason Ekstrand [Mon, 19 Sep 2022 21:56:14 +0000 (16:56 -0500)]
vulkan: Add a helper for gathering pipeline robustness
This is useful for implementing VK_EXT_pipeline_robustness because it
automatically gathers all the bits from everywhere for you.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18690>
Jason Ekstrand [Mon, 19 Sep 2022 21:55:55 +0000 (16:55 -0500)]
vulkan: Record more enabled robustness features
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18690>
Emma Anholt [Sat, 5 Feb 2022 04:02:33 +0000 (20:02 -0800)]
turnip: Add TU_DEBUG=bos to print stats of BOs live at submit time.
I keep needing to hack this in to debug BO leaks, so let's just add it as
an option to use in general.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18679>
Emma Anholt [Mon, 19 Sep 2022 17:30:21 +0000 (10:30 -0700)]
turnip: Fix leak of autotune fence BOs.
If we're reusing the submission data, then reinitializing its CS would
leak its old BO.
Fixes: #7281. glmark2 -b texture goes from 277fps to 1268.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18679>
José Roberto de Souza [Fri, 2 Sep 2022 13:43:47 +0000 (06:43 -0700)]
anv: Nuke cmd_parser_version
This was only necessary for gen7 platforms that no longer support by
anv.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18601>
José Roberto de Souza [Wed, 14 Sep 2022 15:39:39 +0000 (08:39 -0700)]
vulkan_hasvk: Nuke dead code around I915_ENGINE_CLASS_COMPUTE
GPUs supported by this driver don't have I915_ENGINE_CLASS_COMPUTE,
so we can drop all this code.
v2:
- keeping anv_override_engine_counts()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18601>
Mike Blumenkrantz [Tue, 20 Sep 2022 19:16:34 +0000 (15:16 -0400)]
ci: add nouveau flakes
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
28669371
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18712>
Mike Blumenkrantz [Tue, 20 Sep 2022 19:19:36 +0000 (15:19 -0400)]
ci: add a panfrost flake
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
28669388
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18714>
Mike Blumenkrantz [Thu, 15 Sep 2022 01:44:14 +0000 (21:44 -0400)]
anv: force inline more pipe flush functions
yields increased ~33% draw throughput
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18637>
Lionel Landwerlin [Mon, 19 Sep 2022 20:55:20 +0000 (23:55 +0300)]
anv: combine flushes in Draw/DrawIndexed/DrawIndirectByteCountEXT
Based off a patch from zmike
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18637>
Lionel Landwerlin [Mon, 19 Sep 2022 20:28:58 +0000 (23:28 +0300)]
anv: don't export gfx state flushing helper
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18637>
Lionel Landwerlin [Mon, 19 Sep 2022 20:27:20 +0000 (23:27 +0300)]
anv: don't export flush_compute_state
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18637>
Iván Briano [Tue, 13 Sep 2022 19:28:42 +0000 (12:28 -0700)]
anv: populate rt shader groups if they were found in the cache
If the pipeline does not use libraries and the shaders are all found in
the cache, we end up with empty groups and crash at pipeline emit time.
Fixes a bunch of tests under
dEQP-VK.pipeline.monolithic.shader_module_identifier.\*.ray_tracing\*
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18582>
Yonggang Luo [Mon, 19 Sep 2022 18:04:51 +0000 (02:04 +0800)]
aco: Convert to use u8 literal for Unicode character to fixes msvc warning
Warning:
aco_register_allocation.cpp(383): warning C4819: The file contains a character that cannot be represented in the current code page (0). Save the file in Unicode format to prevent data loss
This warning was treated as error with compiling with msvc
u8 is belongs to c11 standard so it's safe to use it
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18682>
Yonggang Luo [Thu, 8 Sep 2022 18:53:44 +0000 (02:53 +0800)]
radv: Remove the redundant #include <gelf.h> and #include <libelf.h> in ac_binary.c
It's not access these two header in the source code
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18682>
Marcin Ślusarz [Fri, 3 Jun 2022 13:39:45 +0000 (15:39 +0200)]
intel/compiler: use nir_lower_task_shader pass
This implements task payload atomics in ANV.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16852>
Marcin Ślusarz [Tue, 20 Sep 2022 13:11:30 +0000 (15:11 +0200)]
intel/compiler: print shader after successful brw_nir_lower_shading_rate_output
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18702>
Marcin Ślusarz [Tue, 20 Sep 2022 13:02:22 +0000 (15:02 +0200)]
intel/compiler: remove second shading rate lowering for mesh
It's already called in brw_postprocess_nir and calling it the second time
actually breaks shading rate.
Initially, when I added this call here in
9acb30c8c40, I was testing it
on an internal tree, which didn't have brw_nir_lower_shading_rate_output call
in brw_postprocess_nir.
Fixes:
9acb30c8c40 ("intel/compiler: implement primitive shading rate for mesh")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18702>
Emma Anholt [Thu, 15 Sep 2022 21:19:33 +0000 (14:19 -0700)]
ci: Update kernel to drm-next-2022-08-12-1
This brings in new msm UAPI that we'd like to be testing in turnip.
Unfortunately, a530 became flaky across dEQP and piglit. It seems that a
GPU hang from a test that we expect to hang will cause a followup
hangcheck affecting innocent tests. For example:
22-09-19 18:53:22 R SERIAL> [ 348.839188] msm_mdp 901000.mdp: [drm:a5xx_irq] *ERROR* gpu fault ring 0 fence ff55 status
C10001C3 rb 084a/084a ib1
000000000105A000/0000 ib2
000000000105B000/0000
22-09-19 18:53:22 R SERIAL> [ 348.839272] msm_mdp 901000.mdp: [drm:recover_worker] *ERROR* A530: hangcheck recover!
22-09-19 18:53:22 R SERIAL> [ 348.852698] msm_mdp 901000.mdp: [drm:recover_worker] *ERROR* A530: offending task: shader_run:sq0 (/piglit/bin/shader_runner tests/spec/glsl-1.30/execution/clipping/vs-clip-distance-enables.shader_test -auto -fbo)
22-09-19 18:53:22 R SERIAL> [ 348.868680] msm_mdp 901000.mdp: [drm:a5xx_irq] *ERROR* gpu fault ring 0 fence ff55 status
C10001C3 rb 084a/084a ib1
000000000105A000/0000 ib2
000000000105B000/0000
22-09-19 18:53:22 R SERIAL> [ 348.879586] msm_mdp 901000.mdp: [drm:recover_worker] *ERROR* A530: hangcheck recover!
[...]
22-09-19 18:53:23 R SERIAL> ERROR - Test spec@glsl-1.10@execution@algebraic@glsl-algebraic-logicand-false: Fail: See "//results/piglit.spec@glsl-1.10@execution@algebraic@glsl-algebraic-logicand-false.log"
As a result, I've moved a530 to test-manual-mr until it can be stabilized
again. This updated kernel also brings in a couple of regression fixes
for nouveau gk20a and gm20b.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18624>
Michel Dänzer [Tue, 20 Sep 2022 12:25:47 +0000 (14:25 +0200)]
lavapipe: Fix float32_atomic_min_max spelling
Fixes build with LLVM >= 15.
Fixes:
31695f81c925 ("lavapipe: export VK_KHR_shader_atomic_float")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18701>
Michel Dänzer [Tue, 20 Sep 2022 12:24:51 +0000 (14:24 +0200)]
gallivm: Fix LLVMAtomicRMWBinOpFMax spelling
Fixes build with LLVM >= 15.
Fixes:
203920d4c693 ("gallivm: add atomic 32-bit float support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18701>
Emma Anholt [Sun, 18 Sep 2022 20:55:19 +0000 (13:55 -0700)]
ci/nouveau: Update gm20b xfails.
Similar set of skips as gk20a, so we can find any remaining flakes given
the firehose of SSBOs and geom/tess flakes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18674>
Emma Anholt [Sat, 17 Sep 2022 04:40:46 +0000 (21:40 -0700)]
ci/nouveau: fix up Jetson Nano
The updated board has a stabilized GPU and now I just need to decide if
I'm building a farm of them or not. The new firmware flash needs a
reminder to the kernel of how to do NFS (no v2, thanks). Also, the full
run is long and we need the TEST_PHASE_TIMEOUT variable to go past 20
minutes now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18674>
Emma Anholt [Sun, 18 Sep 2022 18:10:40 +0000 (11:10 -0700)]
ci/nouveau: Rearrange job setup variables.
Now there's "generic stuff for nouveau with bare metal", "the two board
types and how to use them", and "the specific jobs for those boards."
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18674>
Emma Anholt [Sun, 18 Sep 2022 18:05:01 +0000 (11:05 -0700)]
ci/nouveau: Drop BM_POE_TIMEOUT.
Unused since
5f09b1ebe988 ("ci/bare-metal: Add test phase timeouts to all
boards.").
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18674>
Michael Skorokhodov [Fri, 6 May 2022 09:28:21 +0000 (12:28 +0300)]
egl: Return EGL_BAD_MATCH for invalid share_list
From the eglspec.1.5: "An EGL_BAD_MATCH is generated if [...]
share context was created on a different display than
the one referenced by config."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6414
Signed-off-by: Mykhailo Skorokhodov<mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16368>
Friedrich Vock [Mon, 19 Sep 2022 17:42:37 +0000 (19:42 +0200)]
radv: Correct accel struct header size
The size was changed when adding metadata but not updated here.
Fixes:
07eceb4f ("radv: Add metadata to acceleration structures")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18680>
Pavel Ondračka [Mon, 19 Sep 2022 12:34:28 +0000 (14:34 +0200)]
r300: reduce CPU overhead in IF transformation pass
Right now there is a call to rc_get_variables, which performs a global
analysis of the whole shader, for every IF encountered. As a result,
shaders with a lot of IFs are compiled very slowly. The patological
cases are shaders using relative adressing, where the lowered array
access can result in tens of IFs.
This patch restructures the pass to call the rc_get_variables just once
at the beginning and later reuse the gathered info. We can do this,
because even though we transform the shader in the meantime (like for
example adding extra MOVs) the transformations are not siginificant
enough to influence the relevant variable info we are using.
This reduces CPU time for my shader-db by more than a half. I also
checked that the generated code for all shaders in shader-db is
identical.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18678>
Samuel Pitoiset [Tue, 13 Sep 2022 12:54:46 +0000 (14:54 +0200)]
radv,aco: do not compact MRTs if the pipeline uses a PS epilog
We can't detect color attachment without exports when compiling a PS
epilog, so we can't compact MRTs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18514>
Iago Toral Quiroga [Tue, 20 Sep 2022 08:48:19 +0000 (10:48 +0200)]
v3dv: fix VK_EXT_texel_buffer_alignment
This extension was promoted to Vulkan 1.3 so we should be setting its
properties directly in the VkPhysicalDeviceVulkan13Properties struct
which the common mesa code will use to populate outgoing properties.
Apparently, only the properties struct was promoted and not the features
struct.
Reviewed-by: Eric Engestrom <eric@igalia.com>
Tested-by: Eric Engestrom <eric@igalia.com>
Fixes:
ee62a4c751c ('v3dv: implement VK_EXT_texel_buffer_alignment')
Fixes: dEQP-VK.api.info.get_physical_device_properties2.properties.basic
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18697>
Rhys Perry [Mon, 12 Sep 2022 11:11:09 +0000 (12:11 +0100)]
aco: DCE ra_ctx::defs_done
This was used to distinguish definitions fixed before and during RA, but
it seems it isn't used anymore.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18547>
Samuel Pitoiset [Fri, 9 Sep 2022 09:35:55 +0000 (11:35 +0200)]
radv: allow to build the main FS in a graphics pipeline library
Corner cases like implicit gl_PrimitiveID are currently broken and
will be fixed later, but the general case should work.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18516>
Samuel Pitoiset [Thu, 1 Sep 2022 08:16:11 +0000 (10:16 +0200)]
radv: do not link shaders when the next stage is unknown
With GPL, it's possible to build the pre-rasterization stages separately
from the fragment stage. Implicit IO (like gl_PrimitiveID) between the
last pre-rast stage and the FS will be addressed later.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18516>
Marcin Ślusarz [Mon, 19 Sep 2022 10:55:19 +0000 (12:55 +0200)]
nir, anv, hasvk, radv: pull uses_wide_subgroup_intrinsics into shader_info
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18504>
Marcin Ślusarz [Mon, 19 Sep 2022 10:41:09 +0000 (12:41 +0200)]
anv: small cleanup of anv_graphics_pipeline_compile
Extract variables for things that are computed multiple times.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18504>
Marcin Ślusarz [Wed, 31 Aug 2022 12:28:04 +0000 (14:28 +0200)]
anv: add support for anv_assume_full_subgroups to task & mesh stages
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18504>
Marcin Ślusarz [Wed, 31 Aug 2022 12:26:58 +0000 (14:26 +0200)]
nir: add uses_wide_subgroup_intrinsics to task/mesh shader_info
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18504>
Samuel Pitoiset [Thu, 15 Sep 2022 12:58:51 +0000 (14:58 +0200)]
radv,aco: lower barycentric_at_sample in NIR
fossils-db (NAVI21):
Totals from 158 (0.12% of 134913) affected shaders:
CodeSize: 569456 -> 568824 (-0.11%)
Only Control seems affected.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18615>
Samuel Pitoiset [Thu, 15 Sep 2022 12:56:28 +0000 (14:56 +0200)]
radv: run nir_opt_cse before lowering FS intrinsics
Otherwise, there might be redundant barycentric_at_sample intrinsics
that will be lowered and this will increase code size.
No fossils-db changes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18615>
Samuel Pitoiset [Thu, 15 Sep 2022 12:55:59 +0000 (14:55 +0200)]
radv: add nir_intrinsic_load_sample_positions_amd in the ABI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18615>
Samuel Pitoiset [Thu, 15 Sep 2022 12:55:10 +0000 (14:55 +0200)]
nir: add nir_intrinsic_load_sample_positions_amd
This will be used to lower barycentric_at_sample in NIR for RADV.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18615>
Bas Nieuwenhuizen [Tue, 20 Sep 2022 00:37:39 +0000 (02:37 +0200)]
ac/surface: Fix some warnings.
../mesa/src/amd/common/ac_surface.c:2324:48: warning: implicit conversion from enumeration type 'AddrResourceType' (aka 'enum _AddrResourceType') to different enumeration type 'enum gfx9_resource_type' [-Wenum-conversion]
surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
~ ~~~~~~~~~~~~~~~^~~~~~~~~~~~
../mesa/src/amd/common/ac_surface.c:3046:38: warning: implicit conversion from enumeration type 'const enum gfx9_resource_type' to different enumeration type 'AddrResourceType' (aka 'enum _AddrResourceType') [-Wenum-conversion]
input.resourceType = surf->u.gfx9.resource_type;
~ ~~~~~~~~~~~~~^~~~~~~~~~~~~
../mesa/src/amd/common/ac_surface.c:3069:38: warning: implicit conversion from enumeration type 'const enum gfx9_resource_type' to different enumeration type 'AddrResourceType' (aka 'enum _AddrResourceType') [-Wenum-conversion]
input.resourceType = surf->u.gfx9.resource_type;
The enums are compatible so lets just add some casts.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18694>
Yonggang Luo [Mon, 19 Sep 2022 18:44:30 +0000 (02:44 +0800)]
clover: Fixes use of designated initializers requires in c++ that doesn't support by MSVC
../src/gallium/frontends/clover/nir/invocation.cpp(400): error C7555: use of designated initializers requires at least '/std:c++20'
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18683>
Iago Toral Quiroga [Fri, 16 Sep 2022 09:44:25 +0000 (11:44 +0200)]
v3dv: optimize ldunif load into unifa write
If we emit a ldunif to load the ubo/ssbo base address and
then we are immediately moving it to the unifa register we
can have the ldunif write directly to unifa and avoid the mov
in between, which won't be done by copy propagation because that
only works with temp registers.
Also, since we can't read from unifa we must be careful to disallow
reuse of the ldunif result for a future ldunif of the same base address.
We do that by only reusing ldunif results from temp registers.
total instructions in shared programs:
12468943 ->
12455139 (-0.11%)
instructions in affected programs: 1661233 -> 1647429 (-0.83%)
helped: 8307
HURT: 3994
total uniforms in shared programs: 3704532 -> 3704522 (<.01%)
uniforms in affected programs: 339 -> 329 (-2.95%)
helped: 7
HURT: 0
total max-temps in shared programs: 2148158 -> 2148290 (<.01%)
max-temps in affected programs: 9320 -> 9452 (1.42%)
helped: 175
HURT: 295
total spills in shared programs: 2202 -> 2202 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0
total fills in shared programs: 3059 -> 3057 (-0.07%)
fills in affected programs: 27 -> 25 (-7.41%)
helped: 1
HURT: 0
total sfu-stalls in shared programs: 21167 -> 21056 (-0.52%)
sfu-stalls in affected programs: 497 -> 386 (-22.33%)
helped: 209
HURT: 127
total inst-and-stalls in shared programs:
12490110 ->
12476195 (-0.11%)
inst-and-stalls in affected programs: 1662875 -> 1648960 (-0.84%)
helped: 8312
HURT: 3987
total nops in shared programs: 316563 -> 313553 (-0.95%)
nops in affected programs: 24269 -> 21259 (-12.40%)
helped: 2158
HURT: 1006
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18667>
Iago Toral Quiroga [Fri, 16 Sep 2022 09:42:50 +0000 (11:42 +0200)]
broadcom/compiler: check signal writes to magic regs when updating scoreboard
We have only been checking magic writes from ADD and MUL ports, but signals
can potentially write to magic registers too.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18667>