Le Ma [Tue, 26 Feb 2019 12:37:17 +0000 (20:37 +0800)]
drm/amdgpu: correct programming of ih_chicken for Arcturus
ih_chicken is a register that is not allowed to access by driver
in the L0 security policy.
psp bl need to enable field to allow driver to use physical
bus address for ih ring on secure part.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Snow Zhang <snow.zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Thu, 15 Nov 2018 10:54:35 +0000 (18:54 +0800)]
drm/amdgpu: add Arcturus chip_name for init sdma microcode
So we load the proper firmware for arcturus.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 20 Nov 2018 07:15:31 +0000 (15:15 +0800)]
drm/amdgpu: enable 8 SDMA instances for Arcturus
All the 8 SDMA instances work fine on the latest Gopher build model.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Thu, 15 Nov 2018 10:56:17 +0000 (18:56 +0800)]
drm/amdgpu: correct Arcturus SDMA address space base index
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 19 Sep 2018 06:17:37 +0000 (14:17 +0800)]
drm/amdgpu: support sdma 2~7 doorbell range register offset
Update the doorbell range registers to support additional
SDMA rings.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 18 Sep 2018 09:39:59 +0000 (17:39 +0800)]
drm/amdgpu: skip all gfx ring settings for Arcturus
Not needed on Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 18 Sep 2018 09:04:42 +0000 (17:04 +0800)]
drm/amdgpu: skip load cp gfx firmware for Arcturus
Arcturus has no CPG component any more.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 18 Sep 2018 08:11:44 +0000 (16:11 +0800)]
drm/amdgpu: optimize gfx9 init_microcode function
Split each type of firmware into single function for easy to maintain.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 9 Jul 2019 14:30:19 +0000 (09:30 -0500)]
drm/amdgpu: add Arcturus gpu info firmware
Add GPU info firmware for Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 11 Sep 2018 05:11:28 +0000 (13:11 +0800)]
drm/amdgpu: skip pasid mapping for second mmhub on Arcturus
There's no LUT register for second mmhub to convert pasid since it has no ATC.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 11 Sep 2018 04:33:11 +0000 (12:33 +0800)]
drm/amdgpu: skip to get 3D engine clockgating state for Arcturus
It's because Arcturus has not 3D engine.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 11 Sep 2018 04:14:37 +0000 (12:14 +0800)]
drm/amdgpu: add to set rlc funcs for Arcturus
Shared with other gfx9 parts so use the same functions.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 11 Sep 2018 04:13:41 +0000 (12:13 +0800)]
drm/amdgpu: add number of mec for Arcturus
MEC is the CP compute microcontroller.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 11 Sep 2018 04:11:36 +0000 (12:11 +0800)]
drm/amdgpu: add gfx config for Arcturus
Add Arcturus GFX config.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 11 Sep 2018 03:58:48 +0000 (11:58 +0800)]
drm/amdgpu: add support for Arcturus firmware
Add support for Arcturus gfx firmwares.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 9 Jul 2019 14:23:11 +0000 (09:23 -0500)]
drm/amdgpu/dce_virtual: add Arcturus virtual display support
Virtual dce is a sw only display driver for emulation and
virtualization and cases where we want to use a virtual
display subsystem.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 11 Sep 2018 03:35:34 +0000 (11:35 +0800)]
drm/amdgpu: set Arcturus fw load type as direct
We currently only support direct firmware loading.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 11 Sep 2018 03:20:18 +0000 (11:20 +0800)]
drm/amdgpu: add to set Arcturus ip blocks
Add IP blocks for Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 11 Sep 2018 03:07:09 +0000 (11:07 +0800)]
drm/amdgpu/soc15: add Arcturus common ip blocks
Add common IP blocks for Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Mon, 10 Sep 2018 11:51:07 +0000 (19:51 +0800)]
drm/amdgpu: support hdp flush for more sdma instances
The bit RSVD_ENG0 to RSVD_ENG5 in GPU_HDP_FLUSH_REQ/GPU_HDP_FLUSH_DONE
can be leveraged for sdma instance 2~7 to poll register/memory.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Mon, 10 Sep 2018 06:26:44 +0000 (14:26 +0800)]
drm/amdgpu: specify sdma instance 5~7 with second mmhub type
On Arcturus, sdma instance 5~7 is connected to the second mmhub. The vmhub type
in amdgpu_ring_funcs is constant, so we create an individual amdgpu_ring_funcs
with different vmhub type(AMDGPU_MMHUB_1) for these sdma instances.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 5 Sep 2018 08:21:20 +0000 (16:21 +0800)]
drm/amdgpu: reorganize sdma v4 code to support more instances
This change is needed for Arcturus which has 8 sdma instances.
The CG/PG part is not covered for now.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Thu, 6 Sep 2018 11:37:51 +0000 (19:37 +0800)]
drm/amdgpu: update vmc interrupt routine to support 3 vmhubs
There is one more vmc interrupt and mmhub on Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Thu, 6 Sep 2018 09:34:06 +0000 (17:34 +0800)]
drm/amdgpu: add VMC1 interrupt client id for Arcturus
New IH client id for VMC1.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 9 Jul 2019 14:21:53 +0000 (09:21 -0500)]
drm/amdgpu: dynamically initialize IP offset for Arcturus
Add support for the IP offsets on Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 9 Jul 2019 14:20:24 +0000 (09:20 -0500)]
drm/amdgpu: increase max number of ip base instances to 8
For Arcturus, the number of IP base instances is 8.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 4 Sep 2018 05:36:22 +0000 (13:36 +0800)]
drm/amdgpu: add SDMA 2~7 ip block type
Add IP block type.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Mon, 3 Sep 2018 11:27:52 +0000 (19:27 +0800)]
drm/amdgpu: add SDMA 2~7 interrupt client id for Arcturus
Add new client ids.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 4 Sep 2018 07:29:52 +0000 (15:29 +0800)]
drm/amdgpu: use new mmhub interfaces for Arcturus
Arcturus has two MMHUBs.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Snow Zhang < Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 9 Jul 2019 14:18:03 +0000 (09:18 -0500)]
drm/amdgpu: add mmhub v9.4.1 block for Arcturus (v2)
Arcturus as an updated mmhub block. mmhub is the
memory controller hub used for sdma and multimedia.
v2: squash in AGP BAR programming (Alex)
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 31 Aug 2018 06:46:47 +0000 (14:46 +0800)]
drm/amdgpu: add one more mmhub instance for Arcturus (v2)
v2: set mmhub num under CHIP_ARCTURUS switch case and add one more mmhub id_mgr
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 31 Aug 2018 06:17:28 +0000 (14:17 +0800)]
drm/amdgpu: add new member in amdgpu_device for vmhub counts per asic chip
It aims to replace AMDGPU_MAX_VMHUBS in for loop to initialize registers.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 16 Jul 2019 18:29:19 +0000 (13:29 -0500)]
drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number
The number of GFXHUB/MMHUB may be expanded in later ASICs.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 4 Sep 2018 06:52:25 +0000 (14:52 +0800)]
drm/amdgpu: add gmc basic support for Arcturus
Add initial GMC support for Arcturus
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 9 Jul 2019 14:16:01 +0000 (09:16 -0500)]
drm/amdgpu: add Arcturus asic type
Add asic type for Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 29 Aug 2018 08:28:38 +0000 (16:28 +0800)]
drm/amdgpu: add Arcturus ip_offset header (v3)
Provides the absolute offsets of the IP register
blocks.
v2: update chip name in source code
v3: squash in MP offset updates (Alex)
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 21 Mar 2019 13:08:19 +0000 (09:08 -0400)]
drm/amdgpu: add VCN2.5 headers
VCN is the multi-media block.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 29 Aug 2018 08:50:20 +0000 (16:50 +0800)]
drm/amdgpu: add sdma 4.2.2 header files for Arcturus
SDMA is the system DMA block.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 29 Aug 2018 08:49:19 +0000 (16:49 +0800)]
drm/amdgpu: add mmhub 9.4.1 header files for Acrturus
mmhub is the GPU memory hub used by SDMA and VCN.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 2 Jul 2019 19:42:25 +0000 (14:42 -0500)]
drm/amdgpu: consolidate navi14 IP init
It's the same as navi10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 2 Jul 2019 19:35:36 +0000 (14:35 -0500)]
drm/amdgpu: disable concurrent flushes on Navi14
Same thing applies to navi14 as navi10.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 5 Jul 2019 21:00:08 +0000 (16:00 -0500)]
drm/amdgpu: enable gfxoff code path for navi14
Based on navi10 gfxoff logic, enable the related code
path for navi14.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 2 Jul 2019 17:52:52 +0000 (12:52 -0500)]
drm/amdgpu/vcn: enable indirect DPG SRAM mode for navi14
Enable VCN dynamic powergating for navi14.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 13 May 2019 09:02:12 +0000 (17:02 +0800)]
drm/amd/powerplay: disable gfxoff for navi14
gfxoff doesn't work on navi14 yet, so disable it for now
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 2 Jul 2019 17:49:41 +0000 (12:49 -0500)]
drm/amdgpu/nv: set vcn pg flag for navi14
Enable VCN power gating by default.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 18 Apr 2019 09:46:17 +0000 (17:46 +0800)]
drm/amd/display: disable display writeback for navi14
not used.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 28 Mar 2019 08:43:16 +0000 (16:43 +0800)]
drm/amdgpu: enable async gfx ring for navi14
Same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 20 Mar 2019 08:12:54 +0000 (16:12 +0800)]
drm/amdgpu: enable clock gatings for navi14
Set appropriate CG flags for navi14.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 22 Mar 2019 05:10:03 +0000 (13:10 +0800)]
drm/amdgpu/athub2: set clock gating for navi14
same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 22 Mar 2019 05:03:01 +0000 (13:03 +0800)]
drm/amdgpu/mmhub2: set clock gating for navi14
same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 20 Mar 2019 04:37:45 +0000 (12:37 +0800)]
drm/amdgpu: declare asd firmware for navi14
So the dependency gets properly tracked.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <snow.zhang@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Fri, 1 Mar 2019 21:23:55 +0000 (16:23 -0500)]
drm/amdgpu: Enable VCN on navi14
Add navi14 vcn firmware, and enable VCN on navi14.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 15 Mar 2019 11:15:21 +0000 (19:15 +0800)]
drm/amd/display: skip to load dmcu firmware for navi14
not needed for navi14 at the moment.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 15 Mar 2019 11:10:47 +0000 (19:10 +0800)]
drm/amdgpu: skip to load ta firmware for navi14
Not relevant on navi14.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Tue, 2 Jul 2019 15:43:55 +0000 (10:43 -0500)]
drm/amd/display: add ASICREV defines v2
Add revs for navi10 and 14.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Tue, 26 Feb 2019 18:38:17 +0000 (13:38 -0500)]
drm/amd/display: add dm block
enable DC for navi14.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Tue, 26 Feb 2019 19:38:59 +0000 (14:38 -0500)]
drm/amd/display: add NAVI14 in resource construct
Change the pipes to 5 if the asic is nv14
This is a temp patch, there was some refactor in the dml part of the code.
which is not in this branch. for now this is good, we can implement this
properly once we have an updated branch.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Tue, 2 Jul 2019 15:41:40 +0000 (10:41 -0500)]
drm/amd/display: add nv14 cases to amdgpu_dm
Mostly shared with navi10.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 12 Feb 2019 19:34:54 +0000 (03:34 +0800)]
drm/amdgpu: enable sw smu ip for navi14
same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 12 Feb 2019 19:44:10 +0000 (03:44 +0800)]
drm/amdgpu/smu11: add support for navi14
Same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 12 Feb 2019 03:12:31 +0000 (03:12 +0000)]
drm/amdgpu/psp: start rlc autoload after psp received rlcg for navi14
Update for navi14.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Sun, 10 Feb 2019 21:45:32 +0000 (21:45 +0000)]
drm/amdgpu: enable psp ip block for navi14
Same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 8 Jul 2019 19:03:15 +0000 (14:03 -0500)]
drm/amdgpu/psp: add psp support for navi14 (v3)
Same as navi10.
v2: squash in logic fix (Colin Ian King)
v3: squash in logic simplification (Alex)
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 16 Jan 2019 02:23:17 +0000 (10:23 +0800)]
drm/amdgpu: enable virtual display for navi14
Virtual display is a sw based kms interface for virtualization
and emulation.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 19 Dec 2018 12:39:37 +0000 (20:39 +0800)]
drm/amdgpu: add ip blocks for navi14
Add the initial IP blocks for navi14
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:23:27 +0000 (18:23 +0800)]
drm/amdgpu/soc15: add support for navi14
same as navi10
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 28 May 2019 05:27:11 +0000 (13:27 +0800)]
drm/amdgpu/gfx10: fix programming of SC_HIZ_TILE_FIFO_SIZE field
max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE
field is programmed in units of two entries, but 6 bits is insufficient
to hold value 128/2 = 64, so set this field as 0 which is interpreted by
the hardware as maximum physical fifo size(128).
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 2 Jul 2019 19:20:04 +0000 (14:20 -0500)]
drm/amdgpu/gfx10: update gfx golden settings for navi14
Updated settings from hw team.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 29 Mar 2019 11:46:46 +0000 (19:46 +0800)]
drm/amdgpu/gfx10: update gfx golden settings for navi14
Add updated settings from hw team.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 13 Feb 2019 23:12:00 +0000 (07:12 +0800)]
drm/amdgpu/gfx: update gc_v10_1_1 golden setting
Updated settings for hw team.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 12 Feb 2019 02:56:57 +0000 (02:56 +0000)]
drm/amdgpu/gfx10: add gfx v10_1_1 golden settings for navi14
Add golden settings for navi14.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 14 Feb 2019 01:06:10 +0000 (09:06 +0800)]
drm/amdgpu/gfx: add definition of mmCGTT_GS_NGG_CLK_CTRL
Needed for clockgating.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 29 Jan 2019 14:36:15 +0000 (22:36 +0800)]
drm/amdgpu/gfx10: set tcp harvest for navi14
Update settings for navi14.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 25 Dec 2018 06:45:57 +0000 (14:45 +0800)]
drm/amdgpu: set rlc funcs for navi14
Same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 25 Dec 2018 06:45:21 +0000 (14:45 +0800)]
drm/amdgpu: add me/mec configurations for navi14
Add navi14 to appropriate cases.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:22:16 +0000 (18:22 +0800)]
drm/amdgpu/gfx10: add clockgating support for navi14
Same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:21:35 +0000 (18:21 +0800)]
drm/amdgpu/gfx10: add gfx config for navi14
Add gfx config details for navi14.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 16 Jul 2019 18:22:04 +0000 (13:22 -0500)]
drm/amdgpu/gfx10: add placeholder for navi14 golden settings
To be filled in once available.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:08:28 +0000 (18:08 +0800)]
drm/amdgpu/gfx10: add support for navi14 firmware
Add support for navi14 CP firmware files.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 22 Mar 2019 05:14:25 +0000 (13:14 +0800)]
drm/amdgpu/sdma5: set clock gating for navi14
same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
tiancyin [Tue, 21 May 2019 06:43:48 +0000 (14:43 +0800)]
drm/amdgpu/sdma5: update sdma5 golden settings for navi14
add new registers:
mmSDMA0_RLC3_RB_WPTR_POLL_CNTL,
mmSDMA1_RLC3_RB_WPTR_POLL_CNTL
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 12 Feb 2019 02:58:06 +0000 (02:58 +0000)]
drm/amdgpu/sdma5: add sdma5_0 golden settings for navi14
Add settings for navi14.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Snow Zhang <Snow.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:07:22 +0000 (18:07 +0800)]
drm/amdgpu/sdma5: add placeholder for navi14 golden settings
To be filled in once they are available.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:05:32 +0000 (18:05 +0800)]
drm/amdgpu/sdma5: add support for navi14 firmware
Add support for navi14 sdma firmware files.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:19:42 +0000 (18:19 +0800)]
drm/amdgpu/gmc10: add navi14 support
same as navi10
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 25 Dec 2018 06:44:23 +0000 (14:44 +0800)]
drm/amdgpu: increase max instance number for hw ip
max instance number is 6 for navi10 and 7 for navi14, and we increase the
reg_offset array size to avoid out-of-bound access
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 5 Jun 2019 09:58:57 +0000 (17:58 +0800)]
drm/amdgpu/discovery: init reg base offset via ip discovery for navi14
Add IP discovery for navi14.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:24:03 +0000 (18:24 +0800)]
drm/amdgpu/soc15: initialize reg base for navi14 (v2)
Initialize the IP register base offsets for navi14.
v2: squash in MP, CLK, THM updates
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:04:19 +0000 (18:04 +0800)]
drm/amdgpu: add navi14 ucode loading method
Same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:02:43 +0000 (18:02 +0800)]
drm/amdgpu: set asic family and ip blocks for navi14
same with navi10
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:01:38 +0000 (18:01 +0800)]
drm/amdgpu: add gpu_info firmware for navi14
Add navi14 to case statement to load the GPU info firmware.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:00:26 +0000 (18:00 +0800)]
drm/amdgpu: add navi14 asic type
Add CHIP_NAVI14 to the list of asic types.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hersen wu [Wed, 26 Jun 2019 17:06:07 +0000 (13:06 -0400)]
drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq
[WHY] dc sw clock implementation of navi10 and raven are not exact the
same. dcccg, dchub reference clock initialization is done after dc calls
vbios dispcontroller_init table. for raven family, before
dispcontroller_init is called by dc, the ref clk values are referred
by sw clock implementation and program asic register using wrong
values. this causes dchub pstate error. This need provide valid ref
clk values. for navi10, since dispcontroller_init is not called,
dchubbub_global_timer_enable = 0, hubbub2_get_dchub_ref_freq will
hit aeert. this need remove hubbub2_get_dchub_ref_freq from this
location and move to dcn20_init_hw.
[HOW] for all asic, initialize dccg, dchub ref clk with data from
vbios firmware table by default. for raven asic family, use these data
from vbios, for asic which support sw dccg component, like navi10,
read ref clk by sw dccg functions and update the ref clk.
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 17 Jul 2019 18:10:39 +0000 (13:10 -0500)]
drm/amdgpu/pm: remove check for pp funcs in freq sysfs handlers
The dpm sensor function already does this for us. This fixes
the freq*_input files with the new SMU implementation.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 5 Jul 2019 20:54:28 +0000 (16:54 -0400)]
drm/amd/display: Force uclk to max for every state
Workaround for now to avoid underflow.
The uclk switch time should really be bumped up to 404, but doing so
would expose p-state hang issues for higher bandwidth display
configurations.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Greathouse [Wed, 17 Jul 2019 14:47:58 +0000 (09:47 -0500)]
drm/amdkfd: Remove GWS from process during uninit
If we shut down a process without having destroyed its GWS-using
queues, it is possible that GWS BO will still be in the process
BO list during the gpuvm destruction. This list should be empty
at that time, so we should remove the GWS allocation at the
process uninit point if it is still around.
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Tue, 16 Jul 2019 11:23:22 +0000 (07:23 -0400)]
drm/amd/amdgpu: Fix offset for vmid selection in debugfs interface
The register debugfs interface was using the wrong bitmask for vmid
selection for GFX_CNTL.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 12 Jul 2019 02:53:11 +0000 (10:53 +0800)]
drm/amd/powerplay: update vega20 driver if to fit latest SMU firmware
Optimization for the socket power calculation is introduced.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 16 Jul 2019 06:20:22 +0000 (14:20 +0800)]
drm/amd/powerplay: maintain SMU FW backward compatibility
Do not halt driver loading on if_version mismatch. As our
driver and FWs are backward compatible.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 11 Jul 2019 07:13:17 +0000 (15:13 +0800)]
drm/amd/powerplay: correct smu_update_table usage
The interface was used in a confusing way. In profile mode scenario,
the 2nd parameter of the interface was used in a different way from
other scenarios.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / platform / kernel / linux-starfive.git / log