David Goldman [Mon, 7 Feb 2022 15:20:33 +0000 (10:20 -0500)]
Reland "[clangd] Properly compute framework-style include spelling"
Roll forward of https://reviews.llvm.org/D117056 with a fix. Proper
initialization of `IsPrivateHeader` was missing, causing failures
on Linux.
Nathan Sidwell [Fri, 21 Jan 2022 19:00:56 +0000 (11:00 -0800)]
[demangler] Stricter NestedName parsing
The parsing of nested names is a little lax. This corrects that.
1) The 'L' local name prefix cannot appear before a NestedName -- only
within it. Let's remove that check from parseName, and then adjust
parseUnscopedName to allow it with or without the 'St' prefix.
2) In a nested name, a <template-param>, <decltype> or <substitution>
can only appear as the first element. Let's enforce that. Note I do
not remove these from the loop, to make the change easier to follow
(such a change will come later).
3) Given that, there's no need to special case 'St' outside of the
loop, handle it with the other 'S' elements.
4) There's no need to reset 'EndsWithTemplateArgs' after each
non-template-arg component. Rather, always clear it and then set it
in the template-args case.
5) An template-args cannot immediately follow a template-args.
6) The parsing of a CDtor name with ABITags would attach the tags to
the NestedName node, rather than the CDTor node. This is different to
how ABITags are attached to an unscopedName. Make it consistent.
7) We remain with only CDTor and UnscopedName requireing construction
of a NestedName, so let's drop the PushComponent lambda.
8) Add some tests to catch the new rejected manglings.
Reviewed By: ChuanqiXu
Differential Revision: https://reviews.llvm.org/D118132
Jonas Devlieghere [Mon, 7 Feb 2022 16:11:30 +0000 (08:11 -0800)]
[lldb] Update outdated comment in TestDyldTrieSymbols.py
After
aed965d55d46 we no longer demangle and store the full name. The
test was updated accordingly but the comment still specified that we
should be able to find the symbol by its full demangled name.
Nikita Popov [Mon, 7 Feb 2022 15:52:31 +0000 (16:52 +0100)]
[MatrixBuilder] Require explicit element type in CreateColumnMajorLoad()
This makes the method compatible with opaque pointers.
Hans Wennborg [Mon, 7 Feb 2022 15:47:14 +0000 (16:47 +0100)]
Revert "Remove -Wweak-template-vtables"
Turns out there's still some code referencing this. No harm in keeping it in a
bit longer.
> as it was planned for removal in clang 15 and we're now past the branch point
>
> See https://github.com/llvm/llvm-project/issues/19107
>
> Differential revision: https://reviews.llvm.org/D118762
This reverts commit
564f9be11c9cb8d131f48df07538fab7a19b41a7.
Nikita Popov [Mon, 7 Feb 2022 15:51:22 +0000 (16:51 +0100)]
[mlir] Remove MatrixBuilder template argument
I dropped this argument in
cdc0573f753e639ed78f2a3645179ac2d2718fd0,
but did not adjust mlir. (Or rather I did, but I modified a generated
file ... oops)
Nathan Sidwell [Fri, 28 Jan 2022 19:59:03 +0000 (11:59 -0800)]
[demangler] Fix unresolvedname demangling
We were dropping the [gs] modifier by parsing it in parseExpr, but not
forwarding it on to parseUnresolvedName. This is the straightforwards
fix to forward that flag -- parseExpr must see past it.
Reviewed By: ChuanqiXu
Differential Revision: https://reviews.llvm.org/D118504
Nathan Sidwell [Fri, 21 Jan 2022 19:37:01 +0000 (11:37 -0800)]
[demangler] Remove StdQualifiedName
The StdQualifiedName node class is used for names exactly in the std
namespace. It is not used for nested names that descend further --
those use a NestedName with NameType("std") as the scope.
Representing the compression scheme in the node graph is layer
breaking. We can use the same structure for those exactly in std too,
and reduce code size a bit.
Reviewed By: ChuanqiXu
Differential Revision: https://reviews.llvm.org/D118249
Mark Murray [Mon, 24 Jan 2022 10:39:03 +0000 (10:39 +0000)]
[ARM] Undeprecate complex IT blocks
AArch32/Armv8A introduced the performance deprecation of certain patterns
of IT instructions. After some debate internal to ARM, this is now being
reverted; i.e. no IT instruction patterns are performance deprecated
anymore, as the perfomance degredation is not significant enough.
This reverts the following:
"ARMv8-A deprecates some uses of the T32 IT instruction. All uses of
IT that apply to instructions other than a single subsequent 16-bit
instruction from a restricted set are deprecated, as are explicit
references to the PC within that single 16-bit instruction. This permits
the non-deprecated forms of IT and subsequent instructions to be treated
as a single 32-bit conditional instruction."
The deprecation no longer applies, but the behaviour may be controlled
by the -arm-restrict-it and -arm-no-restrict-it command-line options,
with the latter being the default. No warnings about complex IT blocks
will be generated.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D118044
Nikita Popov [Mon, 7 Feb 2022 15:33:58 +0000 (16:33 +0100)]
[MatrixBuilder] Remove unnecessary IRBuilder template (NFC)
IRBuilderBase exists specifically to avoid the need for this.
Volodymyr Turanskyy [Mon, 7 Feb 2022 13:30:16 +0000 (14:30 +0100)]
Add LLVM Embedded Toolchains call to the table of sync ups.
LLVM Embedded Toolchains working group regular sync up calls to start in early
March, adding details to the table of sync ups for general reference.
Differential Revision: https://reviews.llvm.org/D118884
Sanjay Patel [Mon, 7 Feb 2022 15:12:12 +0000 (10:12 -0500)]
[x86] avoid false dependency stall on 'sbb' with same source reg
This is effectively inverting the transform added with D116804
because the downside of the false dependency of something like
"sbb %eax, %eax" is much greater than the upside of eliminating
a zeroing instruction on (all?) Intel CPUs.
Differential Revision: https://reviews.llvm.org/D118843
Sanjay Patel [Mon, 7 Feb 2022 14:04:33 +0000 (09:04 -0500)]
[InstCombine] add test for demanded 2 low bits of X*X; NFC
Matt Arsenault [Mon, 1 Nov 2021 18:22:10 +0000 (14:22 -0400)]
AMDGPU: Fix clobbering SCC when expanding large offset spill pseudos
If we had a large offset which required materializing in a register,
we would emit an s_add_i32, clobbering SCC. Start checking if SCC is
live, and instead use a VGPR offset. For MUBUF, we switch to using
offen. We would do this anyway in a normal load/store with a frame
index, but not for spills.
The same problem still exists in other contexts where we expand frame
indices.
The nasty edge case is when SGPRs are spilled to memory at a large
frame offset where SCC is also clobbered. This requires a second
scavenging index, and also required several patches in the scavenger
to correctly handle multiple recursive scavenge indexes.
An even nastier edge case we still don't support is if we don't have
any free SGPRs. If SCC is live and we don't have any free SGPRs to
save exec, we have no way of flipping exec back and forth without also
clobbering SCC.
Fixes: SWDEV-309419
David Truby [Thu, 27 Jan 2022 16:31:00 +0000 (16:31 +0000)]
[AArch64][NEON][SVE] Lower FCOPYSIGN using AArch64ISD::BSP
This patch modifies the FCOPYSIGN lowering to go through the BSP
pseudo-instruction. This allows the same lowering code for NEON,
SVE and SVE2.
As part of this, lowering for BSP for SVE and SVE2 is also added.
For SVE and NEON this patch is NFC.
Differential Revision: https://reviews.llvm.org/D118394
Aaron Ballman [Mon, 7 Feb 2022 14:24:09 +0000 (09:24 -0500)]
Use functions with prototypes when appropriate; NFC
A significant number of our tests in C accidentally use functions
without prototypes. This patch converts the function signatures to have
a prototype for the situations where the test is not specific to K&R C
declarations. e.g.,
void func();
becomes
void func(void);
This is the third batch of tests being updated (there are a significant
number of other tests left to be updated).
ksyx [Sun, 6 Feb 2022 02:18:04 +0000 (02:18 +0000)]
[clang-format] Fix DefSeparator empty line issues
- Add or remove empty lines surrounding union blocks.
- Fixes https://github.com/llvm/llvm-project/issues/53229, in which
keywords like class and struct in a line ending with left brace or
whose next line is left brace only, will be falsely recognized as
definition line, causing extra empty lines inserted surrounding blocks
with no need to be formatted.
Reviewed By: MyDeveloperDay, curdeius, HazardyKnusperkeks, owenpan
Differential Revision: https://reviews.llvm.org/D119067
Kim Gräsman [Mon, 7 Feb 2022 14:21:41 +0000 (09:21 -0500)]
Reformat CastExpr unittest suite; NFC
In preparation for adding new tests. No functional change.
Pavel Labath [Mon, 7 Feb 2022 13:52:22 +0000 (14:52 +0100)]
[lldb/Platform] s/m_name/m_hostname
m_name is confusing, as there is a getter called GetName, but it returns
a completely different thing.
Balázs Kéri [Mon, 7 Feb 2022 13:50:47 +0000 (14:50 +0100)]
[clang-tidy] Fixed a compile warning (NFC).
Fixed a "override" related warning in SharedPtrArrayMismatchCheck.h.
Related to differential revision: https://reviews.llvm.org/D117306
Sanjay Patel [Sat, 5 Feb 2022 15:18:38 +0000 (10:18 -0500)]
[InstCombine] SimplifyDemandedBits - mul(x,x) is odd iff x is odd
https://alive2.llvm.org/ce/z/AXPr3k
Nikita Popov [Mon, 7 Feb 2022 13:29:36 +0000 (14:29 +0100)]
[PPCISelLowering] Avoid use of getPointerElementType()
Use the value type instead.
Bjorn Pettersson [Fri, 4 Feb 2022 12:39:52 +0000 (13:39 +0100)]
[test] Use -passes=instcombine instead of -instcombine in lots of tests. NFC
Another step moving away from the deprecated syntax of specifying
pass pipeline in opt.
Differential Revision: https://reviews.llvm.org/D119081
Bjorn Pettersson [Fri, 4 Feb 2022 10:45:19 +0000 (11:45 +0100)]
[test] Use -passes=instsimplify instead of -instsimplify in a number of tests. NFC
Another step moving away from the deprecated syntax of specifying
pass pipeline in opt.
Differential Revision: https://reviews.llvm.org/D119080
Nikita Popov [Mon, 7 Feb 2022 13:22:34 +0000 (14:22 +0100)]
[OMPIRBuilder] Avoid use of getPointerElementType()
Looks like I missed this call when removing others in this file.
Roman Lebedev [Mon, 7 Feb 2022 13:03:40 +0000 (16:03 +0300)]
[LV] Remove `LoopVectorizationCostModel::useEmulatedMaskMemRefHack()`
D43208 extracted `useEmulatedMaskMemRefHack()` from legality into cost model.
What it essentially does is prevents scalarized vectorization of masked memory operations:
```
// TODO: Cost model for emulated masked load/store is completely
// broken. This hack guides the cost model to use an artificially
// high enough value to practically disable vectorization with such
// operations, except where previously deployed legality hack allowed
// using very low cost values. This is to avoid regressions coming simply
// from moving "masked load/store" check from legality to cost model.
// Masked Load/Gather emulation was previously never allowed.
// Limited number of Masked Store/Scatter emulation was allowed.
```
While i don't really understand about what specifically `is completely broken`
was talking about, i believe that at least on X86 with AVX2-or-later,
this is no longer true. (or at least, i would like to know what is still broken).
So i would like to follow suit after D111460, and like wise disable that hack for AVX2+.
But since this was added for X86 specifically, let's just instead completely remove this hack.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D114779
Kadir Cetinkaya [Mon, 7 Feb 2022 12:12:01 +0000 (13:12 +0100)]
[clang][Lexer] Fix tests after
ff77071a4d67
Simon Pilgrim [Mon, 7 Feb 2022 12:58:33 +0000 (12:58 +0000)]
[X86][SSE] Add some initial PAVGB/PAVGW tests
Once D119073 has landed, I'll start addressing these
Florian Hahn [Mon, 7 Feb 2022 12:08:49 +0000 (12:08 +0000)]
[LV] Modernize some runtime check tests a bit.
Update tests to check runtime checks a bit more precisely.
LLVM GN Syncbot [Mon, 7 Feb 2022 11:59:15 +0000 (11:59 +0000)]
[gn build] Port
c63522e6ba77
Balázs Kéri [Mon, 7 Feb 2022 08:56:24 +0000 (09:56 +0100)]
[clang-tidy] Add new check 'shared-ptr-array-mismatch'.
Reviewed By: LegalizeAdulthood
Differential Revision: https://reviews.llvm.org/D117306
Rainer Orth [Mon, 7 Feb 2022 11:43:56 +0000 (12:43 +0100)]
[DebugInfo][test] XFAIL DebugInfo/Generic/missing-abstract-variable.ll on SPARC
`DebugInfo/Generic/missing-abstract-variable.ll` `FAIL`s on SPARC. When
`x` is inlined into `a`, the variable `s` is elided completely, so the
corresponding `CHECK`s fail. Exactly the same happens on RISCV and the
test has already been `XFAIL`ed there.
This patch does the same on SPARC.
Tested on `sparcv9-sun-solaris2.11`.
Differential Revision: https://reviews.llvm.org/D119122
Nikita Popov [Mon, 7 Feb 2022 11:39:35 +0000 (12:39 +0100)]
[Bitcode] Replace assertion with check
Nikita Popov [Mon, 7 Feb 2022 11:37:21 +0000 (12:37 +0100)]
[Bitcode] Add missing test file
This was supposed to be part of
ec18030f5fc1f4a08326e65fe06c6f265a829f4c.
Nikita Popov [Mon, 7 Feb 2022 11:26:12 +0000 (12:26 +0100)]
[Bitcode] Handle invalid data layout gracefully
Valentin Clement [Mon, 7 Feb 2022 11:18:24 +0000 (12:18 +0100)]
[flang] Handle character constant for error code in STOP stmt
Handle character constant ofr error code in the STOP statement.
Depends on D118992
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: kiranchandramohan, schweitz
Differential Revision: https://reviews.llvm.org/D118993
Valentin Clement [Mon, 7 Feb 2022 11:17:02 +0000 (12:17 +0100)]
[flang] Add lowering for ASCII character constant
Lower character constant of KIND = 1 with the
`createStringLiteral` helper function.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: kiranchandramohan, schweitz
Differential Revision: https://reviews.llvm.org/D118992
Nikita Popov [Mon, 7 Feb 2022 10:51:19 +0000 (11:51 +0100)]
[Bitcode] Guard against out of bounds value reference
We should make sure that the value ID is in bounds, otherwise
we will assert / read out of bounds.
Nikita Popov [Mon, 7 Feb 2022 10:43:29 +0000 (11:43 +0100)]
[Bitstream] Check that there is enough space for blob
Instead of simply assuming that it will be zero. I double checked
that the bitstream reader doesn't have any special handling for
all-zero blobs, it will always write out the full contents.
Nikita Popov [Mon, 7 Feb 2022 10:15:43 +0000 (11:15 +0100)]
[Bitcode] Don't assert on invalid attribute group record
Report an error instead.
Nikita Popov [Mon, 7 Feb 2022 09:56:14 +0000 (10:56 +0100)]
[Bitstream] Reject implausibly large reservations
If we're trying to reserve more memory than bits in the stream,
reject this early to avoid OOM.
Valentin Clement [Mon, 7 Feb 2022 10:40:37 +0000 (11:40 +0100)]
[flang] Remove unused converter for now
AbstractConverter private variable is currently not used
and triggers a buildbot failure.
https://lab.llvm.org/buildbot/#/builders/180/builds/3119
This fixes the buildbot.
Sven van Haastregt [Mon, 7 Feb 2022 10:54:55 +0000 (10:54 +0000)]
[OpenCL] opencl-c.h: make attribute order consistent; NFC
For most builtins, `__purefn` always comes after `__ovld`, but the
read_image functions did not follow this pattern.
Igor Kirillov [Fri, 4 Feb 2022 13:26:10 +0000 (13:26 +0000)]
[OpenMP] kmp_atomic_float10_max_min.c test should only be executed on x86 platform
Differential Revision: https://reviews.llvm.org/D118988
Dimitry Andric [Fri, 4 Feb 2022 20:53:09 +0000 (21:53 +0100)]
[TSan] Handle FreeBSD specific indirection of libpthread functions
Similar to
60cc1d3218fc for NetBSD, add aliases and interceptors for the
following pthread related functions:
- pthread_cond_init(3)
- pthread_cond_destroy(3)
- pthread_cond_signal(3)
- pthread_cond_broadcast(3)
- pthread_cond_wait(3)
- pthread_mutex_init(3)
- pthread_mutex_destroy(3)
- pthread_mutex_lock(3)
- pthread_mutex_trylock(3)
- pthread_mutex_unlock(3)
- pthread_rwlock_init(3)
- pthread_rwlock_destroy(3)
- pthread_rwlock_rdlock(3)
- pthread_rwlock_tryrdlock(3)
- pthread_rwlock_wrlock(3)
- pthread_rwlock_trywrlock(3)
- pthread_rwlock_unlock(3)
- pthread_once(3)
- pthread_sigmask(3)
In FreeBSD's libc, a number of internal aliases of the pthread functions
are invoked, typically with an additional prefixed underscore, e.g.
_pthread_cond_init() and so on.
ThreadSanitizer needs to intercept these aliases too, otherwise some
false positive reports about data races might be produced.
Reviewed By: dvyukov
Differential Revision: https://reviews.llvm.org/D119034
Simon Pilgrim [Mon, 7 Feb 2022 09:58:47 +0000 (09:58 +0000)]
[DAG] visitINSERT_VECTOR_ELT - break if-else chain as they both return (style). NFC.
Simon Pilgrim [Mon, 7 Feb 2022 09:54:34 +0000 (09:54 +0000)]
[X86] combineShiftRightArithmetic - break if-else chain as they all return (style). NFC.
Simon Pilgrim [Mon, 7 Feb 2022 09:50:09 +0000 (09:50 +0000)]
[GlobalISel] Move getOpcode() calls inside assert() to avoid (void)s. NFC.
Tidier solution to the unused variable warnings - we already do this in other places in this file.
Zi Xuan Wu [Mon, 7 Feb 2022 09:26:13 +0000 (17:26 +0800)]
[CSKY] Add inline asm constraints and related codegen support
There are kinds of inline asm constraints and corresponding register class or register as following.
'b': mGPRRegClass
'v': sGPRRegClass
'w': sFPR32RegClass or sFPR64RegClass
'c': C register
'z': R14 register
'h': HI register
'l': LO register
'y': HI or LO register
It also adds codegen test for inline-asm including constraints, clobbers and abi names.
Simon Pilgrim [Mon, 7 Feb 2022 09:43:32 +0000 (09:43 +0000)]
[X86] Add fp80 copysign test coverage
Add PR41749 test coverage
Djordje Todorovic [Mon, 7 Feb 2022 09:37:55 +0000 (10:37 +0100)]
[SLPVectorizer] Fix "unused variable" build warning
Nikita Popov [Mon, 7 Feb 2022 09:34:34 +0000 (10:34 +0100)]
[Bitcode] Handle invalid abbrev number error more gracefully
Avoid report_fatal_error(), propagate the error upwards instead.
Nikita Popov [Fri, 4 Feb 2022 14:28:44 +0000 (15:28 +0100)]
[Bitcode] Add fuzzer for bitcode reading
Inspired by the discussion on D118694, this adds a straightforward
fuzzer for bitcode reading. Currently it will very quickly run into
OOM, because we do unconditional vector reservations with
user-provided sizes.
Brad Smith [Mon, 7 Feb 2022 09:04:39 +0000 (04:04 -0500)]
[Driver][OpenBSD] -r: imply -nostdlib like GCC
Similar to D116843 for Gnu.cpp
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D119071
Mariya Podchishchaeva [Thu, 3 Feb 2022 15:37:48 +0000 (18:37 +0300)]
[SYCL] Disallow explicit casts between mismatching address spaces
Reviewed By: bader
Differential Revision: https://reviews.llvm.org/D118935
Djordje Todorovic [Mon, 7 Feb 2022 08:32:09 +0000 (09:32 +0100)]
[GlobalIsel] Fix another "unused variable" warning
Djordje Todorovic [Mon, 7 Feb 2022 08:24:59 +0000 (09:24 +0100)]
Fix the warning after D118805
A variable was used within assert() only.
Valentin Clement [Fri, 4 Feb 2022 10:58:06 +0000 (11:58 +0100)]
[flang] Add test for quiet with local variable in STOP stmt
Depends on D118978.
Differential Revision: https://reviews.llvm.org/D118982
Valentin Clement [Mon, 7 Feb 2022 08:12:17 +0000 (09:12 +0100)]
[flang] Basic local variable lowering
This patch add lowering for simple local variable.
- The signatures in `ConvertType.h` have been simplified to take advantage of the `AbstractConverter`.
- The lowering make use of the `allocateLocal` from the `FirOpBuilder`.
This lowering is used in patch D118982
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: kiranchandramohan, jeanPerier, schweitz
Differential Revision: https://reviews.llvm.org/D118978
Luo, Yuanke [Mon, 7 Feb 2022 07:58:45 +0000 (15:58 +0800)]
[X86] Add test cases for fmul/fdiv with select.
Jun Zhang [Mon, 7 Feb 2022 04:04:13 +0000 (12:04 +0800)]
[NFC][Analyzer] Use range based for loop.
Use range base loop loop to improve code readability.
Differential Revision: https://reviews.llvm.org/D119103
luxufan [Tue, 25 Jan 2022 16:08:39 +0000 (00:08 +0800)]
[JITLink] Fix the incorrect relocation behavior for R_RISCV_BRANCH
In D116573, the relocation behavior of R_RISCV_BRANCH didn't consider that branch instruction like 'bge' has a branch target address which is given as a PC-relative offset, sign-extend and multiplied by 2.
Although the target address is a 12-bits number, acctually its range is [-4096, 4094].
This patch fix it.
Differential Revision: https://reviews.llvm.org/D118151
Kazu Hirata [Mon, 7 Feb 2022 06:18:35 +0000 (22:18 -0800)]
[llvm] Use = default (NFC)
Chuanqi Xu [Mon, 7 Feb 2022 04:47:14 +0000 (12:47 +0800)]
[NFC] Precommit test case for PR53357
zhongyunde 00443407 [Mon, 10 Jan 2022 01:18:57 +0000 (09:18 +0800)]
[DAGCombiner][AArch64] Enhance to support for scalar CSINC
Enhance to fold csel into csinc instruction.
Fix https://github.com/llvm/llvm-project/issues/53071
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D116915
Phoebe Wang [Mon, 7 Feb 2022 01:22:19 +0000 (09:22 +0800)]
[X86] Add pre-commit test for bit test optimization. NFC
Jacques Pienaar [Mon, 7 Feb 2022 01:21:48 +0000 (17:21 -0800)]
[mlir][bazel] Update post ControlFlow dialect split
Kazu Hirata [Mon, 7 Feb 2022 00:36:29 +0000 (16:36 -0800)]
[IR] Use default member initialization in GlobalValue (NFC)
Kazu Hirata [Mon, 7 Feb 2022 00:36:27 +0000 (16:36 -0800)]
[Transforms] Use default member initialization in LibCallSimplifier (NFC)
Kazu Hirata [Mon, 7 Feb 2022 00:36:25 +0000 (16:36 -0800)]
[Transforms] Use default member initialization in LoopVersioning (NFC)
Benjamin Kramer [Sun, 6 Feb 2022 13:06:34 +0000 (14:06 +0100)]
[mlir] Use SmallBitVector instead of SmallDenseSet for AffineMap::compressSymbols
This is both more efficient and more ergonomic to use, as inverting a
bit vector is trivial while inverting a set is annoying.
Sadly this leaks into a bunch of APIs downstream, so adapt them as well.
This would be NFC, but there is an ordering dependency in MemRefOps's
computeMemRefRankReductionMask. This is now deterministic, previously it
was dependent on SmallDenseSet's unspecified iteration order.
Differential Revision: https://reviews.llvm.org/D119076
River Riddle [Sun, 6 Feb 2022 23:10:03 +0000 (15:10 -0800)]
[mlir] Fix GpuToLLVM conversion pass after ControlFlow operations were split from Standard
Stella Laurenzo [Sun, 6 Feb 2022 05:50:27 +0000 (21:50 -0800)]
[mlir] Fixup python bindings after splitting cf ops from std.
River Riddle [Fri, 4 Feb 2022 04:59:43 +0000 (20:59 -0800)]
[mlir] Split out a new ControlFlow dialect from Standard
This dialect is intended to model lower level/branch based control-flow constructs. The initial set
of operations are: AssertOp, BranchOp, CondBranchOp, SwitchOp; all split out from the current
standard dialect.
See https://discourse.llvm.org/t/standard-dialect-the-final-chapter/6061
Differential Revision: https://reviews.llvm.org/D118966
Eugene Zhulenev [Sun, 6 Feb 2022 22:38:33 +0000 (14:38 -0800)]
[mlir] Add canonicalizer to remove redundant shape.cstr_broadcastable ops
Depends On D119025
Reviewed By: frgossen
Differential Revision: https://reviews.llvm.org/D119043
Congzhe Cao [Sun, 6 Feb 2022 21:55:20 +0000 (16:55 -0500)]
[LoopInterchange] Support loop interchange with floating point reductions
Enabled loop interchange support for floating point reductions
if it is allowed to reorder floating point operations.
Previously when we encouter a floating point PHI node in the
outer loop exit block, we bailed out since we could not detect
floating point reductions in the early days. Now we remove this
limiation since we are able to detect floating point reductions.
Reviewed By: #loopoptwg, Meinersbur
Differential Revision: https://reviews.llvm.org/D117450
Mehdi Amini [Sun, 6 Feb 2022 19:48:25 +0000 (19:48 +0000)]
Remove dead forward declaration (NFC)
Simon Pilgrim [Sun, 6 Feb 2022 19:40:08 +0000 (19:40 +0000)]
[KnownBits] Add support for X*X self-multiplication (update)
Rename the SelfMultiply argument to make it clearer that the argument must not be undef
Differential Revision: https://reviews.llvm.org/D108992
Simon Pilgrim [Sun, 6 Feb 2022 19:13:11 +0000 (19:13 +0000)]
[InstCombine] Add mul(x,x) tests showing miscompile
As raised by @efriedma on D117995 - the source must not be undef to demand any bits in mul(x,x) other than bit[1]
https://alive2.llvm.org/ce/z/Cxkjen
Craig Topper [Sun, 6 Feb 2022 18:44:05 +0000 (10:44 -0800)]
[DAGCombiner][RISCV] Allow rotates by non-constant to be matched for i32 on riscv64 with Zbb.
rv64izbb has a RORW/ROLW instructions that operate on the lower
32-bits of a 64-bit value and sign extend bit 31 of the result.
DAGCombiner won't match rotate idioms because the i32 type isn't Legal
on riscv64.
This patch teaches DAGCombiner to allow it if the type is going to
be promoted and the target has Custom type legalization for ISD::ROTL
or ISD::ROTR. I've restricted this to scalar types. It doesn't appear
any in tree targets other than riscv64 have custom type legalization
for rotates.
If this patch isn't acceptable, I guess I can match SRLW, SLLW, and OR
after type legalization, but I'd like to avoid that if possible.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D119062
Kazu Hirata [Sun, 6 Feb 2022 18:54:48 +0000 (10:54 -0800)]
[llvm] Fix header guards (NFC)
Identified with llvm-header-guard.
Kazu Hirata [Sun, 6 Feb 2022 18:54:46 +0000 (10:54 -0800)]
[Breakpoint] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
Kazu Hirata [Sun, 6 Feb 2022 18:54:44 +0000 (10:54 -0800)]
[CodeGen] Use = default (NFC)
Identified with modernize-use-equals-default
Kazu Hirata [Sun, 6 Feb 2022 18:54:42 +0000 (10:54 -0800)]
[Driver] Remove redundant string initialization (NFC)
Identified with readability-redundant-string-init.
Jared Irwin [Sun, 6 Feb 2022 17:36:12 +0000 (12:36 -0500)]
[lld-macho] Add -pagezero_size
Adds `-pagezero_size`. `-pagezero_size` commonly used for kernel development.
`-pagezero_size` changes the `__PAGEZERO` size, removing that segment if it is set to zero.
One of the four flags from {D118570}
Now with error messages and tests.
Differential Revision: https://reviews.llvm.org/D118724
Bjorn Pettersson [Wed, 2 Feb 2022 09:20:00 +0000 (10:20 +0100)]
[DAGCombiner] Fold SSHLSAT/USHLSAT to SHL when no saturation will occur
When the shift amount is known and a known sign bit analysis of
the shiftee indicates that no saturation will occur, then we can
replace SSHLSAT/USHLSAT by SHL.
Differential Revision: https://reviews.llvm.org/D118765
Bjorn Pettersson [Wed, 2 Feb 2022 09:08:26 +0000 (10:08 +0100)]
Pre-commit test cases for DAG combine folds of SSHLSAT/USHLSAT -> SHL
It should be possible to replace SSHLSAT and USHLSAT with SHL when
it is known that no saturation will take place (e.g. by analysing
known sign bits in the first shift operand).
Differential Revision: https://reviews.llvm.org/D118764
Simon Pilgrim [Sun, 6 Feb 2022 17:19:23 +0000 (17:19 +0000)]
Revert rG7275de7fb2f087871611d037d1b529b226dd0521 "[AArch64] translateLocChar - silence dead code warning"
Seems to cause some buildbot misbehaviour (+ there's a dumb copy+paste typo in the commit message....)
Simon Pilgrim [Sun, 6 Feb 2022 17:17:28 +0000 (17:17 +0000)]
[clang][CodeGen] Add _BitInt test coverage to builtins-elementwise-math.c
As suggested on D117898, we should be testing irregular _BitInt types with the __builtin_elementwise_* intrinsics
Simon Pilgrim [Sun, 6 Feb 2022 16:52:23 +0000 (16:52 +0000)]
Fix Wdocumentation unknown parameter warning
Florian Hahn [Sun, 6 Feb 2022 16:37:20 +0000 (16:37 +0000)]
[LV] Use VPReplicateRecipe::isUniform instead isUniformAfterVec (NFCI).
In scalarizeInstruction(), isUniformAfterVectorization is used to detect
cases where it is sufficient to always access the first lane. This
should map directly checking whether the operand is a uniform replicate
recipe.
Differential Revision: https://reviews.llvm.org/D116654
Simon Pilgrim [Sun, 6 Feb 2022 16:32:16 +0000 (16:32 +0000)]
[AArch64] translateLocChar - silence dead code warning
Remove default case from switch and return None after the switch()
Simon Pilgrim [Sun, 6 Feb 2022 16:29:38 +0000 (16:29 +0000)]
[AArch64] LowerVectorSRA_SRL_SHL - silence dead code warning
Remove default case from switch and move llvm_unreachable to after the switch()
Simon Pilgrim [Sun, 6 Feb 2022 16:25:44 +0000 (16:25 +0000)]
[Support] Use llvm_unreachable instead of LLVM_BUILTIN_UNREACHABLE internal define
David Green [Sun, 6 Feb 2022 16:17:06 +0000 (16:17 +0000)]
[ARM] Mark i64 and f64 shuffles as Custom for MVE
This way they get lowered through the ARMISD::BUILD_VECTOR, which can
produce more efficient D register moves.
Also helps D115653 not get stuck in a loop.
David Green [Sun, 6 Feb 2022 14:12:28 +0000 (14:12 +0000)]
[ARM] Add extra vabd, vhadd and vmulh tests. NFC
This is some extra testing for vabd, vhadd and vmulh. Some of the tests
have also be reordered.
Simon Pilgrim [Sun, 6 Feb 2022 12:53:11 +0000 (12:53 +0000)]
[X86] Fold ZERO_EXTEND_VECTOR_INREG(BUILD_VECTOR(X,Y,?,?)) -> BUILD_VECTOR(X,0,Y,0)
Helps avoid some unnecessary shift by splat amount extensions before shuffle combining gets limited by with one use checks
Fangrui Song [Sun, 6 Feb 2022 07:34:14 +0000 (23:34 -0800)]
[ELF] Fix crash when an input is incompatible with a lazy object file
The diagnostic is concise. It is ok because the case is rare.
Stella Laurenzo [Sun, 6 Feb 2022 06:04:19 +0000 (22:04 -0800)]
[mlir] Do not use an empty source file when building aggregate libraries.
See discussion: https://discourse.llvm.org/t/check-mlir-times-examples-standalone-testing-time/6073/7
It turns out that it has been legal since CMake 3.11 to omit sources at library creation time if they are added later via target_sources, as is done here. This side-steps the issue of having a file that changes and invalidates the build of leaves.
Differential Revision: https://reviews.llvm.org/D119069
Rong Xu [Fri, 4 Feb 2022 20:23:47 +0000 (12:23 -0800)]
[SampleFDO] Enable FSAFDO loading passes if --enable-fs-discriminator is enabled
FSAFDO profile loader is currently disabled even --enable-fs-discriminator is enabled.
They need to be turned on by options which makes it cumbersome for experiments.
This patch changes the FSAFDO profile loader enabled by default. Since they are
guarded by EnableFSDiscriminator, they will only be turned on if
--enable-fs-discriminator is enabled. Note that --enable-fs-discriminator is
still disabled by default.
Differential Revision: https://reviews.llvm.org/D119033