review.tizen.org Git - platform/upstream/mesa.git/log

ci/lima: EGL testing was disabled when fp16 fail was removed

fd4d0e1cc23f ("st/mesa: Set gl_config.floatMode based on color_format"),
fixed this functionality across multiple drivers, but EGL testing on
Mali was disabled back then, theofore it still fails here.

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>

ci/radeonsi: stoney arb_timer_query got fixed between kernel 6.3.1..13

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>

Revert "lima/ci: temporarily disable deqp-egl tests due to timeouts"

This reverts commit be2619766be3f4ee0b22a10f8db179dc1e3c5773.

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>

ci/freedreno: add fails introduced by upreving to 6.3.13

Some of these fails/crashes was already present when trying 6.3.4,
two disappeared, one new crash appeared. Identical `.config`.

See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9247

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>

ci: update kernel to 6.3.13

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>

ci: build kernel in gfx-ci/linux and just use binaries in Mesa3D CI

This bring visible speedup while preparing the rootfs and containers.

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24079>

nir: Devendor load_sample_mask

AGX will use this too for its MSAA lowerings.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24148>

nir: Add fence_{pbe,mem}_to_tex(_pixel)_agx intrinsics

Read-after-write hazards require special handling on AGX, since image loads are
implemented with texturing. Add intrinsics to handle these hazards.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24148>

nv50/ir: Support vector movs

nir_opt_mov and nir_op_vecN are only the same if the mov is only a
single component. Otherwise the vec loop will try to access src[c]
where c > 0 which breaks for nir_op_mov. It's uncommon but scalar
back-ends can see vector movs so we need to handle this correctly.

Fixes: 6513c675ad31 ("nv50/ir/nir: implement nir_alu_instr handling")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24167>

glx: Assign unique serial number to GLXBadFBConfig error

Fixes: e89e1f5049d ("glx: Fix error handling yet again in CreateContextAttribs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9171
Tested-by: yan12125
Co-authored-by: XRevan86
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23762>

radeonsi: prefix function with si_ to prevent name collision

Fixed a build error caused by multiple gfx11_init_query symbols when building with iris and radeonsi specified in gallium-drivers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9238
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24045>

isl: Disable MCS compression just on ACM platform

We're still seeing failures with render target reads of multisampled
images on Alchemist platforms, but Meteorlake doesn't appear to have
that issue. Enable MCS on Meteorlake.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22802>

intel/compiler: Look at 2 register worth of data instead of 4

Sampler always writes 4/8 register worth of data but for ld_mcs only
valid data is in first two register. So with 16-bit payload, we need to
split 2-32bit registers into 4-16-bit payload.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22802>

iris: migrate WA 14016118574 to use the WA framework

Fixes: 58829d9f1 ("iris: implement Wa_14016118574")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24156>

iris: migrate WA 14013910100 to use the WA framework

Fixes: eeb3f4594d5 ("intel/xehp: Implement XeHP workaround Wa_14013910100.")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24156>

Update radeon_vcn_enc.c

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24151>

radeonsi: enable vcn encoder rgb input support

v2: use luma pitch when chroma not available (Ruijing)

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24151>

Revert "ac/nir/ngg: Follow intrinsic sources when analyzing before culling."

This reverts commit 411f69b9c5b884f6802758347e72a10ec5564df1.

It broke tessellation in Unigine Heaven with radeonsi.

Fixes: 411f69b9c5b884 - ac/nir/ngg: Follow intrinsic sources when analyzing before culling.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24160>

radeonsi: Use DIV_ROUND_UP instead of ALIGN_POT

DIV_ROUND_UP is the correct replacement for ALIGN_TO.

Fixes: ba83c1e2
Signed-off-by: David Rosca <nowrep@gmail.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24127>

etnaviv: optimize transfers when whole resource level is discarded

Now that all our age tracking is moved to etna_resource_level we can unlock
some more optimizations in the transfers by skipping copies or flushes when
the whole level is discarded.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: optimize render resource update

Now that we track the age at the resource level we can optimize
the render surface update by only copying the single level we are
going to render to.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: keep blit destination tile status valid if possible

If the blit was just a resource flush on a uncompressed buffer we can
keep the tile status as valid, as in that case only clear tiles are filled
in the target buffer, but it doesn't hurt to look at the TS buffer when
fetching from this resource as the tile status matches the content of the
buffer. For compressed formats we can't do the same, as the compressed
tiles are uncompressed when flushing the resource, so the compression tags
don't match the buffer content anymore.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: allow sampler TS even if the resource is flushed

As long as the TS is valid we can use the tile status to optimize the
sample fetch, even if the resource has been flushed for any reason.
Do the check for valid TS first when checking whether to enable sampler
TS to avoid all the other checks when TS isn't usable.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: optimize sampler source update

Now that we track age at the resource level we can optimize
the sampler source update by only copying/flushing the levels
that are actually used by the sampler.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: add tile status buffer status into TS metadata

When the TS is shared all sharing instances must see the same status
information about the resource TS buffer. Add this information to the
shared TS metadata and make it take precedence over the internal
status tracking when the TS is shared.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: move TS meta into etna_resource_level

Handle imports/exports always deal with one specific level of
a resource, so the shared TS metadata should also be per level.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: add helper to set TS validity

Wrap the setting of the resource level TS validity into a
helper function to allow the implementation to change later.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: add helper to get TS validity

Add a small helper to get the validity of the TS buffer for
a resource level. We can drop the ts_size check in several
places, as we never set ts_valid to true if there is no TS
buffer.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: add helper to transfer resource level age to another

Add a small helper to transfer the age (seqno) from one resource level
to another.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: add helper to mark resource level as changed

Add a small helper to mark a resource level as changed so the
seqno handling is hidden.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: add helper to mark resource level as flushed

Add a small helper to mark a resource level as flushed so the
seqno handling is hidden.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: optimize resource copies by skipping clean levels

If we sync/flush a full resource we can skip any level where the
target is of the same age as the source.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: flush destination before executing blit

A blit into a render target may destroy valid TS information, as the
destination TS isn't updated. Flush the blit destination when necessary
to make sure that all pending TS is resolved into the destination before
the blit is executed.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

etnaviv: move resource seqnos to level

Resource maps, blits and surfaces all target a specific level of a
resource, so they can have different ages. Move the seqnos tracking
the age to etna_resource_level.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19964>

ci/etnaviv: update ci expectation

Etnaviv fails in the same way as Lima after the merge of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24157>

ir3: Convert to register intrinsics

Thanks to our SSA-based RA, we only use nir_register for arrays, and we only
access array registers with dedicated moves anyway. So there's no reason to need
any fancy coalescing... we can just switch to register access intrinsics and
translate them to moves exactly like we would've done when getting srcs/dests
before.

This addresses the ir3 portion of #9051.

No shader-db changes with a (significant subset of) Rob's shader-db. (Some
shaders are affected by this change but not in any way that shows up in the
stats.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24126>

ac/llvm: Remove subgroup_id and num_subgroups intrinsics.

We expect that these will be lowered in NIR now.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>

aco: Remove subgroup_id and num_subgroups intrinsics.

These are lowered in NIR now.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>

radeonsi: Use ac_nir_lower_intrinsics_to_args.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>

radeonsi: Move si_select_hw_stage to si_shader_info.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>

radv: Use ac_nir_lower_intrinsics_to_args.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>

radv: Move radv_select_hw_stage to radv_shader_info.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>

ac/nir: Add new pass to lower intrinsics to shader args.

This is beneficial for intrinsics that do an algebraic
instruction such as bitfield extract on shader arguments,
because it allows NIR to be aware of these instructions and
optimize them together with other algebraic instructions in
the shader.

Currently, just handle subgroup_id and num_subgroups intrinsics.
More will be added here in the future.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>

ac/nir: Simplify arg unpacking when shift is zero.

This is so we can just use the same function when it's zero.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>

aco: Fix subgroup_id intrinsic on GFX10.3+.

Change this to match how it works in the LLVM backend.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24005>

pvr: Submit PR commands

This commit adds a partial render command to job submission.
For geom only jobs we must always submit a pr command in case we
enter SPM. For now, for geom+frag jobs, we'll also always submit
a pr command event.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>

pvr: Restructure `rogue_kmd_stream.xml`

Now things are structured in sections, like the other xml files.
And elements within a section are sorted alphabetically.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>

pvr: Remove some magic numbers and increments from km stream

- Update and add csbgen definitions to make the content of the
geom and frag km stream more obvious.

- Replace some of the hard coded constants with defines.

- Adds some static assert to make the provenance of definitions
more clear as well as making sure things fit properly.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>

pvr: Use the SPM EOT on barrier stores

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>

pvr: Compile SPM EOT shader

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>

pvr: Remove mrt setup from SPM EOT

Remove the mrt setup stuff since the EOT program only support
output registers for now. When implementing the tile buffer
support this change can be reverted, or things could be changed
to better fit with how the compiler wants things.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24138>

intel/compiler: remove NV_mesh_shader support

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24071>

anv: drop support for VK_NV_mesh_shader

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24071>

hasvk: remove dead code & comments related to mesh shading

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24071>

iris: avoid duplicating validation entries

If the *first* BO is not marked as "written", but the same BO is marked
as "written" later, then it will be added twice, because the first
instance will have index_for_handle equal to 0.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24108>

pvr: skip setting up SPM consts buffer when no const shared regs are used

This is a temporary measure until the zeroed shaders are replaced with the real
ones. This avoids a VK_ERROR_OUT_OF_DEVICE_MEMORY error due to a zero sized
allocation.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Fixes: 1dfd5351249 ("pvr: Setup SPM background object")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24139>

ntt: Switch to new-style registers and modifiers

Use all the nir_legacy.h features to transition away from the deprecated
structures. shader-db is quite happy. I assume that's a mix of more aggressive
source mod usage and better coalescing (nir-to-tgsi doesn't copyprop).

   total instructions in shared programs: 900179 -> 887156 (-1.45%)
   instructions in affected programs: 562077 -> 549054 (-2.32%)
   helped: 5198
   HURT: 470
   Instructions are helped.

   total temps in shared programs: 91165 -> 91162 (<.01%)
   temps in affected programs: 398 -> 395 (-0.75%)
   helped: 21
   HURT: 18
   Inconclusive result (value mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Tested-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24116>

nir/legacy: Fix handling of fsat(fabs)

Consider code like:

    32x4  %2 = @load_interpolated_input (%1, %0 (0x0)) (base=0, component=0, dest_type=float32, io location=VARYING_SLOT_VAR0 slots=1 mediump)  // Color
    32x4  %3 = fabs %2
    32x4  %4 = fsat %3
    32x4  %5 = fsin %4

The existing logic would incorrectly tell the backend that both fabs and fsat
could be folded, and then half the shader disappears. Whoops. Fix by stopping
the folding in this case. I choose to do this check in the fsat rather than the
fabs because it's more straightforward (1 source vs N uses) but it's somewhat
arbitrary.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24116>

nir/legacy: Fix fneg(load_reg) case

Consider the IR:

   %0 = load_reg
   %1 = fneg %0
   %2 = ffloor %1
   %3 = bcsel .., .., %1

Because the fneg has both foldable and non-foldable users, nir/legacy does not
fold the fneg into the load_reg. This ensures that the backend correctly emits a
dedicated fneg instruction (with the load_reg folded in) for the bcsel to use.
However, because the chasing helpers did not previously take other uses of a
modifier into account, the helpers would fuse in the fneg to the ffloor. Except
that doesn't work, because the load_reg instruction is supposed to be
eliminated. So we end up with broken chased IR:

   1 = fneg r0
   2 = ffloor -NULL
   3 = bcsel, ..., 1

The fix is easy: only fold modifiers into ALU instructions if the modifiers can
be folded away. If we can't eliminate the modifier instruction altogether, it's
not necessarily beneficial to fold it anyway from a register pressure
perspective. So this is probably ok. With that check in place we get correct IR

   1 = fneg r0
   2 = ffloor 1
   3 = bcsel, ..., 1

Fixes carchase/230.shader_test under softpipe.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24116>

zink: remove venus from renderpass optimizations

For venus, need to query the underlying driver.
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/9358

Remove venus for now as it is causing crashes on top of anv/radv.

Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24147>

compiler: Remove blend enums duplicating util

Now unused.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

gallium: Remove pipe->compiler BLEND enum translation

Now unused.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

panfrost: Convert to PIPE_BLEND enums internally

This removes all the users of the compiler enums, and is a lot more natural now
that nir_lower_blend speaks PIPE_BLEND enums.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

nir/lower_blend: Use util enums

This avoids the silly compiler versions. Some bits are slightly more
complicated, because they have to account for inverted enum values (rather than
a separate invert bit), but this is a LOT friendlier to drivers using the pass
and it makes the pass itself more readable.

The conversion functions in panfrost/panvk will go away momentarily.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

lvp: Use common blend/logicop translation

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

vulkan: Add helpers for blend enum translation

Vulkan drivers that use nir_lower_blend need to translate Vulkan enums to the
common (non-Vulkan) versions used in nir_lower_blend. We don't need to duplicate
that boilerplate in every VK driver that uses nir_lower_blend, move panvk's
versions to common code so we can use them in agxv. I suspect powervr wants this
too.

It might be useful to also share the logic to translate vk_color_blend_state
to nir_lower_blend_options wholesale, but panvk wouldn't use it and agxv is
downstream so it wouldn't have any in-tree users. So I'll keep that part
vendored (for now). For now, let's share the easy win of the enum translation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

util/blend: Add helpers for normalizing inverts

To avoid duplicating piles of cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

gallium,util: Move util_blend_dst_alpha_to_one

PanVK will use this too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

gallium,util: Move blend enums to util/

For sharing across the tree.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

gallium/trace: Collect enums from multiple files

We're going to do some code motions out of p_state.h so the one file assumption
will fail. relax it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24076>

docs: truncate feature list for 23.3-devel

Which I forgot to do when branching for 23.2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24143>

afuc: Rework and significantly expand README.rst

This hasn't been updated since the a5xx days, and we've learned much
more since then. I've tried to expand it from a random collection of
notes to a more complete guide to explaining how to read the firmware
and understand the various tricks it uses to make code more compact.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24125>

turnip: Add debug option to allow non-conforming features.

This is because we still may want to be able to expose vulkan 1.3
on some devices that technically do not support it, for instance
the adreno 610 has everything required except multiview, which is
not essential for most games.

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

freedreno: Add support for devices not supporting double thread size.

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

ir3: handle non-uniform case for atomic image/ssbo intrinsics

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

freedreno, turnip: set correct reg_size_vec4 for a6xx_gen1_low

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

turnip: make sampler_minmax support configurable.

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

turnip: Add support for devices not supporting double thread size.

On these devices the actual thread size for compute shaders seems to be
controlled by REG_A6XX_HLSQ_FS_CNTL_0 rather than the CS-related
register.

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

ir3: make wave_granularity configurable

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

ir3: Make FS tex prefetch optimization optional

a610 and friends seem not to have tex prefetch.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

turnip: Make multiview support configurable per generation

a610 and similar models don't have HW support for multiview,
proprietary driver unrolls the drall calls instead.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

freedreno: Add A605, A608, A610, A612 GPUs definition

While we tested a610, a605/a608 are added by observing traces being same
to a610.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

freedreno,turnip: Make VS input attr/binding count configurable

a610 and similar models have fewer VS inputs available.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

freedreno,turnip: Make CS shared memory size configurable

a610 and similar models have less shared memory size.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

freedreno,turnip: Make number of VSC pipes configurable

a610/a608 has less pipes, so we need to make it configurable.

In particular we need to program all of the VSC_PIPE_CONFIG_REG[n]
rather than leaving garbage values for the unused pipes. Pointing
multiple VSC pipes at the same bin makes the hw angry.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

freedreno: Set magic writes per-GPU, using existing data

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

freedreno, turnip: Clarify some RB_CCU_CNTL fields

There is no .gmem field, there is a ccu color cache size field
which tells the size as a fraction of depth cache used in direct
rendering.

There is also GMEM_FAST_CLEAR_DISABLE flag which is set on a608/a610.

Since these values will stop being the same between models,
make them configurable.

Credits to Connor Abbott for deciphering color cache size meaning.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>

anv: hide exec_flags selection inside the i915 backend

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24073>

util: Blake3 - Identify arm64ec as aarch64 instead of x64

ARM64EC is a new build target for Windows ARM64 devices for x64 support.
Currently that build flavor fails due to attempting to use x64 intrinsics.
This commit fixes it by changing the auto-detection to be aarch64
instead of x64 for arm64ec.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24119>

crocus: Avoid fast-clear with incompatible view

Port of code from iris.
Original author: Nanley Chery

Helps with fast_color_clear@fcc-write-after-clear

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24135>

freedreno/cffdec: Decode CP_DRAW_AUTO

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24074>

r300: update RV370 failures

This was missed in 0bf6dcb785ce82006f9757217153735e39127834
There is a loop which iterates over a temp array. NIR optimization
moves the real work out of the loop and what remains are just ALU ops
with undefs. So after converting undefs to zero, the ALU ops are
optimized out and DCE kills the loop. This is a good thing in
general and we don't fail the linking due to the loop presence.

However than we hit the shader constants and ALU limits later :-(
So from dEQP POW we go from NotSupported to Fail.

Fixes: 0bf6dcb785ce82006f9757217153735e39127834
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24134>

pvr: clang-format fixes

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24070>

isl: Set MOCS to uncached for MTL stream-out

Without this change various OpenGL CTS tranform feedback tests were
failing.

Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>

isl/dev: Add uncached MOCS value

Rework:
* Jordan: Add uncached for all platforms (Requested by Francisco)
* Jordan: Use gen7 & gen8 values suggested by Francisco
* Jordan: Fix IVB and CHV MOCS mistakes pointed out by Francisco

Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>

genxml/chv: Add MEMORY_OBJECT_CONTROL_STATE_CHV to document compared to BDW

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>

genxml/hsw: Add additional MOCS field enumerations

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>

anv,iris,hasvk: Use ISL_SURF_USAGE_STREAM_OUT_BIT for setting stream-out MOCS

Cc: 23.2 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23823>