platform/kernel/u-boot.git
8 years agomkimage: Fix munmap() call when importing data
Simon Glass [Wed, 16 Mar 2016 13:45:31 +0000 (07:45 -0600)]
mkimage: Fix munmap() call when importing data

The munmap() call unmaps the wrong memory buffer. Fix it.

Reported-by: Coverity (CID: 138505)
Reported-by: Coverity (CID: 138495)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoFix spelling of "transferred".
Vagrant Cascadian [Tue, 15 Mar 2016 19:16:39 +0000 (12:16 -0700)]
Fix spelling of "transferred".

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoFix spelling of "supported/unsupported".
Vagrant Cascadian [Tue, 15 Mar 2016 19:11:13 +0000 (12:11 -0700)]
Fix spelling of "supported/unsupported".

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
8 years agoFix spelling of "comment".
Vagrant Cascadian [Tue, 15 Mar 2016 19:11:12 +0000 (12:11 -0700)]
Fix spelling of "comment".

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agocmd: Fix license command
Tom Rini [Tue, 15 Mar 2016 16:49:12 +0000 (12:49 -0400)]
cmd: Fix license command

The license command isn't usually built and has a few problems:
- The rules to generate license.h haven't worked in a long time,
  re-write these based on the bmp_logo.h rules.
- 'tok' is unused and the license text size has increased
- bin2header.c wasn't grabbing unistd.h to know the prototype for
  read().

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agoserial: pl01x: Add support for devices with the rate pre-configured.
Eric Anholt [Mon, 14 Mar 2016 01:16:54 +0000 (18:16 -0700)]
serial: pl01x: Add support for devices with the rate pre-configured.

For Raspberry Pi, we had the input clock rate to the pl011 fixed in
the rpi.c file, but it may be changed by firmware due to user changes
to config.txt.  Since the firmware always sets up the uart (default
115200 output unless the user changes it), we can just skip our own
uart init to simplify the boot process and more reliably get serial
output.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
8 years agoDrop various features when the command line is not available
Simon Glass [Mon, 14 Mar 2016 01:07:35 +0000 (19:07 -0600)]
Drop various features when the command line is not available

Some features are only useful or meaningful when the command line is
present. Ensure that these features are not compiled in when CONFIG_CMDLINE
is not enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoAllow command-line files to be dropped
Simon Glass [Mon, 14 Mar 2016 01:07:34 +0000 (19:07 -0600)]
Allow command-line files to be dropped

These files do not need to be compiled when CONFIG_CMDLINE is disabled.
Update the Makefile to reflect this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoAllow command code to compile to nothing
Simon Glass [Mon, 14 Mar 2016 01:07:33 +0000 (19:07 -0600)]
Allow command code to compile to nothing

When CONFIG_CMDLINE is disabled we need to remove all the command-line
code. Most can be removed by dropping the appropriate linker lists from the
images, but sub-commands must be dealt with specially.

A simple mechanism is used to avoid 'unused static function' errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoPanic when no command line processing can be performed
Simon Glass [Mon, 14 Mar 2016 01:07:32 +0000 (19:07 -0600)]
Panic when no command line processing can be performed

Normally board_run_command() will handle command processed. But if for some
reason it returns then we should panic to avoid further processing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agosandbox: Avoid calling commands when not available
Simon Glass [Mon, 14 Mar 2016 01:07:30 +0000 (19:07 -0600)]
sandbox: Avoid calling commands when not available

Don't try to run commands when not supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoarm: x86: Drop command-line code when CONFIG_CMDLINE is disabled
Simon Glass [Mon, 14 Mar 2016 01:07:29 +0000 (19:07 -0600)]
arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled

Update the link script to drop this code when not needed. This is only done
for two architectures at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoAdd an option to enable the command line
Simon Glass [Mon, 14 Mar 2016 01:07:28 +0000 (19:07 -0600)]
Add an option to enable the command line

Add a new Kconfig option for the command line. This is enabled by default,
but when disabled it will remove the command line.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agocbfs: Update a function to be static
Simon Glass [Mon, 14 Mar 2016 01:07:27 +0000 (19:07 -0600)]
cbfs: Update a function to be static

All command functions should be static. Update the CBFS functions to follow
this rule.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoti: k2g: increase phy autoneg timeout
Vitaly Andrianov [Fri, 11 Mar 2016 13:23:04 +0000 (08:23 -0500)]
ti: k2g: increase phy autoneg timeout

After power cycle of a K2G EVM dhcp fails due to a auto-negotiation
timeout. This commit increases the timeout to fix the issue.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Tom Rini [Tue, 22 Mar 2016 16:14:27 +0000 (12:14 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

8 years agodriver: net: fsl-mc: Return from DPAA_exit if boot_status !=0
Prabhakar Kushwaha [Mon, 21 Mar 2016 08:49:39 +0000 (14:19 +0530)]
driver: net: fsl-mc: Return from DPAA_exit if boot_status !=0

Return value of get_mc_boot_status() in case of failure is not necessary
to be -1.

So update the error condition check.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reported-by: Yao Yuan <yao.yuan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8/ls1043aqds: Enable ID_EEPROM support for ls1043aqds
Wenbin Song [Wed, 9 Mar 2016 05:38:25 +0000 (13:38 +0800)]
armv8/ls1043aqds: Enable ID_EEPROM support for ls1043aqds

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8/ls1043aqds: Return i2c mux to default chennel
Wenbin Song [Wed, 9 Mar 2016 05:38:24 +0000 (13:38 +0800)]
armv8/ls1043aqds: Return i2c mux to default chennel

Return i2c mux to the default channel after accessing retimer.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agofreescale: vid: Return i2c mux to default channel
Wenbin Song [Wed, 9 Mar 2016 05:38:23 +0000 (13:38 +0800)]
freescale: vid: Return i2c mux to default channel

IR chip is on one of the channels on multiplexed I2C-bus.
Reset to default channel after accessing.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarm: ls102xa: Enable CONFIG_SYS_CONSOLE_IS_IN_ENV support
Alison Wang [Tue, 8 Mar 2016 03:59:59 +0000 (11:59 +0800)]
arm: ls102xa: Enable CONFIG_SYS_CONSOLE_IS_IN_ENV support

CONFIG_SYS_CONSOLE_IS_IN_ENV needs to be enabled, so we could set stdout
environment variable to specify the vga for the console output when
LCD/HDMI is connected to the boards.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8/fsl-lsch2: fix sdhc clock frequency value
Yangbo Lu [Tue, 16 Feb 2016 02:54:41 +0000 (10:54 +0800)]
armv8/fsl-lsch2: fix sdhc clock frequency value

The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock frequency value that's calculated for eSDHC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2085a: Remove phy configuration from QDS and RDB
Prabhakar Kushwaha [Wed, 24 Feb 2016 11:32:32 +0000 (17:02 +0530)]
armv8: ls2085a: Remove phy configuration from QDS and RDB

As phy_connect and phy_config are being called from DPAA2 driver.
Remove calling of mentioned function from board file.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver: net: ldpaa_eth: Add support of PHY framework
Prabhakar Kushwaha [Wed, 24 Feb 2016 11:32:11 +0000 (17:02 +0530)]
driver: net: ldpaa_eth: Add support of PHY framework

This patch integrate DPAA2 ethernet driver existing PHY framework.

Call phy_connect and phy_config as per available DPMAC id defined
in SerDes Protcol.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: Updating entries in Serdes Table
Pratiyush Srivastava [Fri, 18 Mar 2016 11:44:19 +0000 (17:14 +0530)]
armv8: fsl-layerscape: Updating entries in Serdes Table

The serdes protocol entries in  Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver/ddr/fsl: Add workaround for erratum A-009803
Shengzhou Liu [Thu, 10 Mar 2016 09:36:57 +0000 (17:36 +0800)]
driver/ddr/fsl: Add workaround for erratum A-009803

During initial DDR training, false parity errors may be detected.
This patch adds workaround to fix the erratum.
Tested on LS2085QDS and LS2080RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete
Shengzhou Liu [Thu, 10 Mar 2016 09:36:56 +0000 (17:36 +0800)]
driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete

Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig,
e.g. hwconfig=fsl_ddr:parity=on.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agopci/layerscape: set LUT and msi-map for discovered PCI devices
Stuart Yoder [Thu, 10 Mar 2016 16:52:30 +0000 (10:52 -0600)]
pci/layerscape: set LUT and msi-map for discovered PCI devices

msi-map properties are used to tell an OS how PCI requester IDs are
mapped to ARM SMMU stream IDs.

for all PCI devices discovered in a system:
  -allocate a LUT (look-up-table) entry in that PCI controller
  -allocate a stream ID for the device
  -program and enable a LUT entry (maps PCI requester id to stream ID)
  -set the msi-map property on the controller reflecting the
   LUT mapping

basic bus scanning loop/logic was taken from drivers/pci/pci.c
pci_hose_scan_bus().

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agopci/layerscape: add defines for LUT
Stuart Yoder [Thu, 10 Mar 2016 16:52:24 +0000 (10:52 -0600)]
pci/layerscape: add defines for LUT

The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
that maps PCI requester IDs (bus/dev/fun) to a stream ID.

Add defines for the register offsets.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agopci: make pci_get_hose_head() available to external users
Stuart Yoder [Thu, 10 Mar 2016 16:52:18 +0000 (10:52 -0600)]
pci: make pci_get_hose_head() available to external users

Put pci_get_hose_head() prototype in header so it is available to
external users, allowing them to find and iterate over all pci
controllers.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080a: update stream ID partitioning info
Stuart Yoder [Thu, 10 Mar 2016 16:52:07 +0000 (10:52 -0600)]
armv8: ls2080a: update stream ID partitioning info

Update comments around how stream IDs are partitioned.
Stream IDs allocated to PCI are no longer divided up by
controller, but are instead a contiguous range

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080a: remove obsolete stream ID partitioning support
Stuart Yoder [Thu, 10 Mar 2016 16:52:01 +0000 (10:52 -0600)]
armv8: ls2080a: remove obsolete stream ID partitioning support

Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoboards: ls2080: Fix default bootargs
York Sun [Mon, 29 Feb 2016 23:58:20 +0000 (15:58 -0800)]
boards: ls2080: Fix default bootargs

A white space is missing in multiple-line string for bootargs.

Signed-off-by: York Sun <york.sun@nxp.com>
8 years agoarm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPAT
Alison Wang [Mon, 29 Feb 2016 06:50:20 +0000 (14:50 +0800)]
arm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPAT

As the compatible property values for QSPI and DSPI dts nodes
are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT
need to be updated too.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/crypto/fsl: define structures for PDB
Aneesh Bansal [Mon, 15 Feb 2016 09:42:57 +0000 (15:12 +0530)]
drivers/crypto/fsl: define structures for PDB

Structures are defined for PDB (Protocol Data Blcks) for various
operations. These structure will be used to add PDB data while
creating the PDB descriptors.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
CC: Ulises Cardenas <raul.casas@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/crypto/fsl: add constructs for protocol descriptors
Aneesh Bansal [Mon, 15 Feb 2016 09:42:56 +0000 (15:12 +0530)]
drivers/crypto/fsl: add constructs for protocol descriptors

Construct APIs are added to create Protocol Descriptors for
CAAM block.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
CC: Ulises Cardenas <raul.casas@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/crypto/fsl: correct error checking in run_descriptor
Aneesh Bansal [Thu, 11 Feb 2016 09:06:51 +0000 (14:36 +0530)]
drivers/crypto/fsl: correct error checking in run_descriptor

When CAAM runs a descriptor and an error occurs, a non-zero
value is set in Output Status Register. The if condition should
check the status for a non-zero value.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
Shaohui Xie [Thu, 28 Jan 2016 07:38:15 +0000 (15:38 +0800)]
armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY

To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: lsch3: Enable WUO config for RNI-20 node
Prabhakar Kushwaha [Mon, 25 Jan 2016 06:38:45 +0000 (12:08 +0530)]
armv8: lsch3: Enable WUO config for RNI-20 node

Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.

WRIOP IP is connected to RNI-20 Node.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarm64: Fix layerscape mmu setup
Alexander Graf [Mon, 21 Mar 2016 19:26:12 +0000 (20:26 +0100)]
arm64: Fix layerscape mmu setup

With commit 7985cdf we converted all systems except for the Layerscape
SoCs to the generic descriptor table based page table setup.

On the Layerscape SoCs however, we just provide an empty table stub
and do the setup ourselves. To reserve enough memory for the tables,
we need to override the default counting mechanism which would end up
with an empty table because we have no maps.

Fixes: 7985cdf
Reported-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agostrider: use optimised bus timing for FPGA access
Reinhard Pfau [Wed, 16 Mar 2016 08:20:13 +0000 (09:20 +0100)]
strider: use optimised bus timing for FPGA access

Use optimised bus timing for FPGA access.

Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
8 years agostrider: Define pca593x widths
Dirk Eibach [Wed, 16 Mar 2016 08:20:12 +0000 (09:20 +0100)]
strider: Define pca593x widths

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
8 years agostrider: Add DP501 support for cpu model
Dirk Eibach [Wed, 16 Mar 2016 08:20:11 +0000 (09:20 +0100)]
strider: Add DP501 support for cpu model

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Sun, 20 Mar 2016 22:09:34 +0000 (18:09 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

8 years agoarm: socfpga: sr1500: Misc updates (SPI speed, env location)
Stefan Roese [Thu, 3 Mar 2016 15:57:39 +0000 (16:57 +0100)]
arm: socfpga: sr1500: Misc updates (SPI speed, env location)

This patch makes the following changes to the SR1500 board port:

- Update defconfig to support SPI NOR (use make savedefconfig).
- Increase SPI speed to a maximum of 100MHz for faster system
  bootup.
- Change environment location, so that its not between SPL and
  main U-Boot. This way the combined SPL / U-Boot image can
  be used for updates.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
8 years agoarm: socfpga: Allow boards to define a custom environment size
Stefan Roese [Thu, 3 Mar 2016 15:57:38 +0000 (16:57 +0100)]
arm: socfpga: Allow boards to define a custom environment size

This patch makes it possible that boards can define a board-specific env
size. This is used by the SR1500 SoCFPGA board port.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Marek Vasut <marex@denx.de>
8 years agoarm: socfpga: Fix SR1500 env position
Marek Vasut [Fri, 26 Feb 2016 18:11:30 +0000 (19:11 +0100)]
arm: socfpga: Fix SR1500 env position

Move the inclusion of the common socfpga configuration file further
down in the sr1500 configuration, so that the socfpga_common.h can
check if environment is in SPI NOR and it's location is defined and
if it is not, define default location.

This fixes "arm: socfpga: Enabling U-Boot environment support in QSPI"
which introduced a minor warning.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
8 years agoarm: socfpga: Enabling U-Boot environment support in QSPI
Chin Liang See [Wed, 24 Feb 2016 08:50:22 +0000 (16:50 +0800)]
arm: socfpga: Enabling U-Boot environment support in QSPI

Enabling the support of storing U-Boot environment
within serial NOR flash. By default, its still
store into SDMMC

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
8 years agousb: xhci: Fix vendor command error if the request type is USB_REQ_SET_ADDRESS or...
Ted Chen [Fri, 18 Mar 2016 07:26:52 +0000 (17:56 +1030)]
usb: xhci: Fix vendor command error if the request type is USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION.

Add test into xhci_submit_control_message for usb requesttype in USB
vendor request being of standardized type. This fixes detection of
certain USB fixes, for example Ethernet, USB 3.0 port. Non standardized
requesttype in USB vendor request will be ignored.

Signed-off-by: Ted Chen <tedchen@realtek.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
8 years agousb: Change power-on / scanning timeout handling
Stefan Roese [Tue, 15 Mar 2016 12:59:15 +0000 (13:59 +0100)]
usb: Change power-on / scanning timeout handling

This patch changes the USB port scanning procedure and timeout
handling in the following ways:

a)
The power-on delay in usb_hub_power_on() is now reduced to a value of
max(100ms, "hub->desc.bPwrOn2PwrGood * 2"). The code does not wait
using mdelay, instead usb_hub_power_on() will wait before querying
the device in the scanning loop later. The total timeout for this
hub, which is 1 second + "hub->desc.bPwrOn2PwrGood * 2" is calculated
and will be used in the following per-port scanning loop as the timeout
to detect active USB devices on this hub.

b)
Don't delay the minimum delay (for power to stabilize) in
usb_hub_power_on(). Instead skip querying these devices in the scannig
loop until the delay time is reached.

c)
The ports are now scanned in a quasi parallel way. The current code did
wait for each (unconnected) port to reach its timeout and only then
continue with the next port. This patch now changes this to scan all
ports of all USB hubs quasi simultaneously. For this, all ports are added
to a scanning list. This list is scanned until all ports are ready
by either a) reaching the connection timeout (calculated earlier), or
by b) detecting a USB device. This results in a faster USB scan time as
the recursive scanning of USB hubs connected to the hub that's currently
being scanned will start earlier.

One small functional change to the original code is, that ports with
overcurrent detection will now get rescanned multiple times
(PORT_OVERCURRENT_MAX_SCAN_COUNT).

Without this patch:
starting USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 9 USB Device(s) found

time: 20.163 seconds

With this patch:
starting USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 9 USB Device(s) found

time: 1.822 seconds

So ~18.3 seconds of USB scanning time reduction.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agousb: Don't reset the USB hub a 2nd time
Stefan Roese [Tue, 15 Mar 2016 12:59:14 +0000 (13:59 +0100)]
usb: Don't reset the USB hub a 2nd time

Debugging has shown, that all USB hubs are being reset twice while
USB scanning. This introduces additional delays and makes USB scanning
even more slow. Testing has shown that this 2nd USB hub reset doesn't
seem to be necessary.

This patch now removes this 2nd USB hub reset. Resulting in faster USB
scan time. Here the current numbers:

Without this patch:
=> time usb start
starting USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 9 USB Device(s) found

time: 24.003 seconds

With this patch:
=> time usb start
starting USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 9 USB Device(s) found

time: 20.392 seconds

So ~3.6 seconds of USB scanning time reduction.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Cc: Marek Vasut <marex@denx.de>
8 years agousb: Remove 200 ms delay in usb_hub_port_connect_change()
Stefan Roese [Tue, 15 Mar 2016 12:59:13 +0000 (13:59 +0100)]
usb: Remove 200 ms delay in usb_hub_port_connect_change()

This patch removes 2 mdelay(200) calls from usb_hub_port_connect_change().
These delays don't seem to be necessary. At least not in my tests. Here
the number for a custom x86 Bay Trail board (not in mainline yet) with
a quite large and complex USB hub infrastructure.

Without this patch:
starting USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 9 USB Device(s) found

time: 28.415 seconds

With this patch:
starting USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 9 USB Device(s) found

time: 24.003 seconds

So ~4.5 seconds of USB scanning time reduction.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Cc: Marek Vasut <marex@denx.de>
8 years agousb: legacy_hub_port_reset(): Speedup hub reset handling
Stefan Roese [Tue, 15 Mar 2016 12:59:12 +0000 (13:59 +0100)]
usb: legacy_hub_port_reset(): Speedup hub reset handling

Start with a short USB hub reset delay of 20ms. This can be enough for
some configurations.

The 2nd delay at the end of the loop is completely removed. Since the
delay hasn't been long enough, a longer delay time of 200ms is assigned
and will be used in the next loop round.

This hub reset handling is also used in the v4.4 Linux USB driver,
hub_port_reset().

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Cc: Marek Vasut <marex@denx.de>
8 years agodm: blk: Add tests for block devices
Simon Glass [Sun, 13 Mar 2016 14:22:36 +0000 (08:22 -0600)]
dm: blk: Add tests for block devices

Add some tests to check that block devices work as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: sandbox: Drop the pre-DM host implementation
Simon Glass [Sun, 13 Mar 2016 14:22:35 +0000 (08:22 -0600)]
dm: sandbox: Drop the pre-DM host implementation

Driver model is used for host device block devices now, so we don't need the
old code. Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: sandbox: Switch over to use DM for block devices
Simon Glass [Sun, 13 Mar 2016 14:22:34 +0000 (08:22 -0600)]
dm: sandbox: Switch over to use DM for block devices

Now that the drivers used by sandbox support CONFIG_BLK, we can switch
sandbox over to use driver model for block devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agodm: usb: Unbind old block devices when shutting down USB
Simon Glass [Sun, 13 Mar 2016 14:22:33 +0000 (08:22 -0600)]
dm: usb: Unbind old block devices when shutting down USB

When 'usb start' is used, block devices are created for any USB flash sticks
and disks, etc. When 'usb stop' is used, these block devices are currently
not removed.

We don't want old block devices hanging around since they can still be
visible to U-Boot. Therefore, when USB is shut down, remove and unbind all
the block devices created by the USB subsystem.

Possibly we should unbind all devices which don't cause problems by being
unbound. Most likely we can remove everything except USB controllers, hubs
and emulators. We can consider that later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agobuildman: Clarify the use of -V
Simon Glass [Sun, 13 Mar 2016 01:50:33 +0000 (18:50 -0700)]
buildman: Clarify the use of -V

This option outputs to the log file, not to the terminal. Clarify that in
the help, and add a mention of it in the README.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agobuildman: Add a way to specific a full toolchain prefix
Simon Glass [Sun, 13 Mar 2016 01:50:32 +0000 (18:50 -0700)]
buildman: Add a way to specific a full toolchain prefix

At present buildman allows you to specify the directory containing the
toolchain, but not the actual toolchain prefix. If there are multiple
toolchains in a single directory, this can be inconvenient.

Add a new 'toolchain-prefix' setting to the settings file, which allows
the full prefix (or path to the C compiler) to be specified.

Update the documentation to match.

Suggested-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
8 years agobuildman: Allow branch names which conflict with directories
Simon Glass [Sun, 13 Mar 2016 01:50:31 +0000 (18:50 -0700)]
buildman: Allow branch names which conflict with directories

At present if you try to use buildman with the branch 'test' it will
complain that it is unsure whether you mean the branch or the directory.
This is a feature of the 'git log' command that buildman uses. Fix it
by resolving the ambiguity.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
8 years agodm: ns16550: Add support for reg-offset property
Michal Simek [Tue, 16 Feb 2016 15:17:49 +0000 (16:17 +0100)]
dm: ns16550: Add support for reg-offset property

reg-offset is the part of standard 8250 binding in the kernel.
It is shifting start of address space by reg-offset.
On Xilinx platform this offset is typically 0x1000.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Moved the new field to the end of the struct to avoid problems:
Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agoRevert "fdt: fix address cell count checking in fdt_translate_address()"
Przemyslaw Marczak [Tue, 12 Jan 2016 14:40:44 +0000 (15:40 +0100)]
Revert "fdt: fix address cell count checking in fdt_translate_address()"

This reverts commit 71105f50fedddfa5b0535d102c3d5078671721ad.

The reverted commit was applied for a temporary to unbreak
few Exynos boards on the release.

After the discussion about the change, this commit should be avoided.
Fixed device-tree for Exynos, allows reverting it without any issues.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
8 years agodts:exynos:update pinctrl size-cells and fix child regs
Przemyslaw Marczak [Tue, 12 Jan 2016 14:40:43 +0000 (15:40 +0100)]
dts:exynos:update pinctrl size-cells and fix child regs

This change is required to avoid warnings about invalid
size-cells defined in device-tree pinctrl nodes for Exynos.

Tested on:
- Odroid U3
- Odroid XU3

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
8 years agogpio: Report errors when GPIOs cannot be read
Simon Glass [Tue, 1 Sep 2015 00:55:36 +0000 (18:55 -0600)]
gpio: Report errors when GPIOs cannot be read

Some controllers do not allow the output value to be read. Detect this and
report the error in that case.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agocmd_dhry.c: Use lldiv for vax_mips calculation as well
Tom Rini [Thu, 17 Mar 2016 14:14:25 +0000 (10:14 -0400)]
cmd_dhry.c: Use lldiv for vax_mips calculation as well

Since dhry_per_sec is a u64 we must also use lldiv here when working
with it.  Otherwise:
../lib/dhry/cmd_dhry.c:(.text.do_dhry+0xd8): undefined reference to `__udivdi3'

On some platforms.

Signed-off-by: Tom Rini <trini@konsulko.com>
8 years agox86: Add congatec conga-QA3/E3845-4G (Bay Trail) support
Stefan Roese [Wed, 16 Mar 2016 07:48:21 +0000 (08:48 +0100)]
x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support

This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).

Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.

Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe

Not supported yet is:
- I2C
- USB 3.0

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add support for the samus chromebook
Simon Glass [Wed, 16 Mar 2016 13:44:43 +0000 (07:44 -0600)]
x86: Add support for the samus chromebook

This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Support a chained-boot development flow
Simon Glass [Wed, 16 Mar 2016 13:44:40 +0000 (07:44 -0600)]
x86: Support a chained-boot development flow

Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.

U-Boot expects its GDT to be set up correctly by its 16-bit code. If
coreboot doesn't do this (because it hasn't run the payload setup code yet)
then this won't happen.

In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong. Provide a development-only option to set up the GDT
correctly. This is just a hack so you can jump to U-Boot from any stage of
coreboot, not just at the end.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: dts: Drop memory SPD compatible string
Simon Glass [Wed, 16 Mar 2016 13:44:39 +0000 (07:44 -0600)]
x86: dts: Drop memory SPD compatible string

This is not needed now that the memory controller driver has the SPD data
in its own node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: ivybridge: Convert to use the common SDRAM code
Simon Glass [Wed, 16 Mar 2016 13:44:38 +0000 (07:44 -0600)]
x86: ivybridge: Convert to use the common SDRAM code

Adjust the existing implementation to use the new common SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add common SDRAM-init code
Simon Glass [Wed, 16 Mar 2016 13:44:37 +0000 (07:44 -0600)]
x86: Add common SDRAM-init code

The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Move common PCH code into a common place
Simon Glass [Wed, 16 Mar 2016 13:44:36 +0000 (07:44 -0600)]
x86: Move common PCH code into a common place

The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agodhry: Correct dhrystone calculation for fast machines
Simon Glass [Wed, 16 Mar 2016 13:44:35 +0000 (07:44 -0600)]
dhry: Correct dhrystone calculation for fast machines

At present samus reports about 5600 DMIPS. With the default iteration count
this is OK, but if 10 million runs are performed it overflows. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agoarm: Add a 64-bit division routine to the private library
Simon Glass [Wed, 16 Mar 2016 13:44:34 +0000 (07:44 -0600)]
arm: Add a 64-bit division routine to the private library

This is missing, with causes lldiv() to fail on boards with use the private
libgcc. Add the missing routine.

Code is available for using the CLZ instruction but it is not enabled at
present.

This comes from coreboot version 4.0.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agox86: Fix a header nit in x86-chromebook.h
Simon Glass [Sat, 12 Mar 2016 05:07:35 +0000 (22:07 -0700)]
x86: Fix a header nit in x86-chromebook.h

There is an extra line in the comment in the header. Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add a function to set the IOAPIC ID
Simon Glass [Sat, 12 Mar 2016 05:07:34 +0000 (22:07 -0700)]
x86: Add a function to set the IOAPIC ID

Add a function to set the ID in the IOAPIC.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Update README for new developments
Simon Glass [Sat, 12 Mar 2016 05:07:33 +0000 (22:07 -0700)]
x86: Update README for new developments

Update a few points which have become out-of-date.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Use white on black for the console on chromebooks
Simon Glass [Sat, 12 Mar 2016 05:07:32 +0000 (22:07 -0700)]
x86: Use white on black for the console on chromebooks

This is a little easier on the eyes, particularly when the backlight is set
to maximum.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add a default address for reference code
Simon Glass [Sat, 12 Mar 2016 05:07:31 +0000 (22:07 -0700)]
x86: Add a default address for reference code

Add an address which can be used for loading and running the reference code
when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add video support
Simon Glass [Sat, 12 Mar 2016 05:07:30 +0000 (22:07 -0700)]
x86: broadwell: Add video support

Add a video driver for Intel's broadwell integrated graphics controller.
This uses a binary blob for most init, with the driver just performing a few
basic tasks.

This driver supports VESA as the mode-setting mechanism. Since most boards
don't support driver model yet with VESA, a special case is added to the
Kconfig for broadwell. Eventually all boards will use driver model and this
can be removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add support for high-speed I/O lane with ME
Simon Glass [Sat, 12 Mar 2016 05:07:28 +0000 (22:07 -0700)]
x86: broadwell: Add support for high-speed I/O lane with ME

Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add a GPIO driver
Simon Glass [Sat, 12 Mar 2016 05:07:27 +0000 (22:07 -0700)]
x86: broadwell: Add a GPIO driver

Add a GPIO driver for the GPIO peripheral found on broadwell devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add support for SDRAM setup
Simon Glass [Sat, 12 Mar 2016 05:07:26 +0000 (22:07 -0700)]
x86: broadwell: Add support for SDRAM setup

Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add power-control support
Simon Glass [Sat, 12 Mar 2016 05:07:25 +0000 (22:07 -0700)]
x86: broadwell: Add power-control support

Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598373/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add reference code support
Simon Glass [Sat, 12 Mar 2016 05:07:24 +0000 (22:07 -0700)]
x86: broadwell: Add reference code support

Broadwell needs a special binary blob to set up the PCH. Add code to run
this on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add an LPC driver
Simon Glass [Sat, 12 Mar 2016 05:07:23 +0000 (22:07 -0700)]
x86: broadwell: Add an LPC driver

Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add a northbridge driver
Simon Glass [Sat, 12 Mar 2016 05:07:22 +0000 (22:07 -0700)]
x86: broadwell: Add a northbridge driver

Add a driver for the broadwell northbridge. This sets up the location of
several blocks of registers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add a SATA driver
Simon Glass [Sat, 12 Mar 2016 05:07:21 +0000 (22:07 -0700)]
x86: broadwell: Add a SATA driver

Add a SATA driver for broadwell. This supports connecting an SSD and the
usual U-Boot commands to read and write data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add a pinctrl driver
Simon Glass [Sat, 12 Mar 2016 05:07:20 +0000 (22:07 -0700)]
x86: broadwell: Add a pinctrl driver

GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: broadwell: Add a PCH driver
Simon Glass [Sat, 12 Mar 2016 05:07:19 +0000 (22:07 -0700)]
x86: broadwell: Add a PCH driver

Add a driver for the broadwell low-power platform controller hub.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add basic support for broadwell
Simon Glass [Sat, 12 Mar 2016 05:07:18 +0000 (22:07 -0700)]
x86: Add basic support for broadwell

This adds the broadwell architecture, with the CPU driver and some useful
header files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: dts: Update the pinctrl binding a little
Simon Glass [Sat, 12 Mar 2016 05:07:17 +0000 (22:07 -0700)]
x86: dts: Update the pinctrl binding a little

Make a few minor updates to make the meaning clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add support for running Intel reference code
Simon Glass [Sat, 12 Mar 2016 05:07:16 +0000 (22:07 -0700)]
x86: Add support for running Intel reference code

Intel has invented yet another binary blob which firmware is required to
run. This is run after SDRAM is ready. It is linked to load at a particular
address, typically 0, but is a relocatable ELF so can be moved if required.

Add support for this in the build system. The file should be placed in the
board directory, and called refcode.elf.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Drop all the old pin configuration code
Simon Glass [Sat, 12 Mar 2016 05:07:15 +0000 (22:07 -0700)]
x86: Drop all the old pin configuration code

We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: gpio: Allow the pinctrl driver to set up the pin config
Simon Glass [Sat, 12 Mar 2016 05:07:14 +0000 (22:07 -0700)]
x86: gpio: Allow the pinctrl driver to set up the pin config

Rather than setting up the pin configuration in the GPIO driver, use the
new pinctrl driver to do it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Add an ICH6 pin configuration driver
Simon Glass [Sat, 12 Mar 2016 05:07:13 +0000 (22:07 -0700)]
x86: Add an ICH6 pin configuration driver

Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.

The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:

- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed

It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH

However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.

Also add an 'invert' property to support inverting the input.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: link: Add pin configuration to the device tree
Simon Glass [Sat, 12 Mar 2016 05:07:12 +0000 (22:07 -0700)]
x86: link: Add pin configuration to the device tree

At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.

Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Update microcode for secondary CPUs
Simon Glass [Sat, 12 Mar 2016 05:07:11 +0000 (22:07 -0700)]
x86: Update microcode for secondary CPUs

Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: ivybridge: Show microcode version for each core
Simon Glass [Sat, 12 Mar 2016 05:07:10 +0000 (22:07 -0700)]
x86: ivybridge: Show microcode version for each core

Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agox86: Record the CPU details when starting each core
Simon Glass [Sat, 12 Mar 2016 05:07:09 +0000 (22:07 -0700)]
x86: Record the CPU details when starting each core

As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>