Emil Velikov [Wed, 29 Nov 2017 15:15:19 +0000 (15:15 +0000)]
xlib: remove dummy GLX_MESA_set_3dfx_mode implementation
The implementation is a simple 'return EGL_FALSE'. Stop pretending and
simply remove it.
Note: the removal of XMesa API is fine, since there hasn't been any
users for it in years.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Emil Velikov [Wed, 29 Nov 2017 15:09:01 +0000 (15:09 +0000)]
docs/specs: annotate MESA_agp_offset as obsolete
No Mesa driver has implemented the extension in ages. Seemingly non Mesa
drivers don't implement it either.
As mentioned by Ian, the extension is effectively superseded by
ARB_vertex_buffer_object.
v2: Move the extension to OLD/
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v1)
Reviewed-by: Adam Jackson <ajax@redhat.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Emil Velikov [Wed, 29 Nov 2017 14:46:26 +0000 (14:46 +0000)]
xlib: remove empty GLX_MESA_agp_offset stubs
The extension was never implemented and seemingly never will.
The DRI based libGL dropped support for it over 10 years ago.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Emil Velikov [Wed, 29 Nov 2017 14:32:36 +0000 (14:32 +0000)]
xlib: remove empty GLX_NV_vertex_array_range stubs
The extension was never implemented and seemingly never will.
The DRI based libGL dropped support for it over 10 years ago.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Rafael Antognolli [Wed, 8 Nov 2017 19:39:52 +0000 (11:39 -0800)]
i965/gen10: Change the order of PIPE_CONTROL and load register.
I believe the workaround describes that the MI_LOAD_REGISTER_IMM should
come right after the 3DSTATE_SAMPLE_PATTERN.
This fixes GPU hangs in the i965 initial state batchbuffer when running
some Piglit tests with always_flush_batch=true.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Fri, 6 Oct 2017 18:41:54 +0000 (11:41 -0700)]
intel/compiler: Implement WaClearTDRRegBeforeEOTForNonPS.
The bspec describes:
"WA: Clear tdr register before send EOT in all non-PS shader kernels
mov(8) tdr0:ud 0x0:ud {NoMask}"
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Mon, 2 Oct 2017 18:06:05 +0000 (11:06 -0700)]
i965/gen10: emit 3DSTATE_MULTISAMPLE more often.
On CNL, we see multiple multisample failures on piglit tests. By
emitting this extra state, though not documented in the bspec, those
failures seem to go away.
This workaround could be removed if we ever find out a better solution,
but it should be good enough for now.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Dylan Baker [Thu, 30 Nov 2017 18:39:29 +0000 (10:39 -0800)]
meson: install khrplatform header for EGL as well as GLES
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Thu, 30 Nov 2017 18:37:11 +0000 (10:37 -0800)]
meson: install dri internal header
Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Jason Ekstrand [Thu, 30 Nov 2017 00:22:42 +0000 (16:22 -0800)]
i965: Disable regular fast-clears (CCS_D) on gen9+
This partially reverts commit
3e57e9494c2279580ad6a83ab8c065d01e7e634e
which caused a bunch of GPU hangs on several Source titles. To date, we
have no clue why these hangs are actually happening. This undoes the
final effect of
3e57e9494c227 and gets us back to not hanging. Tested
with Team Fortress 2.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435
Fixes:
3e57e9494c2279580ad6a83ab8c065d01e7e634e
Cc: mesa-stable@lists.freedesktop.org
Vadym Shovkoplias [Fri, 1 Dec 2017 15:08:53 +0000 (17:08 +0200)]
egl/x11: Remove unneeded free() on always null string
In this condition dri2_dpy->driver_name string always equals
NULL, so call to free() is useless
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Eric Engestrom [Wed, 29 Nov 2017 14:19:26 +0000 (14:19 +0000)]
gallium/hud: use #ifdef to test for macro existence
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Engestrom [Fri, 24 Nov 2017 16:23:03 +0000 (16:23 +0000)]
amd: remove always-true BRAHMA_BUILD define
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Vadym Shovkoplias [Fri, 1 Dec 2017 11:23:02 +0000 (13:23 +0200)]
glx/dri3: Remove unused deviceName variable
deviceName string is declared, assigned and freed but actually
never used in dri3_create_screen() function.
Fixes:
2d94601582e ("Add DRI3+Present loader")
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
George Kyriazis [Thu, 30 Nov 2017 20:24:39 +0000 (14:24 -0600)]
swr/scons: Fix intermittent build failure
gen_rasterizer*.cpp depends on gen_ar_eventhandler.hpp.
Account for new dependency.
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Samuel Pitoiset [Thu, 30 Nov 2017 21:23:37 +0000 (22:23 +0100)]
radv: only reset command buffers when the allocation fails
"vkAllocateCommandBuffers can be used to create multiple command
buffers. If the creation of any of those command buffers fails, the
implementation must destroy all successfully created command buffer
objects from this command, set all entries of the pCommandBuffers
array to NULL and return the error."
This has been suggested by gabriel@system.is.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 30 Nov 2017 21:16:09 +0000 (22:16 +0100)]
radv: do not dump meta shaders with RADV_DEBUG=shaders
It's really annoying and this pollutes the output especially
when a bunch of non-meta shaders are compiled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Fri, 3 Nov 2017 00:15:38 +0000 (10:15 +1000)]
r600: add ARB_shader_storage_buffer_object support (v3)
This just builds on the image support. Evergreen only has ssbo
for fragment and compute no other stages.
v2: handle images and ssbo in the same shader properly (Ilia)
v3: fix RESQ on buffers,
fix missing atom emit
fix first element offset
use R32 format
write separate buffer rat store path.
(from running deqp gles3.1 tests)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 27 Nov 2017 06:39:49 +0000 (06:39 +0000)]
r600/cayman: looks like cmpxchg moved to Z
On cayman it appears the cmp component is now in Z.
Fixes:
arb_shader_image_load_store-dead-fragments on cayman.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 27 Nov 2017 02:07:45 +0000 (02:07 +0000)]
r600/shader: fix 64->32 conversions
These didn't handle the TGSI at all properly, this fixes
them to use the common path for 64->32 then adds the 32->int
on at the end.
Fixes:
generated_tests/spec/arb_gpu_shader_fp64/execution/conversion/*
Signed-off-by: Dave Airlie <airlied@redhat.com>
Samuel Pitoiset [Wed, 29 Nov 2017 13:48:32 +0000 (14:48 +0100)]
radv: do not allocate CMASK or DCC for small surfaces
The idea is ported from RadeonSI, but using 512x512 instead of
256x256 seems slightly better. This improves dota2 performance
by +2%.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Samuel Pitoiset [Thu, 30 Nov 2017 19:58:29 +0000 (20:58 +0100)]
radv: do not set DISABLE_LSB_CEIL on GFX9
The state no longer exists on GFX9.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 30 Nov 2017 13:32:58 +0000 (14:32 +0100)]
radv: remove set but unnecessary radv_color_buffer_info::micro_tile_mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 30 Nov 2017 13:32:57 +0000 (14:32 +0100)]
radv: do not store gfx9_epitch in radv_color_buffer_info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dylan Baker [Wed, 29 Nov 2017 19:18:52 +0000 (11:18 -0800)]
meson: fix glxext.h install
Another typo, the glext.h header was being install instead.
Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Wed, 29 Nov 2017 19:16:59 +0000 (11:16 -0800)]
meson: fix GLES3/gl31.h install
This is a typo, gl32.h is installed twice.
Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Marek Olšák [Thu, 30 Nov 2017 01:14:18 +0000 (02:14 +0100)]
ac/surface: always compute DCC info when DCC is possible on GFX9
The same code for VI doesn't check for scanout either.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 30 Nov 2017 01:16:29 +0000 (02:16 +0100)]
radeonsi/gfx9: fix importing shared textures with DCC
VI has 11 dwords at least. GFX9 has 10 dwords.
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jon Turney [Thu, 23 Nov 2017 13:51:43 +0000 (13:51 +0000)]
meson: fix deps and underlinkage of libGL
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Jon Turney [Mon, 20 Nov 2017 22:05:47 +0000 (22:05 +0000)]
meson: build src/glx/windows
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Jon Turney [Thu, 23 Nov 2017 14:01:57 +0000 (14:01 +0000)]
meson: don't require dri2proto for darwin or windows
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Jon Turney [Thu, 23 Nov 2017 13:42:00 +0000 (13:42 +0000)]
meson: set _GNU_SOURCE on cygwin
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Jon Turney [Thu, 23 Nov 2017 13:40:06 +0000 (13:40 +0000)]
meson: set windows glx defines
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Fri, 3 Nov 2017 21:54:03 +0000 (14:54 -0700)]
meson: fix generated source inclusion on macOS and Windows
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Vadym Shovkoplias [Mon, 27 Nov 2017 10:15:13 +0000 (12:15 +0200)]
intel/blorp: Fix possible NULL pointer dereferencing
Fix incomplete check of input params in blorp_surf_convert_to_uncompressed()
which can lead to NULL pointer dereferencing.
Fixes:
5ae8043fed2 ("intel/blorp: Add an entrypoint for doing
bit-for-bit copies")
Fixes:
f395d0abc83 ("intel/blorp: Internally expose
surf_convert_to_uncompressed")
Reviewed-by: Emil Velikov <emli.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Tapani Pälli [Fri, 24 Nov 2017 05:46:07 +0000 (07:46 +0200)]
mesa: add AllowGLSLCrossStageInterpolationMismatch workaround
This fixes issues seen with certain versions of Unreal Engine 4 editor
and games built with that using GLSL 4.30.
v2: add driinfo_gallium change (Emil Velikov)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97852
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103801
Acked-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Vinson Lee [Wed, 29 Nov 2017 07:16:58 +0000 (23:16 -0800)]
anv: Check if memfd_create is already defined.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103909
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Iago Toral Quiroga [Wed, 29 Nov 2017 09:50:42 +0000 (10:50 +0100)]
i965/vec4: use a temp register to compute offsets for pull loads
64-bit pull loads are implemented by emitting 2 separate
32-bit pull load messages, where the second message loads from
an offset at +16B.
That addition of 16B to the original offset should not alter the
original offset register used as source for the pull load instruction
though, since the compiler might use that same offset register in other
instructions (for example, for other pull loads in the shader code
that take that same offset as reference).
If the pull load is 32-bit then we only need to emit one message and
we don't need to do offset calculations, but in that case the optimizer
should be able to drop the redundant MOV.
Fixes the following test on Haswell:
KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components
Reviewed-by: Matt Turner <mattst88@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103007
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:40 +0000 (10:44 +0100)]
etnaviv: GC7000: Factor out state based texture functionality
Prepare for two texture handling paths, the descriptor-based
path will be added in a future commit. These are structured
so that the texture implementation handles its own state
emission.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:39 +0000 (10:44 +0100)]
etnaviv: GC7000: Move active_samplers_bits to texture
This needs to be shared between texture_plain and texture_desc.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:38 +0000 (10:44 +0100)]
etnaviv: GC7000: Factor out incompatible texture handling logic
This will be shared with the texture descriptor path.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:37 +0000 (10:44 +0100)]
etnaviv: GC7000: Track dirty sampler views
Need this to efficiently emit texture descriptor invalidations.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:36 +0000 (10:44 +0100)]
etnaviv: GC7000: Make point sprites work on HALTI5
Track varying component offset of the point size output, as well as
provide the offset of the point coord input.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Wed, 29 Nov 2017 12:19:45 +0000 (13:19 +0100)]
etnaviv: GC7000: State changes for HALTI3..5
Update state objects to add new state, and emit function to emit new
state.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:34 +0000 (10:44 +0100)]
etnaviv: GC7000: Update screen specs for HALTI5
- This core must load shaders from memory (AFAIK)
- Yet another new location for UNIFORMS
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:33 +0000 (10:44 +0100)]
etnaviv: GC7000: Update context reset for ..HALTI5
Update context reset for HALTI3..HALTI5, sorting states for the HALTI
version that has them.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:32 +0000 (10:44 +0100)]
etnaviv: GC7000: No RS align when using BLT
RS align is not necessary and might even be harmful when using the BLT
engine for blitting.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:31 +0000 (10:44 +0100)]
etnaviv: GC7000: BLT engine blitting support
Add an implemenation of key clear_blit functions using the BLT engine
that replaced the RS on GC7000.
Also set level->size correctly for imported resources. This is important
for the BLT resolve-in-place path to work for them.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:30 +0000 (10:44 +0100)]
etnaviv: GC7000: Factor out RS blit functionality
Prepare for BLT-based blitting path by moving RS-based
blitting to the RS implementation file, making this
self-contained.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:29 +0000 (10:44 +0100)]
etnaviv: GC7000: Move etna_coalesce to emit header file
Want to be able to emit state from the texture implementation,
and the blitter implementation.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:28 +0000 (10:44 +0100)]
etnaviv: GC7000: Support BLT as recipient for etna_stall
When the BLT is involved as source or target, add an extra BLT
enable/disable sequence around the sync sequence.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:27 +0000 (10:44 +0100)]
etnaviv: Use only DRAW_INSTANCED on GC3000+
The blob does this, as DRAW_INSTANCED can replace fully all the other
draw commands. It is also required to handle integer vertex formats.
The other path is only there for compatibility and might go away (or at
least rot to become buggy due to dis-use) in newer hardware.
As a by-effect this changes the behavior for GC3000-, by no longer using
the index offset for DRAW_INDEXED but instead adding it to INDEX_ADDR.
This should make no difference.
Preparation for GC7000 support.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Wladimir J. van der Laan [Sat, 18 Nov 2017 09:44:26 +0000 (10:44 +0100)]
etnaviv: Emit SCALE for vertex attributes
This is used by HALTI2+ (GC3000+) when drawing with DRAW_INSTANCED.
It is also necessary when switching between integer and floating point
vertex element formats.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Kenneth Graunke [Tue, 28 Nov 2017 16:58:21 +0000 (08:58 -0800)]
i965: Reorganize batch/state BO fields into a 'brw_growing_bo' struct.
We're about to add more of them, and need to pass the whole lot of them
around together when growing them. Putting them in a struct makes this
much easier.
brw->batch.batch.bo is a bit of a mouthful, but it's nice to have things
labeled 'batch' and 'state' now that we have multiple buffers.
Fixes:
2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 28 Nov 2017 16:20:39 +0000 (08:20 -0800)]
i965: Don't grow batch/state buffer on every emit after an overflow.
Once we reach the intended size of the buffer (BATCH_SZ or STATE_SZ), we
try and flush. If we're not allowed to flush, we resort to growing the
buffer so that there's space for the data we need to emit.
We accidentally got the threshold wrong. The first non-wrappable call
beyond (e.g.) STATE_SZ would grow the buffer to floor(1.5 * STATE_SZ),
The next call would see we were beyond STATE_SZ and think we needed to
grow a second time - when the buffer was already large enough.
We still want to flush when we hit STATE_SZ, but for growing, we should
use the actual size of the buffer as the threshold. This way, we only
grow when actually necessary.
v2: Simplify the control flow (suggested by Jordan)
Fixes:
2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 28 Nov 2017 16:59:07 +0000 (08:59 -0800)]
i965: Preserve EXEC_OBJECT_CAPTURE when growing the BO.
The original state buffer was marked with EXEC_OBJECT_CAPTURE. When
growing it, we want to preserve that flag so we continue to capture it
in GPU hang reports.
Fixes:
2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 28 Nov 2017 16:30:50 +0000 (08:30 -0800)]
i965: Use old_bo->align when growing batch/state buffer instead of 4096.
The intention here is make the new BO use the same alignment as the old
BO. This isn't strictly necessary, but we would have to update the
'alignment' field in the validation list when swapping it out, and we
don't bother today.
The batch and state buffers use an alignment of 4096, so this should be
equivalent - it's just clearer than cut and pasting a magic constant.
Fixes:
2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Dave Airlie [Thu, 23 Nov 2017 00:19:14 +0000 (10:19 +1000)]
r600: no need to reinit compute regs
Compute setup gets emitted into the normal gfx state buffer,
so no need to reinit the basics.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 29 Nov 2017 03:55:52 +0000 (13:55 +1000)]
r600: split cb setup code out from evergreen compute path.
This just makes it easier to bypass for TGSI later.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 20 Nov 2017 21:28:56 +0000 (07:28 +1000)]
r600: add support for compute pkt flags to debug dumping.
This just lets us see packets marked for compute.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 28 Nov 2017 03:30:41 +0000 (13:30 +1000)]
r600: fix bfe where src/dst are same.
This fixes overlaps where src/dst are the same.
Fixes a bunch of the deqp bitfield tests.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Adam Jackson [Mon, 6 Nov 2017 21:28:36 +0000 (16:28 -0500)]
gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control
Reviewed-and-tested-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Kenneth Graunke [Wed, 29 Nov 2017 08:27:18 +0000 (00:27 -0800)]
i965: Program the dynamic state heap size to MAX_STATE_SIZE.
STATE_BASE_ADDRESS specifies a maximum size of the dynamic state
section, beyond which data supposedly reads back as 0. On Gen8+,
we were programming it to the size of the buffer. This worked fine
until we started growing the state buffer in commit
2dfc119f22f25708.
When the state buffer grows, the value in STATE_BASE_ADDRESS becomes
too small, and our state beyond STATE_SZ bytes would read back as 0.
To avoid having to update the value, we program it to MAX_STATE_SIZE.
We used to program the upper bound to the maximum on older hardware
anyway, so programming it too large isn't a big deal.
Bogus SURFACE_STATE can easily lead to GPU hangs and misrendering.
DiRT Rally was hitting the statebuffer growth path, and suffered from
bad texture corruption and GPU hangs (usually around the same time).
This patch fixes both issues.
Fixes:
2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Tue, 28 Nov 2017 16:54:55 +0000 (17:54 +0100)]
r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*
and handle PIPE_FLUSH_HINT_FINISH in r300.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:38:44 +0000 (03:38 +0100)]
radeonsi: remove r600_common_screen
Most files in gallium/radeon now include si_pipe.h.
chip_class and family are now here:
sscreen->info.family
sscreen->info.chip_class
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:19:20 +0000 (03:19 +0100)]
radeonsi: remove r600_pipe_common::barrier_flags::compute_to_L2
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:15:09 +0000 (03:15 +0100)]
radeonsi: remove query/apply_opaque_metadata callbacks
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:08:59 +0000 (03:08 +0100)]
radeonsi: move shader debug helpers out of r600_pipe_common.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:04:55 +0000 (03:04 +0100)]
radeonsi: dismantle si_common_screen_init/destroy
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 22:04:31 +0000 (23:04 +0100)]
radeonsi: document our vendor string situation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 22:02:00 +0000 (23:02 +0100)]
radeonsi: set all pipe buffer functions in r600_buffer_common.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:51:43 +0000 (22:51 +0100)]
radeonsi/uvd: don't call ws->query_info
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:48:36 +0000 (22:48 +0100)]
radeonsi: move video queries into si_get.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:39:28 +0000 (22:39 +0100)]
radeonsi: remove more functions from r600_pipe_common.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:35:27 +0000 (22:35 +0100)]
radeonsi: move/remove ac_shader_binary helpers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:33:10 +0000 (22:33 +0100)]
radeonsi: move all get functions to si_get.c; disk_cache_create to si_pipe.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 20:37:30 +0000 (21:37 +0100)]
radeonsi: remove R600_CONTEXT_* flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 20:36:36 +0000 (21:36 +0100)]
radeonsi: just include si_pipe.h in r600_query.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 20:21:57 +0000 (21:21 +0100)]
radeonsi: remove some definitions and helpers from r600_pipe_common.h
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:16:02 +0000 (20:16 +0100)]
radeonsi: don't use fast color clear for small surfaces
This removes 35+ clear eliminate passes from DOTA 2.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 28 Nov 2017 20:37:26 +0000 (21:37 +0100)]
radeonsi: unify code setting dirty_level_mask for fast clear
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 20:08:20 +0000 (21:08 +0100)]
radeonsi: clean up si_do_fast_color_clear parameters
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:50:31 +0000 (20:50 +0100)]
radeonsi: remove r600_common_context::clear_buffer
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:45:21 +0000 (20:45 +0100)]
radeonsi: move r600_test_dma.c into si_test_dma.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:39:12 +0000 (20:39 +0100)]
radeonsi: move si_pipe_clear_buffer into si_cp_dma.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:36:35 +0000 (20:36 +0100)]
radeonsi: move all clear() code into si_clear.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 23:41:47 +0000 (00:41 +0100)]
radeonsi: enable DCC with MSAA for VI
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 23:36:56 +0000 (00:36 +0100)]
radeonsi: implement fast color clear for DCC with MSAA for VI
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 23:33:53 +0000 (00:33 +0100)]
radeonsi: add a workaround for blending with DCC and MSAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 23:19:56 +0000 (00:19 +0100)]
radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 21:29:26 +0000 (22:29 +0100)]
ac/surface: enable DCC computation for MSAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 28 Nov 2017 19:57:10 +0000 (20:57 +0100)]
radeonsi: fix layered DCC fast clear
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jon Turney [Mon, 27 Nov 2017 13:32:53 +0000 (13:32 +0000)]
util: Also include endian.h on cygwin
If u_endian.h can't determine the endianess, the default behaviour in sha1.c
is to build for big-endian
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Juan A. Suarez Romero [Wed, 29 Nov 2017 11:09:47 +0000 (12:09 +0100)]
mesa: deal with vs_inputs as 64-bit unsigned integer
Commit 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits") uses
vs_prog_data->vs_inputs as if it were a 32-bit unsigned integer.
But actually it is a 64-bit integer, and as such it is used in other
parts of Mesa code. It is worth to note that bits from the entire range
are used, and not only 32-bits. This is due our implementation for
handling 64-bit dual-slot input attributes, which requires to use a
larger bitfield to manage them.
This commit reverts the changes done in brw_draw_upload.c, keeping the
rest of the changes.
This fixes the following tests:
- KHR-GL45.enhanced_layouts.varying_array_locations
- KHR-GL45.enhanced_layouts.varying_locations
Fixes: 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103942
CC: Marek Olšák <marek.olsak@amd.com>
CC: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Timothy Arceri [Thu, 15 Jun 2017 23:56:56 +0000 (09:56 +1000)]
mesa: rework _mesa_add_parameter() to only add a single param
This is more inline with what the functions name suggests it should
do, and makes the code much easier to follow.
This will also make adding uniform packing support much simpler.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Wed, 29 Nov 2017 03:13:17 +0000 (13:13 +1000)]
r600: lds load cleanups.
This is just some cleanups on top of the last patch from my compute branch.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Gert Wollny [Wed, 15 Nov 2017 09:29:12 +0000 (10:29 +0100)]
r600_shader: only load from LDS what is really used
Use the destination write mask to determine which values are really to be
read from LDS and load only these.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Dave Airlie [Sun, 26 Nov 2017 23:36:39 +0000 (23:36 +0000)]
r600/sb: handle jump after target to end of program. (v2)
This fixes hangs on cayman with
tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test
This has a single if/else in it, and when this peephole activated,
it would set the jump target to NULL if there was no instruction
after the final POP. This adds a NOP if we get a jump in this case,
and seems to fix the hangs, so we have a valid target for the ELSE
instruction to go to, instead of 0 (which causes infinite loops).
v2: update last_cf correctly. (I had some other patches hide this)
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Tue, 28 Nov 2017 16:12:45 +0000 (08:12 -0800)]
i965: Change a ret == -1 check to ret != 0.
For consistency with most other ret checks. Suggested by Chris.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Kenneth Graunke [Sun, 26 Nov 2017 09:14:26 +0000 (01:14 -0800)]
i965: Use C99 struct initializers in brw_bufmgr.c.
This is cleaner than using a non-standard memclear macro (which does a
memset to 0) and then initializing fields after the fact. We move the
declarations to where we initialized the fields. While we're at it, we
move the declaration of 'ret' that goes with the ioctl, eliminating the
declaration section altogether.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>