Lux Aliaga [Mon, 6 Mar 2023 17:08:14 +0000 (14:08 -0300)]
arm64: dts: qcom: sm6125: Add UFS nodes
Adds a UFS host controller node and its corresponding PHY to
the sm6125 platform.
Signed-off-by: Lux Aliaga <they@mint.lgbt>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230306170817.3806-5-they@mint.lgbt
Jianhua Lu [Thu, 23 Mar 2023 00:59:25 +0000 (08:59 +0800)]
arm64: dts: qcom: sm8250-xiaomi-elish-csot: Add Xiaomi Mi Pad 5 Pro CSOT variant
Add support for the Xiaomi Mi Pad 5 Pro CSOT variant. The CSOT variant
uses China Star Optoelectronics Technology (CSOT) panel based on NT36523
display controller.
Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323005925.23179-3-lujianhua000@gmail.com
Jianhua Lu [Thu, 23 Mar 2023 00:59:24 +0000 (08:59 +0800)]
arm64: dts: qcom: sm8250-xiaomi-elish-boe: Add mdss and dsi panel
Add nodes for BOE NT36523 panel found in xiaomi-elish. This panel
is a dual dsi mode panel and the dsi phy type is cphy.
Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323005925.23179-2-lujianhua000@gmail.com
Jianhua Lu [Thu, 23 Mar 2023 00:59:23 +0000 (08:59 +0800)]
arm64: dts: qcom: Split elish dts into common dtsi and elish-boe dts
There are two panel variants of xiaomi-elish, BOE and CSOT panels.
In order to support both panels, so split elish dts into common dtsi
and elish-boe dts.
Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323005925.23179-1-lujianhua000@gmail.com
Krzysztof Kozlowski [Wed, 22 Mar 2023 17:41:48 +0000 (18:41 +0100)]
arm64: dts: qcom: sm8150: add compatible fallback to mailbox
SC8150 mailbox is compatible with SDM845.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-12-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 22 Mar 2023 17:41:47 +0000 (18:41 +0100)]
arm64: dts: qcom: sc7180: add compatible fallback to mailbox
SC7180 mailbox is compatible with SDM845.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-11-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 22 Mar 2023 17:41:46 +0000 (18:41 +0100)]
arm64: dts: qcom: qcs404: add compatible fallback to mailbox
QCS404 mailbox is compatible with MSM8916.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-10-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 22 Mar 2023 17:41:45 +0000 (18:41 +0100)]
arm64: dts: qcom: sm6125: add compatible fallback to mailbox
SM6125 mailbox is compatible with MSM8994.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-9-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 22 Mar 2023 17:41:44 +0000 (18:41 +0100)]
arm64: dts: qcom: sm6115: add compatible fallback to mailbox
SM6115 mailbox is compatible with MSM8994.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-8-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 22 Mar 2023 17:41:43 +0000 (18:41 +0100)]
arm64: dts: qcom: sdm630: add compatible fallback to mailbox
SDM630 mailbox is compatible with MSM8994.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-7-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 22 Mar 2023 17:41:42 +0000 (18:41 +0100)]
arm64: dts: qcom: msm8998: add compatible fallback to mailbox
MSM8998 mailbox is compatible with MSM8994.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-6-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 22 Mar 2023 17:41:41 +0000 (18:41 +0100)]
arm64: dts: qcom: msm8976: add compatible fallback to mailbox
MSM8976 mailbox is compatible with MSM8994.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-5-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 22 Mar 2023 17:41:40 +0000 (18:41 +0100)]
arm64: dts: qcom: ipq8074: add compatible fallback to mailbox
IPQ8074 mailbox is compatible with IPQ6018.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322174148.810938-4-krzysztof.kozlowski@linaro.org
Konrad Dybcio [Wed, 5 Apr 2023 15:50:34 +0000 (17:50 +0200)]
arm64: dts: qcom: Add initial QTI RB1 device tree
Add an initial device tree for the QTI RB1 development board, based on
the QRB2210 (QCM2290 derivative) SoC. This device tree targets the SoM
revision 4, a.k.a. the Mass Production SKU.
To get a successful boot, run:
cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/qrb2210-rb1.dtb >\
.Image.gz-dtb
mkbootimg \
--kernel .Image.gz-dtb \
--ramdisk some_initrd \
--output rb1-boot.img \
--pagesize 4096 \
--base 0x8000 \
--cmdline 'some cmdline'
fastboot boot rb1-boot.img
There's no dtbo or other craziness to worry about.
For the best dev experience, you can erase boot and use fastboot boot
everytime, so that the bootloader doesn't mess with you.
If you have a SoM revision 3 or older (there should be a sticker on it
with text like -r00, where r is the revision), you will need to apply
this additional diff:
aliases {
- serial0 = &uart0;
+ serial0 = &uart4;
/* UART connected to the Micro-USB port via a FTDI chip */
- &uart0 {
+ &uart4 {
That should however only concern preproduction boards.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230403-topic-rb1_qcm-v2-5-dae06f8830dc@linaro.org
Konrad Dybcio [Wed, 5 Apr 2023 15:50:33 +0000 (17:50 +0200)]
arm64: dts: qcom: Add initial PM2250 device tree
Introduce an initial device tree for the PM2250 (sometimes known as
PM4125) PMIC.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230403-topic-rb1_qcm-v2-4-dae06f8830dc@linaro.org
Konrad Dybcio [Wed, 5 Apr 2023 15:50:32 +0000 (17:50 +0200)]
arm64: dts: qcom: Add initial QCM2290 device tree
Add an initial device tree for the QCM2290 low-end SoC, featuring 4
"customized" Cortex-A53 cores and up to 4 GiB of LPDDR(3/4X).
This revision brings support for:
- TSENS & thermal zones
- SDHCI1/2
- I2C, SPI, UART
- MPSS
- ADSP
- Wi-Fi
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230403-topic-rb1_qcm-v2-3-dae06f8830dc@linaro.org
Konrad Dybcio [Thu, 6 Apr 2023 12:55:45 +0000 (14:55 +0200)]
arm64: dts: qcom: sdm845-polaris: Drop inexistent properties
Drop the qcom,snoc-host-cap-skip-quirk that was never introduced to
solve schema warnings.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406-topic-ath10k_bindings-v3-2-00895afc7764@linaro.org
Dylan Van Assche [Thu, 6 Apr 2023 17:31:48 +0000 (19:31 +0200)]
arm64: dts: qcom: sdm845-shift-axolotl: enable SLPI
Enable the SLPI DSP on the SHIFTPHONES SHIFT6mq phone with a
Qualcomm SDM845 SoC.
Signed-off-by: Dylan Van Assche <me@dylanvanassche.be>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406173148.28309-6-me@dylanvanassche.be
Dylan Van Assche [Thu, 6 Apr 2023 17:31:47 +0000 (19:31 +0200)]
arm64: dts: qcom: sdm845-oneplus: enable SLPI
Enable the SLPI DSP on the Oneplus 6 phone with a Qualcomm SDM845 SoC.
Signed-off-by: Dylan Van Assche <me@dylanvanassche.be>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406173148.28309-5-me@dylanvanassche.be
Dylan Van Assche [Thu, 6 Apr 2023 17:31:46 +0000 (19:31 +0200)]
arm64: dts: qcom: sdm845: add SLPI FastRPC support
Qualcomm SDM845 SoC features a SLPI DSP which uses FastRPC through
an allocated memory region to load files from the host filesystem
such as sensor configuration files.
Add a FastRPC node at /dev/fastrpc-sdsp and a DMA region, similar to
downstream, to allow userspace to communicate with the SLPI via the
FastRPC interface for initializing the sensors on the SLPI.
Signed-off-by: Dylan Van Assche <me@dylanvanassche.be>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406173148.28309-4-me@dylanvanassche.be
Dylan Van Assche [Thu, 6 Apr 2023 17:31:45 +0000 (19:31 +0200)]
dt-bindings: firmware: qcom: scm: add SSC_Q6 and ADSP_Q6 VMIDs
SSC_Q6 and ADSP_Q6 are used in the FastRPC driver for accessing
the secure world.
Signed-off-by: Dylan Van Assche <me@dylanvanassche.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406173148.28309-3-me@dylanvanassche.be
Dylan Van Assche [Thu, 6 Apr 2023 17:31:44 +0000 (19:31 +0200)]
arm64: dts: qcom: sdm845: add SLPI remoteproc
Add the SLPI remoteproc to the SDM845 Qualcomm SoC which is responsible
for exposing the sensors connected to the SoC. The SLPI communicates
over GLink edge 'dsps' and is similar to other DSPs e.g. ADSP or CDSP.
This patch allows the SLPI to boot and expose itself over QRTR as
service 400.
Signed-off-by: Dylan Van Assche <me@dylanvanassche.be>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406173148.28309-2-me@dylanvanassche.be
Bartosz Golaszewski [Thu, 6 Apr 2023 19:28:11 +0000 (21:28 +0200)]
arm64: dts: qcom: sa8775p-ride: add PMIC regulators
Add PMIC regulators for sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406192811.460888-4-brgl@bgdev.pl
Konrad Dybcio [Fri, 7 Apr 2023 13:28:36 +0000 (15:28 +0200)]
arm64: dts: qcom: sdm845-oneplus: Fix speaker GPIO node
Drop the unnecessary mux{} level to make dtbs check happy.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230407-topic-msm_dtb-v1-6-6efb4196f51f@linaro.org
Konrad Dybcio [Fri, 7 Apr 2023 13:28:35 +0000 (15:28 +0200)]
arm64: dts: qcom: pm8916: Fix pm8941-misc node name
Fix the node name to make dtbs_check happy:
qcom/apq8016-sbc.dtb: pmic@0: 'extcon@1300' does not match any of the
regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$',
'^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^charger@[0-9a-f]+$',
'^mpps@[0-9a-f]+$', '^nvram@[0-9a-f]+$', '^rtc@[0-9a-f]+$',
'^temp-alarm@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$',
'^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$',
'gpio@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$'
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230407-topic-msm_dtb-v1-5-6efb4196f51f@linaro.org
Konrad Dybcio [Fri, 7 Apr 2023 13:28:34 +0000 (15:28 +0200)]
arm64: dts: qcom: sc7280: Fix up the gic node
Fix the following schema warning:
gic-its@
17a40000: False schema does not allow {'compatible':
['arm,gic-v3-its'], 'msi-controller': True, '#msi-cells': [[1]],
'reg': [[0,
396623872, 0, 131072]], 'status': ['disabled']}
And reorder the properties to be more in order with all other nodes.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230407-topic-msm_dtb-v1-4-6efb4196f51f@linaro.org
Douglas Anderson [Thu, 23 Mar 2023 17:30:18 +0000 (10:30 -0700)]
arm64: dts: qcom: sdm845: Fix cheza qspi pin config
Cheza's SPI flash hookups (qspi) are exactly the same as trogdor's.
Apply the same solution that's described in the patch ("arm64: dts:
qcom: sc7180: Fix trogdor qspi pin config")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.14.I82951106ab8170f973a4c1c7d9b034655bbe2f60@changeid
Douglas Anderson [Thu, 23 Mar 2023 17:30:17 +0000 (10:30 -0700)]
arm64: dts: qcom: sc7280: Fix qspi pin config
Similar to sc7180 (see the patch ("arm64: dts: qcom: sc7180: Fix
trogdor qspi pin config")), we should adjust the qspi pin config for
sc7280.
I won't re-describe all the research/arguments in the sc7180 patch
here, but there are a few differences for sc7280 worth noting:
1. On herobrine the SPI flash (qspi) is wired up differently on the
board. Rather than Cr50 and the AP being wired directly together,
there's actually a mux that will _either_ connect the AP to the
flash or Cr50 to the flash. This means that the internal pulls on
Cr50 don't affect us and we should enable our own pulldowns.
2. On herobrine, EEs added an external pulldown on the MISO line. The
argument in the schematic said that we added it (but not one on
MOSI and CLK) because Cr50 already enabled pulldowns on MOSI and
CLK. ...though, as per #1, those Cr50 pulldowns would only affect
the line when the mux was swung to Cr50.
The ironic result of #1 and #2 is that the external pulldowns on
CLK/MISO/MOSI on herobrine are _exactly opposite_ of the ones on
trogdor.
3. While I still don't have the actual exact schematics for all
variants of IDP/CRD that were produced, I have some reference
schematics that give me a belief of how the qspi is hooked up
there. From this, I'm fairly certain that all of the older variants
of IDP/CRD either have a pulldown on the CLK/MOSI/MISO lines (maybe
through a direct connect to Cr50) or have no pull (in other words,
they don't have a pullup). I'll go ahead and enable internal
pulldowns on all the lines since that won't hurt to double-pull if
there's an external pulldown and it's nice to have a pulldown if
there's nothing external. Note that this only affects _older_
CRDs. Newer revs are considered "herobrine" (see the hoglin/zoglin
device trees).
4. I didn't find the same strange "auto-switch-to-keeper" at suspend
when probing on sc7280. Whatever pulls (or lack thereof) I left at
suspend time seemed to persist into suspend.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.13.Ib44c3e417c414a4227db8def75ded37ad368212c@changeid
Douglas Anderson [Thu, 23 Mar 2023 17:30:16 +0000 (10:30 -0700)]
arm64: dts: qcom: sc7180: Fix trogdor qspi pin config
In commit
7ec3e67307f8 ("arm64: dts: qcom: sc7180-trogdor: add initial
trogdor and lazor dt") we specified the pull settings on the boot SPI
(the qspi) data lines as pullups to "park" the lines. This seemed like
the right thing to do, but I never really probed the lines to confirm.
Since that time, I've done A LOT of research, experiements and poking
of the lines with a voltmeter.
A first batch of discoveries:
- There is an external pullup on CS (clearly shown on schematics)
- There are weak external pulldowns on CLK/MOSI (believed to be Cr50's
internal pulldowns)
- There is no pull on MISO.
- When qspi isn't actively transferring it still drives CS, CLK, and
MOSI. CS and MOSI are driven high and CLK is driven low. It does not
drive MISO and (if no internal pulls are enabled) the line floats.
The above means that it's good to have some sort of pull on MISO, at
the very least. The pullup that we had before was actually fine (and
my voltmeter confirms that it actually affected the state of the pin)
but a pulldown would work equally well (and would match MOSI and CLK
better).
The above also means that we could save a tiny bit of power (not
measurable by my setup) by setting up a sleep state for these pins. If
nothing else this prevents us from driving high against Cr50's
internal pulldown on MOSI. However, Qualcomm has also asserted in the
past that it burns a little extra power to drive a pin, especially
since these are configured with a slightly higher drive strength
Let's fix all this. Since the external pulls are different for the two
data lines, we'll split them into separate configs. Then we'll change
the MISO pin to a pulldown and add a sleep state.
On a slightly tangental (but not totally unrelated note), I also
discovered some interesting things with these pins in suspend. First,
I found that if we don't switch the pins to GPIO that the qspi
peripheral continues to drive them in suspend. That'll be solved by
what we're already doing above. Second, I found that something in the
system suspend path (after Linux stops running) reconfigures these
pins so that they don't have their normal pulls enabled but instead
change to "keepers" (bias-bus-hold in DT speak). If a pin was floating
before we entered suspend then it would stop floating. I found that I
could manually pull a pin to a different level and then probe it and
it would stay there. This is exactly keeper behavior. With the
solution we have the switch to "keeper" doesn't matter too much but
it's good to document.
While talking about "keepers", it can also be noted that I found that
the "keepers" on these pins were at least enough to win a fight
against Cr50's internal pulls. That means it's best to make sure that
the state of the pins are already correct before the mysterious
transition to a keeper. Otherwise we'll burn (a small amount of) power
in S3 via this fight. Luckily with the current solution we don't hit
this case.
NOTE: I've left "sc7180-idp" behavior totally alone in this patch. I
didn't add a sleep state and I didn't change any pulls--I just adapted
it to the fact that the data lines have separate configs. Qualcomm
doesn't provide me with schematics for IDP and thus I don't actually
know how the pulls are configured. Since this is just a development
platform and worked well enough, it seems safer to leave it alone.
Dependencies:
- This patch has a hard dependency on ("pinctrl: qcom: Support
OUTPUT_ENABLE; deprecate INPUT_ENABLE"). Something in the boot code
seemed to have been confused and thought it needed to set the
"OUTPUT ENABLE" bit for these pins even though it was using them as
SPI. Thus if we don't honor the "output-disable" property we could
end up driving the SPI pins while in sleep mode.
- In general, it's probably best not to backport this to a kernel that
doesn't have commit
d21f4b7ffc22 ("pinctrl: qcom: Avoid glitching
lines when we first mux to output"). That landed a while ago, but
it's still good to be explicit in case someone was backporting. If
we don't have that then there might be a glitch when we first switch
over to GPIO before we disable the output.
- This patch _doesn't_ really have any dependency on the qspi driver
patch that supports setting the pinctrl sleep state--they can go in
either order. If we define the sleep state and the driver never
selects it that's fine. If the driver tries to select a sleep state
that we don't define that's fine.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.12.I6f03f86546e6ce9abb1d24fd9ece663c3a5b950c@changeid
Douglas Anderson [Thu, 23 Mar 2023 17:30:15 +0000 (10:30 -0700)]
arm64: dts: qcom: sdm845: Remove superfluous "input-enable"s from cheza
As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should
use output-disable, not input-enable"), using "input-enable" in
pinctrl states for Qualcomm TLMM pinctrl devices was either
superfluous or there to disable a pin's output.
Looking at cheza
* ec_ap_int_l, h1_ap_int_odl: Superfluous. The pins will be configured
as inputs automatically by the Linux GPIO subsystem (presumably the
reference for other OSes using these device trees).
* bios_flash_wp_l: Superfluous. This pin is exposed to userspace
through the kernel's GPIO API and will be configured automatically.
That means that in none of the cases for cheza did we need to change
"input-enable" to "output-disable" and we can just remove these
superfluous properties.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.11.Ia439c29517b1c0625325a54387b047f099d16425@changeid
Douglas Anderson [Thu, 23 Mar 2023 17:30:14 +0000 (10:30 -0700)]
arm64: dts: qcom: sc7280: Remove superfluous "input-enable"s from idp-ec-h1
As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should
use output-disable, not input-enable"), using "input-enable" in
pinctrl states for Qualcomm TLMM pinctrl devices was either
superfluous or there to disable a pin's output.
Looking at the sc7280-idp-ec-h1.dtsi file:
* ap_ec_int_l, h1_ap_int_odl: Superfluous. The pins will be configured
as inputs automatically by the Linux GPIO subsystem (presumably the
reference for other OSes using these device trees).
That means that in none of the cases for sc7280-idp-ec-h1.dtsi did we
need to change "input-enable" to "output-disable" and we can just
remove these superfluous properties.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.10.I1343c20f4aaac8e2c1918b756f7ed66f6ceace9c@changeid
Douglas Anderson [Thu, 23 Mar 2023 17:30:13 +0000 (10:30 -0700)]
arm64: dts: qcom: sc7180: Remove superfluous "input-enable"s from trogdor
As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should
use output-disable, not input-enable"), using "input-enable" in
pinctrl states for Qualcomm TLMM pinctrl devices was either
superfluous or there to disable a pin's output.
Looking at trogdor:
* ap_ec_int_l, fp_to_ap_irq_l, h1_ap_int_odl, p_sensor_int_l:
Superfluous. The pins will be configured as inputs automatically by
the Linux GPIO subsystem (presumably the reference for other OSes
using these device trees).
* bios_flash_wp_l: Superfluous. This pin is exposed to userspace
through the kernel's GPIO API and will be configured automatically.
That means that in none of the cases for trogdor did we need to change
"input-enable" to "output-disable" and we can just remove these
superfluous properties.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.9.I94dbc53176e8adb0d7673b7feb2368e85418f938@changeid
Douglas Anderson [Thu, 23 Mar 2023 17:30:08 +0000 (10:30 -0700)]
arm64: dts: qcom: sc7180: Annotate l13a on trogdor to always-on
The l13a rail on trogdor devices has always been intended to be
always-on on both S0 and S3. Different trogdor variants use l13a in
slightly different ways, but the overall theme is that it's a 1.8V
rail that the board uses for things that it wants powered in on S0 and
S3. On many boards this includes the boot SPI (AKA qspi).
For all intents and purposes this patch is actually a no-op since
something else in the system seems to already be keeping the rail on
all the time (confirmed via multimeter). That "something else" was
postulated to be the modem but the rail is on / stays on even without
the modem/wifi coming up so it's likely the boot config. In any case,
making the fact that this is always-on explicit seems like a good
idea.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.4.I9f47a8a53eacff6229711a827993792ceeb36971@changeid
Douglas Anderson [Thu, 23 Mar 2023 17:30:07 +0000 (10:30 -0700)]
arm64: dts: sdm845: Rename qspi data12 as data23
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.
Fixes:
e1ce853932b7 ("arm64: dts: qcom: sdm845: Add qspi (quad SPI) node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.3.I88528d037b7fda4e53a40f661be5ac61628691cd@changeid
Douglas Anderson [Thu, 23 Mar 2023 17:30:06 +0000 (10:30 -0700)]
arm64: dts: sc7280: Rename qspi data12 as data23
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.
Fixes:
7720ea001b52 ("arm64: dts: qcom: sc7280: Add QSPI node")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.2.I4043491bb24b1e92267c5033d76cdb0fe60934da@changeid
Douglas Anderson [Thu, 23 Mar 2023 17:30:05 +0000 (10:30 -0700)]
arm64: dts: sc7180: Rename qspi data12 as data23
There are 4 qspi data pins: data0, data1, data2, and data3. Currently
we have a shared pin state for data0 and data1 (2 lane config) and a
pin state for data2 and data3 (you'd enable both this and the 2 lane
state for 4 lanes). The second state is obviously misnamed. Fix it.
Fixes:
ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323102605.1.Ifc1b5be04653f4ab119698a5944bfecded2080d6@changeid
Bjorn Andersson [Fri, 7 Apr 2023 17:51:26 +0000 (10:51 -0700)]
Merge branch 'ib-qcom-quad-spi' of https://git./linux/kernel/git/linusw/linux-pinctrl into arm64-for-6.4
Merge the support for output-enable/disable in the pinctrl-msm driver,
to ensure that bisection across the following SC7180/SC7280 DeviceTree
changes result in something electrically sound.
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Devi Priya [Thu, 16 Mar 2023 07:29:39 +0000 (12:59 +0530)]
arm64: dts: qcom: Add ipq9574 SoC and AL02 board support
Add initial device tree support for Qualcomm IPQ9574 SoC and AL02 board
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Co-developed-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316072940.29137-6-quic_devipriy@quicinc.com
Bjorn Andersson [Fri, 7 Apr 2023 17:35:12 +0000 (10:35 -0700)]
Merge branch '
20230316072940.29137-2-quic_devipriy@quicinc.com' into HEAD
Merge the IPQ9574 Global Clock Controller Devicetree binding, to make
available the clock definitions used in the Devicetree source.
Devi Priya [Thu, 16 Mar 2023 07:29:35 +0000 (12:59 +0530)]
dt-bindings: clock: Add ipq9574 clock and reset definitions
Add clock and reset ID definitions for ipq9574
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316072940.29137-2-quic_devipriy@quicinc.com
Petr Vorel [Tue, 31 Jan 2023 20:04:14 +0000 (21:04 +0100)]
arm64: dts: qcom: msm8994-angler: removed clash with smem_region
This fixes memory overlap error:
[ 0.000000] reserved@6300000 (0x0000000006300000--0x0000000007000000) overlaps with smem_region@6a00000 (0x0000000006a00000--0x0000000006c00000)
smem_region is the same as in downstream (qcom,smem) [1], therefore
split reserved memory into two sections on either side of smem_region.
Not adding labels as it's not expected to be used.
[1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm/boot/dts/qcom/msm8994.dtsi#948
Fixes:
380cd3a34b7f ("arm64: dts: msm8994-angler: fix the memory map")
Signed-off-by: Petr Vorel <pvorel@suse.cz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230131200414.24373-3-pvorel@suse.cz
Petr Vorel [Tue, 31 Jan 2023 20:04:13 +0000 (21:04 +0100)]
arm64: dts: qcom: msm8994-angler: Fix cont_splash_mem mapping
Angler's cont_splash_mem mapping is shorter in downstream [1],
therefore
380cd3a34b7f was wrong. Obviously also
0e5ded926f2a was wrong
(workaround which fixed booting at the time).
This fixes error:
[ 0.000000] memory@3401000 (0x0000000003401000--0x0000000005601000) overlaps with tzapp@4800000 (0x0000000004800000--0x0000000006100000)
[1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm64/boot/dts/huawei/huawei_msm8994_angler_row_vn1/huawei-fingerprint.dtsi#16
Fixes:
380cd3a34b7f ("arm64: dts: msm8994-angler: fix the memory map")
Fixes:
0e5ded926f2a ("arm64: dts: qcom: msm8994-angler: Disable cont_splash_mem")
Signed-off-by: Petr Vorel <pvorel@suse.cz>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230131200414.24373-2-pvorel@suse.cz
Douglas Anderson [Thu, 30 Mar 2023 21:11:00 +0000 (14:11 -0700)]
MAINTAINERS: qcom: Add reviewer for Qualcomm Chromebooks
Developers on the ChromeOS team generally want to be notified to
review changes that affect Chromebook device tree files. While we
could individually add developers, the set of developers and the time
each one has available to review patches will change over time. Let's
try adding a group list as a reviewer and see if that's an effective
way to manage things.
A few notes:
* Though this email address is actually backed by a mailing list, I'm
adding it as "R"eviewer and not "L"ist since it's not a publicly
readable mailing list and it's intended just to have a few people on
it. This also hopefully conveys a little more responisbility for the
people that are part of this group.
* I've added all sc7180 and sc7280 files here. At the moment I'm not
aware of any non-Chromebooks being supported that use these
chips. If later something shows up then we can try to narrow down.
* I've added "sdm845-cheza" to this list but not the rest of
"sdm845". Cheza never shipped but some developers still find the old
developer boards useful and thus it continues to get minimal
maintenance. Most sdm845 device tree work, however, seems to be for
non-Chromebooks.
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230330141051.1.If8eb4f30cb53a00a5bef1b7d3cc645c3536615ec@changeid
Kathiravan T [Mon, 20 Mar 2023 10:45:30 +0000 (16:15 +0530)]
arm64: dts: qcom: ipq5332: add few device nodes
Add the nodes for QUP peripheral, PRNG and WDOG. While at it, enable the
I2C device for MI01.2 board.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230320104530.30411-3-quic_kathirav@quicinc.com
Krzysztof Kozlowski [Fri, 10 Mar 2023 13:49:25 +0000 (14:49 +0100)]
arm64: dts: qcom: sm8550: add ADSP audio codec macros
Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on
Qualcomm SM8550. The nodes are very similar to SM8450, except missing
NPL clock which is not exposed on SM8550 and should not be touched.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230310134925.514125-1-krzysztof.kozlowski@linaro.org
Manivannan Sadhasivam [Wed, 8 Mar 2023 07:56:48 +0000 (13:26 +0530)]
arm64: dts: qcom: Remove "iommus" property from PCIe nodes
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map"
properties for the PCIe nodes. First one passes the SMR mask to the iommu
driver and the latter specifies the SID for each PCIe device.
But with "iommus" property, the PCIe controller will be added to the
iommu group along with the devices. This makes no sense because the
controller will not initiate any DMA transaction on its own. And moreover,
it is not strictly required to pass the SMR mask to the iommu driver. If
the "iommus" property is not present, then the default mask of "0" would be
used which should work for all PCIe devices.
On the other side, if the SMR mask specified doesn't match the one expected
by the hypervisor, then all the PCIe transactions will end up triggering
"Unidentified Stream Fault" by the SMMU.
So to get rid of these hassles and also prohibit PCIe controllers from
adding to the iommu group, let's remove the "iommus" property from PCIe
nodes.
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308075648.134119-1-manivannan.sadhasivam@linaro.org
Krzysztof Kozlowski [Wed, 5 Apr 2023 06:09:06 +0000 (08:09 +0200)]
arm64: dts: qcom: sm8450: simplify interrupts-extended
The parent controller for both interrupts is GIC, so no need for
interrupts-extended.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-5-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 5 Apr 2023 06:09:05 +0000 (08:09 +0200)]
arm64: dts: qcom: sm8250: simplify interrupts-extended
The parent controller for the interrupt is GIC, so no need for
interrupts-extended.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-4-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 5 Apr 2023 06:09:04 +0000 (08:09 +0200)]
arm64: dts: qcom: sc8280xp: simplify interrupts-extended
The parent controller for both interrupts is GIC, so no need for
interrupts-extended.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-3-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 5 Apr 2023 06:09:03 +0000 (08:09 +0200)]
arm64: dts: qcom: sm8450: label the Soundwire nodes
Use labels, instead of comments, for Soundwire controllers. Naming them
is useful, because they are specialized and have also naming in
datasheet/programming guide.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 5 Apr 2023 06:09:02 +0000 (08:09 +0200)]
arm64: dts: qcom: sc8280xp: label the Soundwire nodes
Use labels, instead of comments, for Soundwire controllers. Naming them
is useful, because they are specialized and have also naming in
datasheet/programming guide.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230405060906.143058-1-krzysztof.kozlowski@linaro.org
Konrad Dybcio [Sat, 18 Mar 2023 13:42:55 +0000 (14:42 +0100)]
arm64: dts: qcom: sm6115: Use the correct DSI compatible
Use the non-deprecated, SoC-specific DSI compatible.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230307-topic-dsi_qcm-v6-9-70e13b1214fa@linaro.org
Steev Klimaszewski [Sun, 26 Mar 2023 23:38:12 +0000 (18:38 -0500)]
arm64: dts: qcom: sc8280xp-x13s: Add bluetooth
The Lenovo Thinkpad X13s has a WCN6855 Bluetooth controller on uart2,
add this.
Signed-off-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230326233812.28058-5-steev@kali.org
Bjorn Andersson [Sun, 26 Mar 2023 23:38:11 +0000 (18:38 -0500)]
arm64: dts: qcom: sc8280xp: Define uart2
Add the definition for uart2 for sc8280xp devices.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230326233812.28058-4-steev@kali.org
Manivannan Sadhasivam [Thu, 16 Mar 2023 08:11:16 +0000 (13:41 +0530)]
arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316081117.14288-19-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Thu, 16 Mar 2023 08:11:15 +0000 (13:41 +0530)]
arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316081117.14288-18-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Thu, 16 Mar 2023 08:11:14 +0000 (13:41 +0530)]
arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes
The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316081117.14288-17-manivannan.sadhasivam@linaro.org
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:13 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
Set line names for GPIO lines exposed by PMICs on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-16-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:12 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes
Add GPIO controller nodes to PMICs that have the GPIO hooked up on
sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-15-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:09 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p: pmic: add thermal zones
Add the thermal zones and associated alarm nodes for the PMICs that have
them hooked up on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-12-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:08 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input
Add the RESIN input for sa8775p platforms' PMIC.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-11-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:07 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p: pmic: add the power key
Add the power key node under the PON node for PMIC #0 on sa8775p.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-10-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:06 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p: add the Power On device node
Add the PON node to PMIC #0 for sa8775p platforms.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-9-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:05 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p: add support for the on-board PMICs
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced
to the SoC via SPMI. Enable the PMICs for sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-8-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:03 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p: add the spmi node
Add the SPMI PMIC Arbiter node for SA8775p platforms.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-6-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:02 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p: add the pdc node
Add the Power Domain Controller node for SA8775p.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-5-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:53:00 +0000 (14:53 +0200)]
arm64: dts: qcom: sa8775p: sort soc nodes by reg property
Sort all children of the soc node by the first address in their reg
property. This was mostly already the case but there were some nodes
that didn't follow it so fix it now for consistency.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-3-brgl@bgdev.pl
Bartosz Golaszewski [Mon, 27 Mar 2023 12:52:59 +0000 (14:52 +0200)]
arm64: dts: qcom: sa8775p: pad reg properties to 8 digits
The file has inconsistent padding of the address part of soc node
children's reg properties. Fix it.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-2-brgl@bgdev.pl
Krzysztof Kozlowski [Mon, 3 Apr 2023 13:23:28 +0000 (15:23 +0200)]
arm64: dts: qcom: sc8280xp: correct Soundwire wakeup interrupt name
The bindings expect second Soundwire interrupt to be "wakeup" (Linux
driver takes by index):
sc8280xp-crd.dtb: soundwire-controller@3330000: interrupt-names:1: 'wakeup' was expected
Fixes:
c18773d162a6 ("arm64: dts: qcom: sc8280xp: add SoundWire and LPASS")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230403132328.61414-1-krzysztof.kozlowski@linaro.org
Konrad Dybcio [Wed, 29 Mar 2023 19:41:23 +0000 (21:41 +0200)]
arm64: dts: qcom: sdm845-tama: Enable GPI_DMA0/1
Enable both GPI DMAs.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-6-2b1567c039d7@linaro.org
Konrad Dybcio [Wed, 29 Mar 2023 19:41:22 +0000 (21:41 +0200)]
arm64: dts: qcom: sdm845-tama: Enable GPU
Enable the A630 GPU and its GMU.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-5-2b1567c039d7@linaro.org
Konrad Dybcio [Wed, 29 Mar 2023 19:41:21 +0000 (21:41 +0200)]
arm64: dts: qcom: sdm845-tama: Enable remoteprocs
Enable ADSP, CDSP and Venus.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-4-2b1567c039d7@linaro.org
Konrad Dybcio [Wed, 29 Mar 2023 19:41:20 +0000 (21:41 +0200)]
arm64: dts: qcom: sdm845-tama: Add regulator-system-load to l14a/l28a
Add the properties to ensure the ever so delicate touchscreen setup
matches downstream.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-3-2b1567c039d7@linaro.org
Konrad Dybcio [Wed, 29 Mar 2023 19:41:19 +0000 (21:41 +0200)]
arm64: dts: qcom: sdm845-tama: Add Synaptics Touchscreen
Add required pins and RMI4 node to the common DT and remove it
from Akatsuki, as it uses a different touch.
Since the panels are super high tech proprietary incell, they
need to be handled with very precise timings. As such the panel
driver sets up the power rails and GPIOs and the touchscreen
driver *has to* probe afterwards.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-2-2b1567c039d7@linaro.org
Konrad Dybcio [Wed, 29 Mar 2023 19:41:18 +0000 (21:41 +0200)]
arm64: dts: qcom: sdm845-tama: Add display nodes
Add required nodes to support display on XZ2/XZ2c. XZ3 has a
different power rail setup and needs to be handled separately.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-1-2b1567c039d7@linaro.org
Adam Skladowski [Sat, 25 Mar 2023 11:28:52 +0000 (12:28 +0100)]
arm64: dts: msm8953: Pad regs to 8 digits
Follow other dtses and pad regs to 8 digits.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-4-a39.skl@gmail.com
Adam Skladowski [Sat, 25 Mar 2023 11:28:51 +0000 (12:28 +0100)]
arm64: dts: msm8953: Drop unsupported dwc3 flag
Property phy_mode according to binding checker does not exist,
drop it.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-3-a39.skl@gmail.com
Adam Skladowski [Sat, 25 Mar 2023 11:28:50 +0000 (12:28 +0100)]
arm64: dts: msm8953: Provide dsi_phy clocks to gcc
Provide clocks from dsi_phy to gcc, this will make
sure we don't fallback to global name lookup.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-2-a39.skl@gmail.com
Adam Skladowski [Sat, 25 Mar 2023 11:28:49 +0000 (12:28 +0100)]
arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo
Assign RPM_SMD_XO_CLK_SRC from rpmcc in place
of fixed-clock where possible.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230325112852.18841-1-a39.skl@gmail.com
Neil Armstrong [Fri, 24 Mar 2023 09:28:47 +0000 (10:28 +0100)]
arm64: dts: qcom: sm8450: remove invalid properties in cluster-sleep nodes
Fixes the following DT bindings check error:
domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'
domain-idle-states: cluster-sleep-1: 'idle-state-name', 'local-timer-stop' do not match any of the regexes:
'pinctrl-[0-9]+'
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-2-0ca1bea1a843@linaro.org
Krzysztof Kozlowski [Fri, 24 Mar 2023 07:38:13 +0000 (08:38 +0100)]
arm64: dts: qcom: sc8280xp: drop incorrect domain idle states properties
Domain idle states do not use 'idle-state-name':
sc8280xp-crd.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+'
Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230324073813.22158-6-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Fri, 24 Mar 2023 07:38:12 +0000 (08:38 +0100)]
arm64: dts: qcom: sm8350: drop incorrect domain idle states properties
Domain idle states do not use 'idle-state-name' and 'local-timer-stop':
sm8350-mtp.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+'
Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230324073813.22158-5-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Fri, 24 Mar 2023 07:38:11 +0000 (08:38 +0100)]
arm64: dts: qcom: sm8150: drop incorrect domain idle states properties
Domain idle states do not use 'idle-state-name' and 'local-timer-stop':
sm8150-hdk.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+'
Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230324073813.22158-4-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Fri, 24 Mar 2023 07:38:10 +0000 (08:38 +0100)]
arm64: dts: qcom: sm6375: drop incorrect domain idle states properties
Domain idle states do not use 'idle-state-name' and 'local-timer-stop':
sm6375-sony-xperia-murray-pdx225.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+'
Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230324073813.22158-3-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Fri, 24 Mar 2023 07:38:09 +0000 (08:38 +0100)]
arm64: dts: qcom: sdm845: drop incorrect domain idle states properties
Domain idle states do not use 'idle-state-name' and 'local-timer-stop':
sdm845-shift-axolotl.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+'
Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230324073813.22158-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Fri, 24 Mar 2023 07:38:08 +0000 (08:38 +0100)]
arm64: dts: qcom: sm8250: drop incorrect domain idle states properties
Domain idle states do not use 'idle-state-name' and 'local-timer-stop':
sm8250-hdk.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+'
Reported-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230324073813.22158-1-krzysztof.kozlowski@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:13:03 +0000 (15:13 +0100)]
arm64: dts: qcom: sm6375-pdx225: Add volume down GPIO key
Add the required nodes to enable the volume down key on the Sony
Xperia 10 IV.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-14-708b8191f7eb@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:13:02 +0000 (15:13 +0100)]
arm64: dts: qcom: sm6375: Introduce C3 power state for both ARM clusters
Introduce the C3 power state, which - to the best of my understanding -
gates the CPU clock, but does not shut off the power rail.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-13-708b8191f7eb@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:13:01 +0000 (15:13 +0100)]
arm64: dts: qcom: sm6375: Bump CPU rail power collapse index
In preparation for supporting a less-deep sleep state, rename the
existing rail power off from _0 to _1.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-12-708b8191f7eb@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:13:00 +0000 (15:13 +0100)]
arm64: dts: qcom: sm6375: Configure TSENS thermal zones
Add a thermal zones configuration for all 15+11 TSENS sensors.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-11-708b8191f7eb@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:12:59 +0000 (15:12 +0100)]
arm64: dts: qcom: sm6375: Add TSENS
Add nodes for the two TSENS v2.8.0 controllers present on the SoC.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-10-708b8191f7eb@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:12:58 +0000 (15:12 +0100)]
arm64: dts: qcom: sm6375: Add CPUCP L3 node
Configure the L3 cache DVFS scaler within the CPUCP block to allow
for dynamic frequency switching.
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-9-708b8191f7eb@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:12:57 +0000 (15:12 +0100)]
arm64: dts: qcom: sm6375: Add modem nodes
Add required nodes to make the embedded 5G modem boot up on SM6375.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-8-708b8191f7eb@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:12:56 +0000 (15:12 +0100)]
arm64: dts: qcom: sm6375: Add wifi node
Add a node for ATH10K_SNoC wifi on SM6375.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-7-708b8191f7eb@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:12:54 +0000 (15:12 +0100)]
arm64: dts: qcom: sm6375: Add IMEM
Add a node for the IMEM block on SM6375.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-5-708b8191f7eb@linaro.org
Konrad Dybcio [Thu, 16 Mar 2023 14:12:53 +0000 (15:12 +0100)]
arm64: dts: qcom: sm6375: Add RPM sleep stats
Add a node for RPM sleep stats to enable sleep monitoring.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-4-708b8191f7eb@linaro.org
Konrad Dybcio [Wed, 15 Mar 2023 14:11:25 +0000 (15:11 +0100)]
arm64: dts: qcom: sm8550: Use the correct BWMON fallback compatible
Use the correct fallback compatible for the BWMONv4 with merged global and
monitor register spaces.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-7-77a050c2fbda@linaro.org
Konrad Dybcio [Wed, 15 Mar 2023 14:11:24 +0000 (15:11 +0100)]
arm64: dts: qcom: sdm845: Use the correct BWMON compatible
Drop the incorrect msm8998 fallback and use the new qcom,sdm845-cpu-bwmon
compatible to distinguish the CPU BWMON found on this platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-6-77a050c2fbda@linaro.org
Konrad Dybcio [Wed, 15 Mar 2023 14:11:23 +0000 (15:11 +0100)]
arm64: dts: qcom: sc8280xp: Use the correct BWMON fallback compatible
Use the correct fallback compatible for the BWMONv4 with merged global and
monitor register spaces.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-5-77a050c2fbda@linaro.org
Konrad Dybcio [Wed, 15 Mar 2023 14:11:22 +0000 (15:11 +0100)]
arm64: dts: qcom: sc7280: Use the correct BWMON fallback compatible
Use the correct fallback compatible for the BWMONv4 with merged global and
monitor register spaces.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-4-77a050c2fbda@linaro.org