Christian Gmeiner [Sat, 8 Jul 2023 15:37:35 +0000 (17:37 +0200)]
nir/lower_tex: optimize offset lowering for has_texture_scaling
Generates much better code and even helps to beat a blob driver.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24054>
Christian Gmeiner [Mon, 10 Jul 2023 20:24:46 +0000 (22:24 +0200)]
nir: rename has_txs to has_texture_scaling
Convert it to an opt-in for backends to prefer and use nir_load_texture_scale
instead of txs for nir lowerings.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Suggested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24054>
Christian Gmeiner [Sat, 8 Jul 2023 15:43:31 +0000 (17:43 +0200)]
nir: rename intrinsic to have a more generic nameing
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24054>
Eric Engestrom [Wed, 12 Jul 2023 07:51:43 +0000 (08:51 +0100)]
etnaviv/ci: drop duplicate line in etnaviv files list
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24106>
Karol Herbst [Thu, 22 Jun 2023 14:43:40 +0000 (16:43 +0200)]
nvc0: backport fp helper invocation fix to 2nd gen Maxwell+
Ben prefers that we use the firmware method where possible.
Cc: mesa-stable
Signed-off-by: Karol Herbst <git@karolherbst.de>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23802>
Hyunjun Ko [Wed, 12 Jul 2023 05:07:23 +0000 (14:07 +0900)]
anv: Adds a workaround for HEVC decoding on some old platforms.
HEVC support on Gfx9 is only available on VCS0. So limit the number of video queues
to the first VCS engine instance.
We should be able to query HEVC support from the kernel using the engine query uAPI,
but this appears to be broken : https://gitlab.freedesktop.org/drm/intel/-/issues/8832
When this bug is fixed we should be able to check HEVC support to determine the
correct number of queues.
Closes: mesa/mesa#9172, mesa/mesa#9314
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24065>
Dave Airlie [Tue, 11 Jul 2023 04:41:01 +0000 (14:41 +1000)]
ci: update fails for fixed tests due to llvmpipe linear changes.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
Dave Airlie [Mon, 10 Jul 2023 07:34:50 +0000 (17:34 +1000)]
llvmpipe/linear: add support for rgba color buffers.
This adds support to the linear rast for rgba outputs.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
Dave Airlie [Mon, 10 Jul 2023 07:32:53 +0000 (17:32 +1000)]
llvmpipe/linear: add support for sampling when cbuf order is different.
This rewrites bgra sampling when the output is rgba,
and vice-versa.
It allows to skip swaps if the sampling and cbuf match.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
Dave Airlie [Mon, 10 Jul 2023 07:21:59 +0000 (17:21 +1000)]
llvmpipe/linear: add sample routines for swapping r/b channels
This lets rgba textures be sampled in linear mode.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
Dave Airlie [Mon, 10 Jul 2023 05:39:35 +0000 (15:39 +1000)]
llvmpipe/linear/tgsi: calculate num_texs properly for nir.
This is a bit hacky, but it does the right thing and counts the number
of textures instructions so the linear path can work for multiple textures.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
Dave Airlie [Tue, 11 Jul 2023 03:56:23 +0000 (13:56 +1000)]
llvmpipe/linear: refactor linear samplers into templated code.
Before adding new copies of all of these for swapping start by
refactoring into macro templated code.
I avoided using inline functions because I want to test with
opts turned down, and this will kill perf.
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24066>
Faith Ekstrand [Wed, 12 Jul 2023 00:48:02 +0000 (19:48 -0500)]
freedreno/ci: Update pixmark piano checksums
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Mon, 29 May 2023 17:05:56 +0000 (13:05 -0400)]
pan/mdg: Ingest new-style registers
Switch to register intrinsics, using the helpers. Since our backend copyprop
chokes on non-SSA moves, we get better coalescing with this approach, hence the
small improvements to instruction count / cycle count in shader-db. Changes to
register pressure seem to be noise from iteration order. I'm not too worried.
total instructions in shared programs: 1508444 -> 1508193 (-0.02%)
instructions in affected programs: 42581 -> 42330 (-0.59%)
helped: 482
HURT: 41
Inconclusive result (value mean confidence interval includes 0).
total bundles in shared programs: 643023 -> 643136 (0.02%)
bundles in affected programs: 16318 -> 16431 (0.69%)
helped: 230
HURT: 85
Inconclusive result (value mean confidence interval includes 0).
total quadwords in shared programs: 1125992 -> 1125600 (-0.03%)
quadwords in affected programs: 125366 -> 124974 (-0.31%)
helped: 507
HURT: 351
Quadwords are helped.
total registers in shared programs: 90632 -> 90554 (-0.09%)
registers in affected programs: 669 -> 591 (-11.66%)
helped: 114
HURT: 31
Registers are helped.
total threads in shared programs: 55607 -> 55600 (-0.01%)
threads in affected programs: 20 -> 13 (-35.00%)
helped: 1
HURT: 7
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 1371 -> 1437 (4.81%)
spills in affected programs: 44 -> 110 (150.00%)
helped: 0
HURT: 2
total fills in shared programs: 5133 -> 5273 (2.73%)
fills in affected programs: 84 -> 224 (166.67%)
helped: 0
HURT: 2
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Fri, 9 Jun 2023 15:03:09 +0000 (11:03 -0400)]
gallivm: Switch to reg intrinsics
This is pretty straightforward, since we don't try to "coalesce" register access
the way a GPU backend would. In the old path, we generated register load/store
instructions internally when hitting register sources/destinations. In the new
path, we just translate the register load/store intrinsics to the LLVM
loads/stores and we're back where we started. It's a bit more code, but it's
more straightforward.
Notably, although this continues to use registers, this does NOT use the chasing
helpers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Tue, 23 May 2023 18:46:18 +0000 (14:46 -0400)]
nir: Remove nir_register-based unit tests
Non-SSA functionality will become obsolete after nir_register is removed, so
there's no need to keep the tests around, and they will interfere with the
nir_register de-clawing.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Fri, 26 May 2023 16:30:51 +0000 (12:30 -0400)]
nir: Remove nir_lower_regs_to_ssa
It is now unused, as all internal producers of registers have been switched over
to intrinsics and no drivers call it.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Thu, 25 May 2023 13:05:56 +0000 (09:05 -0400)]
nir/lower_shader_calls: Convert to register intrinsics
Yet another internal use of nir_register that gets lowered back to SSA after the
pass. Easy enough to replace with intrinsic-based registers instead.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Mon, 10 Jul 2023 21:15:42 +0000 (16:15 -0500)]
mesa: Convert PTN to register intrinsics
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Mon, 10 Jul 2023 21:06:50 +0000 (16:06 -0500)]
mesa: Return SSA defs from PTN ALU helpers
Mostly a big simplifcation. Some noise on Haswell shader-db:
total instructions in shared programs: 2978203 -> 2978161 (<.01%)
instructions in affected programs: 9812 -> 9770 (-0.43%)
helped: 61
HURT: 39
helped stats (abs) min: 1 max: 5 x̄: 1.44 x̃: 1
helped stats (rel) min: 0.27% max: 7.69% x̄: 1.76% x̃: 1.18%
HURT stats (abs) min: 1 max: 4 x̄: 1.18 x̃: 1
HURT stats (rel) min: 0.55% max: 16.67% x̄: 4.49% x̃: 3.45%
95% mean confidence interval for instructions value: -0.71 -0.13
95% mean confidence interval for instructions %-change: -0.11% 1.46%
Inconclusive result (%-change mean confidence interval includes 0).
total cycles in shared programs:
45346214 ->
45346684 (<.01%)
cycles in affected programs: 519970 -> 520440 (0.09%)
helped: 157
HURT: 157
helped stats (abs) min: 2 max: 2970 x̄: 166.80 x̃: 6
helped stats (rel) min: 0.05% max: 40.38% x̄: 5.01% x̃: 1.42%
HURT stats (abs) min: 2 max: 1922 x̄: 169.80 x̃: 10
HURT stats (rel) min: 0.04% max: 44.00% x̄: 6.28% x̃: 2.46%
95% mean confidence interval for cycles value: -49.93 52.92
95% mean confidence interval for cycles %-change: -0.49% 1.76%
Inconclusive result (value mean confidence interval includes 0).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Mon, 10 Jul 2023 21:05:50 +0000 (16:05 -0500)]
mesa: Simplify ptn_log() a bit
Using fdiv lets us drop the fneg. nir_opt_algebraic will re-optimize
this if the driver implements fdiv using fmul and frcp.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Mon, 10 Jul 2023 21:00:16 +0000 (16:00 -0500)]
gallium: Convert TTN to register intrinsics
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Tue, 23 May 2023 22:13:05 +0000 (18:13 -0400)]
gallium: Return SSA values from TTN ALU helpers
This is a lot simpler!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Fri, 9 Jun 2023 13:41:21 +0000 (09:41 -0400)]
nir: Add lower_vec_to_regs pass
This is a variant of nir_lower_vec_to_movs that produces register intrinsics
(store_reg with write masks) instead of masked moves.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Fri, 9 Jun 2023 14:20:43 +0000 (10:20 -0400)]
nir: Add intrinsics version of locals_to_regs
This isn't so bad. I still duplicated the pass because it makes a lot easier to
have them coexist, switch users over one by one, and then garbage collect the
old when we're done.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Faith Ekstrand [Fri, 9 Jun 2023 13:36:22 +0000 (09:36 -0400)]
nir/from_ssa: Support register intrinsics
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Faith Ekstrand [Wed, 31 May 2023 18:55:47 +0000 (13:55 -0500)]
nir/from_ssa: Make additional assumptions in coalescing
At this point, everything is SSA. Also, NIR no longer allows different
numbers of components on the two sides of a phi so we can just assert
rather than trying to gracefully handle mismatches.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Mon, 22 May 2023 17:04:05 +0000 (13:04 -0400)]
nir: Produce intrinsics in lower_{phis,ssa_defs}_to_regs
A number of passes lower SSA partially to registers, do work that would be
invalid in SSA, and then go back into SSA with nir_lower_regs_to_ssa. As a step
towards replacing nir_register with intrinsics,
the nir_lower_{phis,ssa_defs}_to_regs passes are changed to produce intrinsics
instead of nir_registers, and their callers are updated to call
nir_lower_reg_intrinsics_to_ssa instead of nir_lower_regs_to_ssa to compensate.
Jointly authored with Faith.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Faith Ekstrand [Wed, 31 May 2023 18:26:53 +0000 (13:26 -0500)]
nir: Add a reg_intrinsics flag to nir_convert_from_ssa
It doesn't do anything yet. We leave that to the subsequent patches so we can
keep the tree-wide refactor as simple as possible.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Mon, 22 May 2023 18:44:52 +0000 (14:44 -0400)]
nir: Add new version of lower_regs_to_ssa
in the sense of operating on register intrinsics instead of nir_registers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Tue, 16 May 2023 21:07:20 +0000 (17:07 -0400)]
nir: Add legacy data structures & helpers
These are registerful versions of core nir_src/nir_dest which will become
SSA-only soon enough, and modifierful versions of nir_alu_src/nir_alu_dest.
The latter will let us remove modifiers from nir_alu_instr finally.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Thu, 18 May 2023 15:00:50 +0000 (11:00 -0400)]
nir: Add pass for trivializing register access
After running the pass, all register access intrinsics are guaranteed to be
"trivial" in the sense that the program is free of hazards preventing
propagating them away without inserting any copies.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Mon, 22 May 2023 18:39:52 +0000 (14:39 -0400)]
nir: Add helpers for walking register uses
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Alyssa Rosenzweig [Tue, 16 May 2023 15:19:49 +0000 (11:19 -0400)]
nir: Add intrinsics for register access
Note the writemask handling is chosen for consistency with the rest of NIR. In
every other instance, writemask=w requires a vec4 source. This is hardcoded into
nir_validate and nir_print as what it means to have a writemask.
More importantly, consistency with how register writemasks currently work.
nir_print hides it, but r0.w = fneg ssa_1.x is actually a vec4 instruction with
source ssa_1.xxxx. As a silly example nir_dest_num_components(that) = 4 in the
old model. I realize this is quite strange coming from a scalar ISA, but it's
perfectly natural for the class of vec4 hardware for which this was designed. In
that hardware, conceptually all instructions are vec4`, so the sequence "fneg
ssa_1 and write to channel w" is implemented as "fneg a vec4 with ssa_1.x in the
last component and write that vec4 out but mask to write only the w channel".
Isn't this inefficient? It can be. To save power, Midgard has scalar ALUs in
addition to vec4 ALUs. Those details are confined to the backend VLIW scheduler;
the instruction selection is still done as vec4. This mechanism has little in
common with AMD's SALUs. Midgard has a wave size of 1, with special hacks for
derivatives.
As a result, all backends consuming register writemasks are expecting this
pattern of code. Changing the store to take a vec1 instead of a vec4 would
require changing every backend to reswizzle the sources to resurrect the vec4. I
started typing a branch to do this yesterday, but it made a mess of both Midgard
and nir-to-tgsi. Without any good reason to think it'd actually help
performance, I abandoned the idea. Getting all 15 backends converted to the
helpers is enough of a challenge without forcing 10 backends to reswizzle their
sources too.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
Eric Engestrom [Tue, 11 Jul 2023 15:18:21 +0000 (16:18 +0100)]
ci: split farm rules out of test-source-dep.yml
That file has become a bit of the new `.gitlab-ci.yml` with just about
everything in there, but a lot of its content doesn't need to be in the
same file anymore now that `!reference` exists.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24090>
Dave Airlie [Tue, 11 Jul 2023 05:09:09 +0000 (15:09 +1000)]
llvmpipe/linear: don't allow linear path for shader output with location frac
This has been broken for a while, but we weren't hitting the linear paths in CI
This fixes:
tests/spec/arb_enhanced_layouts/execution/component-layout/fs-output.shader_test.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24083>
Eric Engestrom [Tue, 11 Jul 2023 18:44:39 +0000 (19:44 +0100)]
ci: fix .valve-farm-manual-rules
28667995e4c3437868ee ("ci: create manual farm rules") was clearly written before
9a8a7aaf1d17c4586ca7 ("ci: split valve farm in two") and landed after but missed
this change when rebasing.
Fixes:
28667995e4c3437868ee ("ci: create manual farm rules")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24097>
Konstantin Seurer [Tue, 11 Jul 2023 14:47:34 +0000 (16:47 +0200)]
nir/opt_dead_cf: Clarify comment
Make it obvious that the comment is about the block stitching behavior
of nir_cf_node_remove.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22064>
Konstantin Seurer [Mon, 10 Jul 2023 19:40:44 +0000 (21:40 +0200)]
nir/opt_dead_cf: Run dead_cf_block while it makes progress
Previously, nir_opt_dead_cf could skip dead CF nodes because overwriting
cur after dead_cf_block is not enough to cover the whole CF list.
foreach_list_typed would select the next node, skipping the node that
previously made progress:
block 1
if (true) {}
block 2
if (true) {}
block 3
if (true) {}
Would turn into:
block 1, then, block 2
if (true) { }
block 3, then
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22064>
Konstantin Seurer [Thu, 18 May 2023 09:38:43 +0000 (11:38 +0200)]
nir/lower_shader_calls: Remat derefs after shader calls
This avoids spilling deref instructions by wrapping shader calls inside
dummy blocks, rematerializing derefs in their use blocks and removing
the dummy blocks.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22064>
Rob Clark [Fri, 30 Jun 2023 18:53:16 +0000 (11:53 -0700)]
freedreno/drm/virtio: Trigger host side wait boost
Let the host know that we'll be waiting for a fence via an asynchronous
WAIT_FENCE command.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23955>
Lionel Landwerlin [Tue, 11 Jul 2023 09:36:15 +0000 (12:36 +0300)]
anv: fix utrace signaling with Xe
utrace submits can either have a batch or not.
When there is a batch, the utrace vk_sync is signaled by the utrace
batch (because utrace does a timestamp buffer copy using its own
batch). When there is no batch, the utrace vk_sync should be signaled
by the application batch (no timestamp copy required, utrace can read
the timestamps when the application batch has completed).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
fdea48df5e ("anv: Implement Xe version of anv_queue_exec_locked() and queue_exec_trace()")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24085>
Lucas Fryzek [Fri, 7 Jul 2023 19:15:20 +0000 (15:15 -0400)]
gallium: Remove `PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND`
Since the mesa state tracker can promote RGB texture formats
to RGBA texture formats (among other formats) without exposing
any of that information to a driver, it is more desirable to
have the behaviour of `PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND`
be the default. This avoids rendering bugs where an application
sets `DST_ALPHA` blending on a format where there is no alpha
channel, that has been promoted to a format that actually has an
alpha channel. The driver can instead rely on the common code
in the state tracker to convert the blending parameter to one
that reflects the limitations of the application requested format,
as long as `PIPE_CAP_INDEP_BLEND_FUNC` is supported.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24044>
Danylo Piliaiev [Tue, 11 Jul 2023 10:13:08 +0000 (12:13 +0200)]
tu: Fix zombie VMAs array not initialized when first BOs may be freed
First BOs were allocated before zombie_vmas was initialized so on
failure their clean up paths used uninitialized zombie_vmas.
Fixes
dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic
dEQP-VK.api.object_management.alloc_callback_fail.device_group
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/9247
Fixes:
63904240f21b192a5fb1e79046a2c351fbd98ace
("tu: Re-enable bufferDeviceAddressCaptureReplay")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24086>
Eric Engestrom [Mon, 3 Jul 2023 16:30:38 +0000 (17:30 +0100)]
ci: set priority:low tag only on non-Marge pipelines
This allows dynamically setting the priority to avoid starving Marge.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23976>
Eric Engestrom [Mon, 3 Jul 2023 16:37:46 +0000 (17:37 +0100)]
ci: document workflow rules
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23976>
Marek Olšák [Tue, 11 Jul 2023 09:04:09 +0000 (05:04 -0400)]
radeonsi/gfx11: fix a regression with PAIRS packets due to shader changes
When the vertex shader switches from hw GS to hw HS and vice versa, we need
to re-emit all draw user SGPRs.
Fixes:
1753b321f876 - radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for gfx by buffering reg writes
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24087>
Daniel Schürmann [Thu, 22 Jun 2023 11:42:37 +0000 (13:42 +0200)]
amd: Do shader binary alignment for prefetch at memory allocation time.
This makes it consistent between drivers and compilers.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23799>
Daniel Schürmann [Thu, 22 Jun 2023 11:24:16 +0000 (13:24 +0200)]
amd: move end-of-code marker padding to ACO.
This makes it consistent between drivers and compilers.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23799>
Marek Olšák [Tue, 11 Jul 2023 03:19:39 +0000 (23:19 -0400)]
radeonsi: fix gfx9 regression causing GPU hangs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes:
283be8ac3b8610a77b2 - radeonsi: handle GE_CNTL and IA_MULTI_VGT_PARAM as a tracked register
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2651
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9249
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24082>
Christian Gmeiner [Thu, 6 Jul 2023 06:24:03 +0000 (08:24 +0200)]
etnaviv: linker: clean up etna_link_shader(..)
There is no case that etna_link_shader(..) can fail now.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24030>
Christian Gmeiner [Thu, 6 Jul 2023 06:08:16 +0000 (08:08 +0200)]
etnaviv: linker: handle scenario where there are FS inputs without matching VS output
If there is a FS input but no VS output the behavior is undefined
but okay. Use a register 0 (position) for such cases.
glsl-routing test triggers it with e.g. the following subtest.
Test: VS(C0 -- T0 -- T2 -- T4 T5)
FS(C0 C1 T0 T1 T2 T3 T4 T5)
This will now end with following linker debug output:
link result:
vs -> fs comps use pa_attr
t1 -> t1 xyzw 0,0,0,0 0x000002f1
t2 -> t2 xyzw 0,0,0,0 0x000002f1
t0 -> t3 xyzw 0,0,0,0 0x000002f1
t3 -> t4 xyzw 0,0,0,0 0x000002f1
t0 -> t5 xyzw 0,0,0,0 0x000002f1
t4 -> t6 xyzw 0,0,0,0 0x000002f1
t5 -> t7 xyzw 0,0,0,0 0x000002f1
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24030>
David Heidelberg [Tue, 11 Jul 2023 00:17:01 +0000 (02:17 +0200)]
ci/freedreno: another batch of a530 flakes
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24081>
Karmjit Mahil [Fri, 23 Jun 2023 09:38:16 +0000 (10:38 +0100)]
docs: Add inital PowerVR driver documentation
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8048
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23992>
Daniel Schürmann [Wed, 28 Jun 2023 16:35:08 +0000 (18:35 +0200)]
radv: migrate radv_shader hash to BLAKE3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23974>
Daniel Schürmann [Wed, 28 Jun 2023 10:15:51 +0000 (12:15 +0200)]
radv/meta: disable disk cache for meta shaders
Meta shaders are already stored in a separate cache file,
inserting them into the disk cache is unnecessary.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23909>
Daniel Schürmann [Tue, 27 Jun 2023 15:47:18 +0000 (17:47 +0200)]
vulkan/pipeline_cache: add 'skip_disk_cache' option
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23909>
Daniel Schürmann [Wed, 21 Jun 2023 12:08:06 +0000 (14:08 +0200)]
aco/assembler: change prefetch mode on GFX10.3+ during loops if beneficial
Totals from 8864 (6.68% of 132726) affected shaders: GFX11
CodeSize:
90776128 ->
90923760 (+0.16%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23748>
Daniel Schürmann [Tue, 20 Jun 2023 17:03:35 +0000 (19:03 +0200)]
aco/assembler: align loops if it reduces the number of cache lines
This is especially beneficial on GFX6-9.
Totals from 11229 (8.46% of 132726) affected shaders: GFX11
CodeSize:
109608640 ->
109840916 (+0.21%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23748>
Daniel Schürmann [Tue, 20 Jun 2023 13:36:38 +0000 (15:36 +0200)]
aco/assembler: align resume shaders with cache lines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23748>
Julia Tatz [Sat, 8 Jul 2023 19:37:40 +0000 (15:37 -0400)]
aux/trace: fix (u)int dump
The PRI* macros don't include the required introductory % character
Fixes:
d29bb6467e2 ("aux/trace: use stdint.h types")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24057>
Lionel Landwerlin [Mon, 10 Jul 2023 22:06:04 +0000 (01:06 +0300)]
zink: drop linear D32_SFLOAT_S8_UINT requirement
Very likely a typo. Afaict radv/anv don't support this.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24078>
Feng Jiang [Mon, 22 May 2023 06:27:25 +0000 (14:27 +0800)]
virgl/video: Fix out-of-bounds access in fill_mpeg4_picture_desc()
An out-of-bounds access has occurred to array ref[2] and it needs
to be fixed.
Fixes:
6b5aecb19558 ("virgl: add support for hardware video acceleration")
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23160>
Mike Blumenkrantz [Thu, 6 Jul 2023 12:57:29 +0000 (08:57 -0400)]
zink: fix batch disambiguation on first submit
submit_count is used to disambiguate a batch_id based on the generation
id of a given batch: this value is incremented once on submit and once on
reset such that the diff of the values is > 1 any time the batch does not
represent the fence it was last submitted with
in the case of a batch's first use, however, this value was being incorrectly
incremented such that the first submit would cause disambiguation checks
to erroneously determine that the batch had already completed, breaking synchronization
fixes #9313
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24016>
Lionel Landwerlin [Mon, 10 Jul 2023 14:00:28 +0000 (17:00 +0300)]
zink: update profile vulkan version requirements
Pretty much all the profiles references Vulkan 1.2 or 1.3 only
structures but only say they need a 1.0.X version.
This fails parsing of the Vulkan Profile scripts for generating
implementation checks against a particular profile.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24072>
Feng Jiang [Wed, 24 May 2023 07:47:00 +0000 (15:47 +0800)]
radeonsi/vcn: Remove unnecessary type conversion
The types of both 'encrypted' and 'picture->protected_playback'
are bool, so there is no need. I guess this is a typo.
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23202>
Feng Jiang [Wed, 24 May 2023 07:33:07 +0000 (15:33 +0800)]
frontends/va: Fix memory leak of decrypt_key
pipe_picture_desc.decrypt_key was alloced in function
handleVAProtectedSliceDataBufferType(), but nowhere to
free it. Now, it will be freed as the vlVaContext is
destroyed.
Fixes:
deb7dc82f62 ("frontends/va: handle protected slice data buffer")
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23202>
Dave Airlie [Wed, 14 Jun 2023 20:05:44 +0000 (06:05 +1000)]
gallium/va: fix superres av1 decoding.
On a superres sample, vulkan was decoding fine, but vaapi failed,
fix the micols calculations.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23715>
Eric Engestrom [Mon, 10 Jul 2023 10:20:16 +0000 (11:20 +0100)]
ci/zink+radv: fix flake definition
Fixes:
741bfb52e674950e7731 ("zink/ci: add more tests to the flake list of vangogh")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24068>
David Heidelberg [Sat, 8 Jul 2023 11:14:58 +0000 (13:14 +0200)]
ci/traces: switch from xvfb to Weston XWayland
- Drop now unused RUN_CMD_WRAPPER.
- Copy-paste Weston initiation code from init-stage2.sh with slightly adjustments.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24056>
David Heidelberg [Sat, 8 Jul 2023 16:00:15 +0000 (18:00 +0200)]
ci/container: we need to keep the wine inside
Needed for testing with wine apitrace.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24056>
David Heidelberg [Sat, 8 Jul 2023 11:34:51 +0000 (13:34 +0200)]
ci/container: add weston into Vulkan container
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24056>
Yonggang Luo [Tue, 4 Jul 2023 09:48:40 +0000 (17:48 +0800)]
nir: Remove nir_builder_init, it's not used anymore
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24038>
Yonggang Luo [Fri, 7 Jul 2023 12:46:14 +0000 (20:46 +0800)]
treewide: remove unused nir_builder
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24038>
Yonggang Luo [Tue, 4 Jul 2023 09:26:56 +0000 (17:26 +0800)]
treewide: Remove all usage of nir_builder_init with nir_builder_create and nir_builder_at
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24038>
Christian Gmeiner [Tue, 4 Jul 2023 07:19:05 +0000 (09:19 +0200)]
docs: update etnaviv extensions
I went through the list and updated the extensions that are supported
and passing (most) of the piglit's and deqp's.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24032>
Friedrich Vock [Sun, 9 Jul 2023 19:12:00 +0000 (21:12 +0200)]
radv/rt: Miss rays that hit the triangle's v edge
The hardware seems to do this as well. Avoids invoking hit shaders twice
at shared edges.
Fixes the fails in watertightness tests on emulated RT.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24063>
Friedrich Vock [Sun, 9 Jul 2023 19:09:11 +0000 (21:09 +0200)]
radv/rt: Enable exact on software intersection functions
These functions need exact output, otherwise watertightness can't be
guaranteed in some cases.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24063>
Sagar Ghuge [Thu, 6 Jul 2023 16:34:44 +0000 (09:34 -0700)]
iris: Drop depth cache flush requirement after depth clear/resolve
From Bspec 46959, a programming note applicable to Gfx12+:
"Since HZ_OP has to be sent twice (first time set the clear/resolve
state and 2nd time to clear the state), and HW internally flushes the
depth cache on HZ_OP, there is no need to explicitly send a Depth
Cache flush after Clear or Resolve."
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24027>
Sagar Ghuge [Thu, 6 Jul 2023 16:29:31 +0000 (09:29 -0700)]
anv: Drop depth cache flush requirement after depth clear/resolve
From Bspec 46959, a programming note applicable to Gfx12+:
"Since HZ_OP has to be sent twice (first time set the clear/resolve
state and 2nd time to clear the state), and HW internally flushes the
depth cache on HZ_OP, there is no need to explicitly send a Depth
Cache flush after Clear or Resolve."
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24027>
Italo Nicola [Mon, 10 Jul 2023 15:00:56 +0000 (15:00 +0000)]
freedreno/ci: add KHR-GL46.buffer_storage.map_persistent_flush to flakes
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Suggested-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>
Italo Nicola [Thu, 9 Feb 2023 13:14:29 +0000 (13:14 +0000)]
mesa/main: add PIPE_FORMAT_VYUY and PIPE_FORMAT_B8R8_G8R8
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>
Italo Nicola [Thu, 9 Feb 2023 11:32:12 +0000 (11:32 +0000)]
mesa/main: add PIPE_FORMAT_YVYU and PIPE_FORMAT_R8B8_R8G8
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>
Italo Nicola [Wed, 1 Feb 2023 21:59:38 +0000 (21:59 +0000)]
gallium/st: add support for PIPE_FORMAT_NV21 and PIPE_FORMAT_G8_B8R8_420
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>
Italo Nicola [Thu, 9 Feb 2023 12:39:33 +0000 (12:39 +0000)]
nir: add options to lower y_vu, yv_yu, yx_xvxu and xy_vxux
`y_vu` will be used to convert NV21 to RGB.
`yv_yu` will be used to convert YVYU and VYUY to RGB when the
subsampling formats PIPE_FORMAT_R8B8_R8G8 and PIPE_FORMAT_B8R8_G8R8
are supported.
`yx_xvxu` and `xy_vxux` will be used to convert YVYU and VYUY to RGB
when those subsampling formats are not supported.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>
David Heidelberg [Mon, 10 Jul 2023 11:28:48 +0000 (13:28 +0200)]
ci/freedreno: add execution@varying-struct-copy-return-vs flake
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24069>
David Heidelberg [Mon, 10 Jul 2023 11:27:27 +0000 (13:27 +0200)]
ci/freedreno: add KHR-GL46.buffer_storage flakes
Both flakes occuring time to time on Adreno 6xx series.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24069>
Italo Nicola [Mon, 10 Jul 2023 12:56:37 +0000 (12:56 +0000)]
d3d12/ci: add piglit arb_clear_texture-integer fail to CI expectations
Likely related to other ARB_texture_integer fails, instead of something
specific to ARB_clear_texture.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Fri, 7 Jul 2023 15:44:28 +0000 (15:44 +0000)]
lima/ci: add some ARB_clear_texture piglit tests to lima-fails.txt
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Tue, 20 Jun 2023 20:24:01 +0000 (20:24 +0000)]
gallium: remove PIPE_CAP_CLEAR_TEXTURE
ARB_clear_texture is now implemented in common code.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Thu, 22 Jun 2023 17:41:16 +0000 (17:41 +0000)]
gallium: cleanup util_blitter_clear_render_target
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Sun, 9 Jul 2023 22:45:47 +0000 (19:45 -0300)]
clover: use fallback path when pipe->clear_texture is not available
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Wed, 21 Jun 2023 14:46:02 +0000 (14:46 +0000)]
rusticl: use fallback path when pipe->clear_texture is not available
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Thu, 22 Jun 2023 18:45:18 +0000 (18:45 +0000)]
mesa/st: use fallback path when pipe->clear_texture is not available
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Thu, 22 Jun 2023 18:32:45 +0000 (18:32 +0000)]
gallium: rename util_clear_texture to util_clear_texture_sw
This better explain what this function does, making it less likely that
people mistakenly use it instead of util_default_clear_texture.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Thu, 22 Jun 2023 18:35:06 +0000 (18:35 +0000)]
gallium: use u_default_clear_texture where applicable
This removes some shared code between backends that implemented their
version of pipe->clear_texture without anything driver-specific code.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Mon, 19 Jun 2023 22:04:15 +0000 (22:04 +0000)]
gallium: implement u_default_clear_texture
util_clear_texture implements clear_texture through a memset.
This patch implements u_default_clear_texture, which tries to clear the
given texture using a surface plus clear_render_target or
clear_depth_stencil.
In case this path fails, either because the formats are non-renderable
or for some other reason, we fallback to `util_clear_texture`, which is
guaranteed to work.
This will allow us to make ARB_clear_texture available to every driver,
as well as provide HW acceleration for the clear_texture operation.
If some hardware doesn't want to use it, such as llvmpipe, it can always
just directly point to the software version using pipe->clear_texture.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Sun, 9 Jul 2023 22:47:43 +0000 (19:47 -0300)]
d3d12: fix clear_depth_stencil texture deref
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Wed, 28 Jun 2023 14:23:39 +0000 (14:23 +0000)]
vc4: implement clear_render_target and clear_depth_stencil
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
Italo Nicola [Wed, 28 Jun 2023 14:23:27 +0000 (14:23 +0000)]
v3d: implement clear_render_target and clear_depth_stencil
Also added some related piglit failures to broadcom-rpi4-fails.txt.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>
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