Nishanth Menon [Tue, 30 May 2023 16:58:55 +0000 (11:58 -0500)]
arm64: dts: ti: k3-am62a-main: Add sa3_secproxy
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. This is in addition to the one in the main domain DMSS
subsystem that is used for general purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nitin Yadav [Tue, 30 May 2023 16:58:54 +0000 (11:58 -0500)]
arm64: dts: ti: k3-am62-main: Add sa3_secproxy
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. This is in addition to the one in the main domain DMSS
subsystem that is used for general purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
[nm@ti.com: Update commit message, minor updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 7 Jun 2023 13:20:43 +0000 (08:20 -0500)]
arm64: dts: ti: k3-am65-iot2050-common: Rename rtc8564 nodename
Just use "rtc" as the nodename to better match with the bindings.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 7 Jun 2023 13:20:42 +0000 (08:20 -0500)]
arm64: dts: ti: k3-am65-main: Drop deprecated ti,otap-del-sel property
ti,otap-del-sel has been deprecated in favor of ti,otap-del-sel-legacy.
Drop the duplicate and misleading ti,otap-del-sel property.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 7 Jun 2023 13:20:41 +0000 (08:20 -0500)]
arm64: dts: ti: k3-am65-main: Fix mcan node name
s/mcan/can to stay in sync with bindings conventions.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:11 +0000 (19:47 +0530)]
arm64: dts: ti: k3-am642-sk/evm: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. AM64 SK and EVM has a S28 64 MiB OSPI
flash with sector size of 256 KiB thus the size of the smallest partition
is chosen as 256 KiB, the partition names and offsets are chosen according
to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-6-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:10 +0000 (19:47 +0530)]
arm64: dts: ti: k3-am654-baseboard: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. AM654 baseboard has a MT35XU512ABA
64 MiB OSPI flash with sector size of 128 KiB thus the size of the
smallest partition is chosen as 128 KiB, the partition names and
offsets are chosen according to the corresponding name and offsets
in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-5-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:09 +0000 (19:47 +0530)]
arm64: dts: ti: k3-j7200-som: Describe OSPI and Hyperflash partition info
Describe OSPI and Hyperflash partition information through device tree,
this helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition information
in a string format. J7200 SoM has a S28 64 MiB OSPI flash with sector size
of 256 KiB thus the size of the smallest partition is chosen as 256 KiB,
the SoM also has a 64 MiB Hyperflash present on it, the partition names
and offsets are chosen according to the corresponding name and offsets
in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-4-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:08 +0000 (19:47 +0530)]
arm64: dts: ti: k3-j721e-sk: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. J721E SK has a S28 64 MiB OSPI flash
with sector size of 256 KiB thus the size of the smallest partition is
chosen as 256 KiB, the partition names and offsets are chosen according
to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-3-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:07 +0000 (19:47 +0530)]
arm64: dts: ti: k3-j721e: Describe OSPI and QSPI flash partition info
Describe OSPI and QSPI flash partition information through device tree,
this helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition information
in a string format. J721E SoM has a MT35 64 MiB OSPI flash and MT25 64 MiB
QSPI flash both with sector size of 128 KiB thus the size of the smallest
partition is chosen as 128KiB, the partition names and offsets are chosen
according to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-2-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Apurva Nandan [Thu, 4 May 2023 08:03:05 +0000 (13:33 +0530)]
arm64: dts: ti: k3-j784s4-evm: Add support for OSPI and QSPI flashes
J784S4 has S28HS512T OSPI flash connected to OSPI0 and MT25QU512A QSPI
flash connected to OSPI1, enable support for the same. Also describe
the partition information according to the offsets in the bootloader.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20230504080305.38986-3-a-nandan@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Apurva Nandan [Thu, 4 May 2023 08:03:04 +0000 (13:33 +0530)]
arm64: dts: ti: k3-j784s4-mcu-wakeup: Add FSS OSPI0 and FSS OSPI1
TI K3 J784S4 has the Cadence OSPI controllers OSPI0 and OSPI1 on FSS
bus for interfacing with OSPI flashes. Add the nodes to allow using
SPI flashes.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20230504080305.38986-2-a-nandan@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Wadim Egorov [Fri, 5 May 2023 13:10:12 +0000 (15:10 +0200)]
arm64: dts: ti: Add LED controller to phyBOARD-Electra
With commit
9f6ffd0da650 ("dt-bindings: leds: Convert PCA9532 to dtschema"),
we can now add the LED controller without introducing new dtbs_check warnings.
Add missing I2C LED controller.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20230505131012.2027309-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 12:33:13 +0000 (18:03 +0530)]
arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select pinmux
J721E common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_8 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-5-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 12:33:12 +0000 (18:03 +0530)]
arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux
J7200 common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-4-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 12:33:11 +0000 (18:03 +0530)]
arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node
J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory
controller, add corresponding node, pinmux and partitions for the same.
HyperBus is muxed with OSPI and only one controller can be active at a
time, therefore keep HyperBus node disabled. Bootloader will detect the
external mux state through a wkup gpio and enable the node as required.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-3-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 12:33:10 +0000 (18:03 +0530)]
arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node
J721E has a Flash SubSystem that has one OSPI and one HyperBus with
muxed datapath and another independent OSPI. Add DT nodes for HyperBus
controller and keep it disabled and model the data path selection mux as a
reg-mux.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-2-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:37 +0000 (12:21 -0500)]
arm64: dts: ti: k3-j721e: Enable MDIO nodes at the board level
MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmux.
As the attached PHY is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the MDIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-5-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:36 +0000 (12:21 -0500)]
arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete
and may not be functional unless they are extended with a chosen interrupt
and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at
the board integration level, these nodes should only be enabled when
provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that
are actually used on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-4-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:35 +0000 (12:21 -0500)]
arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level
PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.
As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-3-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:34 +0000 (12:21 -0500)]
arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
These nodes are example nodes for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.
Examples should go in the bindings or other documentation.
Remove this node.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-2-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:33 +0000 (12:21 -0500)]
arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status
Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT
addition went in at around the same time and must have missed that
change so the mailboxes are not re-enabled. Do that here.
Fixes:
fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64")
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-1-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bhavya Kapoor [Tue, 2 May 2023 09:08:14 +0000 (14:38 +0530)]
arm64: dts: ti: k3-j784s4-main: Enable support for high speed modes
eMMC tuning was incomplete earlier, so support for high speed modes was
kept disabled. Remove no-1-8-v property to enable support for high
speed modes for eMMC in J784S4 SoC.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230502090814.144791-1-b-kapoor@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bhavya Kapoor [Tue, 2 May 2023 08:11:17 +0000 (13:41 +0530)]
arm64: dts: ti: k3-j784s4-evm: Add pinmux information for ADC
J784S4 has two instances of 8 channel ADCs in MCU domain. Add pinmux
information for both ADC nodes.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230502081117.21431-3-b-kapoor@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bhavya Kapoor [Tue, 2 May 2023 08:11:16 +0000 (13:41 +0530)]
arm64: dts: ti: k3-j784s4-mcu-wakeup: Add support for ADC nodes
J784S4 has two instances of 8 channel ADCs in MCU domain. Add support
for both ADC nodes.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230502081117.21431-2-b-kapoor@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Jyri Sarha [Tue, 9 May 2023 10:23:53 +0000 (15:53 +0530)]
arm64: dts: ti: am65x: Add Rocktech OLDI panel DT overlay
The OLDI-LCD1EVM add on board has Rocktech RK101II01D-CT panel[1] with
integrated touch screen. The integrated touch screen is Goodix GT928.
This panel connects with AM65 GP-EVM[2].
Add DT nodes for these and connect the endpoint nodes with DSS.
[1]: Panel link
https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT
[2]: AM654 LCD EVM:
https://www.ti.com/tool/TMDSLCD1EVM
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
[abhatia1@ti.com: Make cosmetic and 6.4 kernel DTSO syntax changes]
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230509102354.10116-2-a-bhatia1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bhavya Kapoor [Mon, 24 Apr 2023 09:38:27 +0000 (15:08 +0530)]
arm64: dts: ti: k3-j721e-main: Update delay select values for MMC subsystems
Update the delay values for various speed modes supported, based on
the revised august 2021 J721E Datasheet.
[1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and
Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in
https://www.ti.com/lit/ds/symlink/tda4vm.pdf,
(SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021)
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230424093827.1378602-1-b-kapoor@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 18 Apr 2023 21:37:40 +0000 (16:37 -0500)]
arm64: dts: ti: k3-am62x-sk-common: Improve documentation of mcasp1_pins
Include documentation of the AMC package pin name as well to keep it
consistent with the rest of the pinctrl documentation.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230418213740.153519-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 18 Apr 2023 21:37:39 +0000 (16:37 -0500)]
arm64: dts: ti: k3-am62x-sk-common: Add eeprom
Add board EEPROM support to device tree
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230418213740.153519-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 18 Apr 2023 21:37:38 +0000 (16:37 -0500)]
arm64: dts: ti: k3-am62x-sk-common: Describe main_uart1 and wkup_uart
wkup_uart and main_uart1 on this platform is used by tifs and DM
firmwares. Describe them for completeness including the pinmux.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230418213740.153519-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 18 Apr 2023 21:37:37 +0000 (16:37 -0500)]
arm64: dts: ti: k3-am62x-sk-common: Drop extra EoL
Drop an extra EoL
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230418213740.153519-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Mon, 17 Apr 2023 22:54:50 +0000 (17:54 -0500)]
arm64: dts: ti: k3: j721s2/j784s4: Switch to https links
Looks like a couple of http:// links crept in. Use https instead.
While at it, drop unicode encoded character.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230417225450.1182047-1-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Keerthy [Wed, 5 Apr 2023 21:53:28 +0000 (16:53 -0500)]
arm64: dts: ti: j721s2: Add VTM node
VTM stands for Voltage Thermal Management. Add the thermal zones.
Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3,
WKUP1 & WKUP2 domains respectively.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[bb@ti.com: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230405215328.3755561-8-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Keerthy [Wed, 5 Apr 2023 21:53:27 +0000 (16:53 -0500)]
arm64: dts: ti: j7200: Add VTM node
VTM stands for Voltage Thermal Management. Add the thermal zones.
Three sensors mapping to 3 thermal zones. MCU, MPU & Main domains
respectively.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[bb@ti.com: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230405215328.3755561-7-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Keerthy [Wed, 5 Apr 2023 21:53:26 +0000 (16:53 -0500)]
arm64: dts: ti: j721e: Add VTM node
VTM stands for Voltage Thermal Management. Add the thermal zones.
Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F
respectively.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[bb@ti.com: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230405215328.3755561-6-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Keerthy [Wed, 5 Apr 2023 21:53:25 +0000 (16:53 -0500)]
arm64: dts: ti: j784s4: Add VTM node
VTM stands for Voltage Thermal Management. Add the thermal zones.
Seven sensors mapping to seven thermal zones. Main0, Main1, Main2, Main3,
Main4, WKUP1 & WKUP2 domains respectively.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[bb@ti.com: rebased on v6.3-rc1]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230405215328.3755561-5-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bryan Brattlof [Wed, 5 Apr 2023 21:53:24 +0000 (16:53 -0500)]
arm64: dts: ti: k3-am62a-wakeup: add VTM node
The am62ax supports a single Voltage and Thermal Management (VTM) device
located in the wakeup domain with three associated temperature monitors
located in various hot spots of the die.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230405215328.3755561-4-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bryan Brattlof [Wed, 5 Apr 2023 21:53:23 +0000 (16:53 -0500)]
arm64: dts: ti: k3-am62-wakeup: add VTM node
The am62x supports a single Voltage and Thermal Management (VTM) module
located in the wakeup domain with two associated temperature monitors
located in hot spots of the die.
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230405215328.3755561-3-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bryan Brattlof [Wed, 5 Apr 2023 21:53:22 +0000 (16:53 -0500)]
arm64: dts: ti: k3-am64-main: add VTM node
The am64x supports a single VTM module which is located in the main
domain with two associated temperature monitors located at different hot
spots on the die.
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230405215328.3755561-2-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Aswath Govindraju [Fri, 31 Mar 2023 09:00:28 +0000 (14:30 +0530)]
arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-9-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Aswath Govindraju [Fri, 31 Mar 2023 09:00:27 +0000 (14:30 +0530)]
arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
Add PCIe1 RC device tree node for the single PCIe instance present on
the J721S2.
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-8-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Aswath Govindraju [Fri, 31 Mar 2023 09:00:26 +0000 (14:30 +0530)]
arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a
QSPI NOR flash on the common processor board connected to the OSPI1
instance. Add support for the same
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-7-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Aswath Govindraju [Fri, 31 Mar 2023 09:00:25 +0000 (14:30 +0530)]
arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that up to 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-6-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Aswath Govindraju [Fri, 31 Mar 2023 09:00:24 +0000 (14:30 +0530)]
arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-5-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Aswath Govindraju [Fri, 31 Mar 2023 09:00:23 +0000 (14:30 +0530)]
arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
Add support for two instance of OSPI in J721S2 SoC.
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-4-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Matt Ranostay [Fri, 31 Mar 2023 09:00:22 +0000 (14:30 +0530)]
arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-3-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Aswath Govindraju [Fri, 31 Mar 2023 09:00:21 +0000 (14:30 +0530)]
arm64: dts: ti: k3-j721s2-main: Add support for USB
Add support for single instance of USB 3.0 controller in J721S2 SoC.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331090028.8373-2-r-gunasekaran@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Roger Quadros [Thu, 30 Mar 2023 08:49:53 +0000 (11:49 +0300)]
arm64: dts: ti: k3-am625: Enable Type-C port for USB0
USB0 is a Type-C port with dual data role and power sink.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230330084954.49763-3-rogerq@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Hari Nagalla [Tue, 2 May 2023 23:15:27 +0000 (18:15 -0500)]
arm64: dts: ti: k3-j784s4-evm: Reserve memory for remote proc IPC
Reserve memory for remote processors. Two memory regions are reserved
for each remote processor. The first 1Mb region is used for virtio
Vring buffers for IPC and the second region is used for holding
resource table, trace buffer and as external memory to the remote
processor. The mailboxes are also assigned for each remote processor.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Link: https://lore.kernel.org/r/20230502231527.25879-4-hnagalla@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Hari Nagalla [Tue, 2 May 2023 23:15:26 +0000 (18:15 -0500)]
arm64: dts: ti: k3-j784s4-main: Add C71x DSP nodes
The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage
domain. The functionality of these DSP subsystems is similar to the C71x
DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of
L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem
has a CMMU but is not currently used. The inter-processor communication
between the main A72 cores and the C71x DSPs is achieved through shared
memory and mailboxes. Add the DT nodes for these DSP processor sub-systems.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Link: https://lore.kernel.org/r/20230502231527.25879-3-hnagalla@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Hari Nagalla [Tue, 2 May 2023 23:15:25 +0000 (18:15 -0500)]
arm64: dts: ti: k3-j784s4-main: Add R5F cluster nodes
The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining three clusters are present in the
MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). The functionality
of the R5FSS is same as the R5FSS functionality on earlier K3 platform
device J721S2. Each of the R5FSS can be configured at boot time to be
either run in a LockStep mode or in an Asymmetric Multi Processing (AMP)
fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled
Memory (TCM) internal memories for each core split between two banks -
ATCM and BTCM (further interleaved into two banks). There are some IP
integration differences from standard Arm R5 clusters such as the absence
of an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT nodes for the R5F cluster/subsystems, the two R5F cores are
each added as child nodes to the corresponding cluster node. The clusters
are configured to run in LockStep mode by default, with the ATCMs enabled
to allow the R5 cores to execute code from DDR with boot-strapping code
from ATCM. The inter-processor communication between the main A72 cores
and these processors is achieved through shared memory and Mailboxes.
The following firmware names are used by default for these cores, and
can be overridden in a board dts file if needed:
MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes)
MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode)
MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes)
MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode)
MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes)
MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode)
MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (needed only in Split mode)
MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode)
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Link: https://lore.kernel.org/r/20230502231527.25879-2-hnagalla@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Udit Kumar [Wed, 19 Apr 2023 04:00:07 +0000 (09:30 +0530)]
arm64: dts: ti: k3-j7200-som: Enable I2C
This patch enables wkup_i2c0 node in board dts file
along with pin mux and speed.
Also enables underneath eeprom CAV24C256WE.
J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) :
https://www.ti.com/lit/ds/symlink/dra821u.pdf
J7200 User Guide (Section 4.3, Table 4-2) :
https://www.ti.com/lit/ug/spruiw7a/spruiw7a.pdf
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230419040007.3022780-3-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Keerthy [Wed, 19 Apr 2023 04:00:06 +0000 (09:30 +0530)]
arm64: dts: ti: k3-j7200: Fix physical address of pin
wkup_pmx splits into multiple regions. Like
wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12)
wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15)
wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84)
wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100)
With this split, pin offset needs to be adjusted to
match with new pmx for all pins above wkup_pmx0.
Example a pin under wkup_pmx1 should start from 0 instead of
old offset(0x38 WKUP_PADCONFIG 14 offset)
J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) :
https://www.ti.com/lit/ds/symlink/dra821u.pdf
Fixes:
9ae21ac445e9 ("arm64: dts: ti: k3-j7200: Fix wakeup pinmux range")
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230419040007.3022780-2-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 25 Apr 2023 22:17:08 +0000 (17:17 -0500)]
arm64: dts: ti: k3-am62a7-sk: Describe main_uart1 and wkup_uart
wkup_uart and main_uart1 on this platform is used by tifs and DM
firmwares. Describe them for completeness including the pinmux.
Signed-off-by: Nishanth Menon <nm@ti.com>
[bb@ti.com: updated pinmux and commit subject]
Signed-off-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20230425221708.549675-1-bb@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Mon, 24 Apr 2023 14:49:43 +0000 (09:49 -0500)]
arm64: dts: ti: k3-am65-main: Remove "syscon" nodes added for pcieX_ctrl
Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node
point to the parent with an offset argument. This change is as
discussed in [1].
[1] http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230424144949.244135-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Krzysztof Kozlowski [Fri, 21 Apr 2023 22:31:43 +0000 (00:31 +0200)]
arm64: dts: ti: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
k3-am6528-iot2050-basic-pg2.dtb: l3-cache0: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230421223143.115099-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 22:59:13 +0000 (17:59 -0500)]
arm64: dts: ti: k3-am65: Drop aliases
iot boards have always defined their own aliases and with the base-board
defining it's own aliases, there are no pending boards depending on
common aliases defined in SoC level.
aliases are meant to be defined appropriately based on the exposed
interfaces at a board level, drop the aliases defined at SoC level.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230419225913.663448-8-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 22:59:12 +0000 (17:59 -0500)]
arm64: dts: ti: k3-am654-base-board: Add aliases
Introduce aliases compatible with the base definition, but focussed on
the interfaces that have been exposed on the platform.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230419225913.663448-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 22:59:11 +0000 (17:59 -0500)]
arm64: dts: ti: k3-am654-base-board: Add board detect eeprom
Enable AT24CM01 on the base board using the corresponding compatible.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230419225913.663448-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 22:59:10 +0000 (17:59 -0500)]
arm64: dts: ti: k3-am654-base-board: Add missing PMIC
Add the missing vdd_mpu PMIC.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230419225913.663448-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 22:59:09 +0000 (17:59 -0500)]
arm64: dts: ti: k3-am654-base-board: Add VTT GPIO regulator for DDR
Hold the DDR vtt regulator active for functionality.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230419225913.663448-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 22:59:08 +0000 (17:59 -0500)]
arm64: dts: ti: k3-am654-base-board: Rename regulator node name
Rename the regulator node names to the standard regulator-0.. numbers.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230419225913.663448-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 22:59:07 +0000 (17:59 -0500)]
arm64: dts: ti: k3-am654-base-board: Add missing pinmux wkup_uart, mcu_uart and mcu_i2c
Many of the definitions depend on pinmux done by the bootloader. Be
explicit about the pinmux for functionality and completeness.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Link: https://lore.kernel.org/r/20230419225913.663448-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 18 Apr 2023 01:27:16 +0000 (20:27 -0500)]
arm64: dts: ti: k3-am62a: Add watchdog nodes
Add nodes for watchdogs:
- 5 in main domain
- 1 in MCU domain
- 1 in wakeup domain
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230418012717.1230882-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 18 Apr 2023 01:27:15 +0000 (20:27 -0500)]
arm64: dts: ti: k3-am62a: Add general purpose timers
Similar to commit
3308a31c507c ("arm64: dts: ti: k3-am62: Add general
purpose timers for am62"), there are 12 general purpose timers on am62a7
split between 8 in main and 4 in mcu domains. The 4 in mcu domain do not
have interrupts that are routable to a53.
We configure the timers with the 25 MHz input clock by default as the
32.768 kHz clock may not be wired on the device. We leave the MCU domain
timers clock mux unconfigured, and mark the MCU domain timers reserved.
The MCU domain timers are likely reserved by the software for the ESM
module.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230418012717.1230882-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 14:12:22 +0000 (09:12 -0500)]
arm64: dts: ti: k3-j721s2-common-proc-board: Drop bootargs
Drop bootargs from the dts. The console arguments are already covered in
stdout-path property and earlycon is a debug property that should be
enabled only when debug is desired and not as default.
Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230419141222.383567-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 14:12:21 +0000 (09:12 -0500)]
arm64: dts: ti: k3-j7200-common-proc-board: Drop bootargs
Drop bootargs from the dts. The console arguments are already covered in
stdout-path property and earlycon is a debug property that should be
enabled only when debug is desired and not as default.
Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230419141222.383567-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 14:12:20 +0000 (09:12 -0500)]
arm64: dts: ti: k3-j721e-*: Drop bootargs
Drop bootargs from the dts. The console arguments are already covered in
stdout-path property and earlycon is a debug property that should be
enabled only when debug is desired and not as default.
Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230419141222.383567-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 14:12:19 +0000 (09:12 -0500)]
arm64: dts: ti: k3-am65*: Drop bootargs
Drop bootargs from the dts. earlycon is a debug property that should be
enabled only when debug is desired and not as default - see referenced
link on discussion on this topic.
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/20230419141222.383567-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 19 Apr 2023 14:12:18 +0000 (09:12 -0500)]
arm64: dts: ti: k3-am62x-sk-common: Drop bootargs
Drop bootargs from the dts. The console arguments are already covered in
stdout-path property and earlycon is a debug property that should be
enabled only when debug is desired and not as default.
Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230419141222.383567-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:28 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am642-sk|evm: Drop bootargs, add aliases
Drop bootargs and add aliases based on base pinout of SK as per [1] and
evm per [2].
Indices chosen attempt to maintain some level of consistency with
existing aliases.
While at this, drop a extra EoL. While this patch could be split, it
seems trivial to add additional cleanup steps.
[1] https://www.ti.com/lit/df/sprr432/sprr432.pdf
[2] https://www.ti.com/lit/zip/swrr171
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-11-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:27 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am642-evm: Add VTT GPIO regulator for DDR
Hold the DDR vtt regulator active for functionality.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-10-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:26 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am642-evm: Rename regulator node name
Rename the regulator node names to the standard regulator-0.. numbers.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-9-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:25 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am642-evm: Describe main_uart1 pins
Describe the main_uart1 pins even though it is a reserved node for
hardware complete description. This is used by other users of device
tree to help configure the SoC per board requirements.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-8-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:24 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am642-evm: Enable main_i2c0 and eeprom
Enable AT24CM01 on the base board using the corresponding compatible.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:23 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am642-sk: Rename regulator node name
Rename the regulator node names to the standard regulator-0.. numbers.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:22 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am642-sk: Describe main_uart1 pins
Describe the main_uart1 pins even though it is a reserved node for
hardware complete description. This is used by other users of device
tree to help configure the SoC per board requirements.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:21 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am642-sk: Enable main_i2c0 and eeprom
Enable AT24C512C on the base board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:20 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am642-sk: Fix mmc1 pinmux
Fix the pinmux for pulldirection to get stable sdcard behavior.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 14 Apr 2023 07:33:19 +0000 (02:33 -0500)]
arm64: dts: ti: k3-am64: Add general purpose timers
There are 11 general purpose timers on am64 that can be used for things
like PWM using pwm-omap-dmtimer driver. There are also additional four
timers in the MCU domain that do not have interrupts routable for Linux.
We configure the timers with the 25 MHz input clock by default as the
32.768 kHz clock may not be wired on the device. We leave the MCU domain
timers clock mux unconfigured, and mark the MCU domain timers reserved.
The MCU domain timers are likely reserved by the software for the ESM
module.
Compared to am65, the timers on am64 do not have a dedicated IO mux for
the timers. On am62, the timers have different interrupts, clocks and
power domains compared to am65, and the MCU timers are at a different
IO address. Compared to AM62, the AM64 times have different clocks and
count in main domain are different as well.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230414073328.381336-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Linus Torvalds [Sun, 7 May 2023 20:34:35 +0000 (13:34 -0700)]
Linux 6.4-rc1
Linus Torvalds [Sun, 7 May 2023 18:32:18 +0000 (11:32 -0700)]
Merge tag 'perf-tools-for-v6.4-3-2023-05-06' of git://git./linux/kernel/git/acme/linux
Pull perf tool updates from Arnaldo Carvalho de Melo:
"Third version of perf tool updates, with the build problems with with
using a 'vmlinux.h' generated from the main build fixed, and the bpf
skeleton build disabled by default.
Build:
- Require libtraceevent to build, one can disable it using
NO_LIBTRACEEVENT=1.
It is required for tools like 'perf sched', 'perf kvm', 'perf
trace', etc.
libtraceevent is available in most distros so installing
'libtraceevent-devel' should be a one-time event to continue
building perf as usual.
Using NO_LIBTRACEEVENT=1 produces tooling that is functional and
sufficient for lots of users not interested in those libtraceevent
dependent features.
- Allow Python support in 'perf script' when libtraceevent isn't
linked, as not all features requires it, for instance Intel PT does
not use tracepoints.
- Error if the python interpreter needed for jevents to work isn't
available and NO_JEVENTS=1 isn't set, preventing a build without
support for JSON vendor events, which is a rare but possible
condition. The two check error messages:
$(error ERROR: No python interpreter needed for jevents generation. Install python or build with NO_JEVENTS=1.)
$(error ERROR: Python interpreter needed for jevents generation too old (older than 3.6). Install a newer python or build with NO_JEVENTS=1.)
- Make libbpf 1.0 the minimum required when building with out of
tree, distro provided libbpf.
- Use libsdtc++'s and LLVM's libcxx's __cxa_demangle, a portable C++
demangler, add 'perf test' entry for it.
- Make binutils libraries opt in, as distros disable building with it
due to licensing, they were used for C++ demangling, for instance.
- Switch libpfm4 to opt-out rather than opt-in, if libpfm-devel (or
equivalent) isn't installed, we'll just have a build warning:
Makefile.config:1144: libpfm4 not found, disables libpfm4 support. Please install libpfm4-dev
- Add a feature test for scandirat(), that is not implemented so far
in musl and uclibc, disabling features that need it, such as
scanning for tracepoints in /sys/kernel/tracing/events.
perf BPF filters:
- New feature where BPF can be used to filter samples, for instance:
$ sudo ./perf record -e cycles --filter 'period > 1000' true
$ sudo ./perf script
perf-exec 2273949 546850.708501: 5029 cycles:
ffffffff826f9e25 finish_wait+0x5 ([kernel.kallsyms])
perf-exec 2273949 546850.708508: 32409 cycles:
ffffffff826f9e25 finish_wait+0x5 ([kernel.kallsyms])
perf-exec 2273949 546850.708526: 143369 cycles:
ffffffff82b4cdbf xas_start+0x5f ([kernel.kallsyms])
perf-exec 2273949 546850.708600: 372650 cycles:
ffffffff8286b8f7 __pagevec_lru_add+0x117 ([kernel.kallsyms])
perf-exec 2273949 546850.708791: 482953 cycles:
ffffffff829190de __mod_memcg_lruvec_state+0x4e ([kernel.kallsyms])
true 2273949 546850.709036: 501985 cycles:
ffffffff828add7c tlb_gather_mmu+0x4c ([kernel.kallsyms])
true 2273949 546850.709292: 503065 cycles:
7f2446d97c03 _dl_map_object_deps+0x973 (/usr/lib/x86_64-linux-gnu/ld-linux-x86-64.so.2)
- In addition to 'period' (PERF_SAMPLE_PERIOD), the other
PERF_SAMPLE_ can be used for filtering, and also some other sample
accessible values, from tools/perf/Documentation/perf-record.txt:
Essentially the BPF filter expression is:
<term> <operator> <value> (("," | "||") <term> <operator> <value>)*
The <term> can be one of:
ip, id, tid, pid, cpu, time, addr, period, txn, weight, phys_addr,
code_pgsz, data_pgsz, weight1, weight2, weight3, ins_lat, retire_lat,
p_stage_cyc, mem_op, mem_lvl, mem_snoop, mem_remote, mem_lock,
mem_dtlb, mem_blk, mem_hops
The <operator> can be one of:
==, !=, >, >=, <, <=, &
The <value> can be one of:
<number> (for any term)
na, load, store, pfetch, exec (for mem_op)
l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl)
na, none, hit, miss, hitm, fwd, peer (for mem_snoop)
remote (for mem_remote)
na, locked (for mem_locked)
na, l1_hit, l1_miss, l2_hit, l2_miss, any_hit, any_miss, walk, fault (for mem_dtlb)
na, by_data, by_addr (for mem_blk)
hops0, hops1, hops2, hops3 (for mem_hops)
perf lock contention:
- Show lock type with address.
- Track and show mmap_lock, siglock and per-cpu rq_lock with address.
This is done for mmap_lock by following the current->mm pointer:
$ sudo ./perf lock con -abl -- sleep 10
contended total wait max wait avg wait address symbol
...
16344 312.30 ms 2.22 ms 19.11 us
ffff8cc702595640
17686 310.08 ms 1.49 ms 17.53 us
ffff8cc7025952c0
3 84.14 ms 45.79 ms 28.05 ms
ffff8cc78114c478 mmap_lock
3557 76.80 ms 68.75 us 21.59 us
ffff8cc77ca3af58
1 68.27 ms 68.27 ms 68.27 ms
ffff8cda745dfd70
9 54.53 ms 7.96 ms 6.06 ms
ffff8cc7642a48b8 mmap_lock
14629 44.01 ms 60.00 us 3.01 us
ffff8cc7625f9ca0
3481 42.63 ms 140.71 us 12.24 us
ffffffff937906ac vmap_area_lock
16194 38.73 ms 42.15 us 2.39 us
ffff8cd397cbc560
11 38.44 ms 10.39 ms 3.49 ms
ffff8ccd6d12fbb8 mmap_lock
1 5.43 ms 5.43 ms 5.43 ms
ffff8cd70018f0d8
1674 5.38 ms 422.93 us 3.21 us
ffffffff92e06080 tasklist_lock
581 4.51 ms 130.68 us 7.75 us
ffff8cc9b1259058
5 3.52 ms 1.27 ms 703.23 us
ffff8cc754510070
112 3.47 ms 56.47 us 31.02 us
ffff8ccee38b3120
381 3.31 ms 73.44 us 8.69 us
ffffffff93790690 purge_vmap_area_lock
255 3.19 ms 36.35 us 12.49 us
ffff8d053ce30c80
- Update default map size to 16384.
- Allocate single letter option -M for --map-nr-entries, as it is
proving being frequently used.
- Fix struct rq lock access for older kernels with BPF's CO-RE
(Compile once, run everywhere).
- Fix problems found with MSAn.
perf report/top:
- Add inline information when using --call-graph=fp or lbr, as was
already done to the --call-graph=dwarf callchain mode.
- Improve the 'srcfile' sort key performance by really using an
optimization introduced in 6.2 for the 'srcline' sort key that
avoids calling addr2line for comparision with each sample.
perf sched:
- Make 'perf sched latency/map/replay' to use "sched:sched_waking"
instead of "sched:sched_waking", consistent with 'perf record'
since
d566a9c2d482 ("perf sched: Prefer sched_waking event when it
exists").
perf ftrace:
- Make system wide the default target for latency subcommand, run the
following command then generate some network traffic and press
control+C:
# perf ftrace latency -T __kfree_skb
^C
DURATION | COUNT | GRAPH |
0 - 1 us | 27 | ############# |
1 - 2 us | 22 | ########### |
2 - 4 us | 8 | #### |
4 - 8 us | 5 | ## |
8 - 16 us | 24 | ############ |
16 - 32 us | 2 | # |
32 - 64 us | 1 | |
64 - 128 us | 0 | |
128 - 256 us | 0 | |
256 - 512 us | 0 | |
512 - 1024 us | 0 | |
1 - 2 ms | 0 | |
2 - 4 ms | 0 | |
4 - 8 ms | 0 | |
8 - 16 ms | 0 | |
16 - 32 ms | 0 | |
32 - 64 ms | 0 | |
64 - 128 ms | 0 | |
128 - 256 ms | 0 | |
256 - 512 ms | 0 | |
512 - 1024 ms | 0 | |
1 - ... s | 0 | |
#
perf top:
- Add --branch-history (LBR: Last Branch Record) option, just like
already available for 'perf record'.
- Fix segfault in thread__comm_len() where thread->comm was being
used outside thread->comm_lock.
perf annotate:
- Allow configuring objdump and addr2line in ~/.perfconfig., so that
you can use alternative binaries, such as llvm's.
perf kvm:
- Add TUI mode for 'perf kvm stat report'.
Reference counting:
- Add reference count checking infrastructure to check for use after
free, done to the 'cpumap', 'namespaces', 'maps' and 'map' structs,
more to come.
To build with it use -DREFCNT_CHECKING=1 in the make command line
to build tools/perf. Documented at:
https://perf.wiki.kernel.org/index.php/Reference_Count_Checking
- The above caught, for instance, fix, present in this series:
- Fix maps use after put in 'perf test "Share thread maps"':
'maps' is copied from leader, but the leader is put on line 79
and then 'maps' is used to read the reference count below - so
a use after put, with the put of maps happening within
thread__put.
Fixed by reversing the order of puts so that the leader is put
last.
- Also several fixes were made to places where reference counts were
not being held.
- Make this one of the tests in 'make -C tools/perf build-test' to
regularly build test it and to make sure no direct access to the
reference counted structs are made, doing that via accessors to
check the validity of the struct pointer.
ARM64:
- Fix 'perf report' segfault when filtering coresight traces by
sparse lists of CPUs.
- Add support for 'simd' as a sort field for 'perf report', to show
ARM's NEON SIMD's predicate flags: "partial" and "empty".
arm64 vendor events:
- Add N1 metrics.
Intel vendor events:
- Add graniterapids, grandridge and sierraforrest events.
- Refresh events for: alderlake, aldernaken, broadwell, broadwellde,
broadwellx, cascadelakx, haswell, haswellx, icelake, icelakex,
jaketown, meteorlake, knightslanding, sandybridge, sapphirerapids,
silvermont, skylake, tigerlake and westmereep-dp
- Refresh metrics for alderlake-n, broadwell, broadwellde,
broadwellx, haswell, haswellx, icelakex, ivybridge, ivytown and
skylakex.
perf stat:
- Implement --topdown using JSON metrics.
- Add TopdownL1 JSON metric as a default if present, but disable it
for now for some Intel hybrid architectures, a series of patches
addressing this is being reviewed and will be submitted for v6.5.
- Use metrics for --smi-cost.
- Update topdown documentation.
Vendor events (JSON) infrastructure:
- Add support for computing and printing metric threshold values. For
instance, here is one found in thesapphirerapids json file:
{
"BriefDescription": "Percentage of cycles spent in System Management Interrupts.",
"MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
"MetricGroup": "smi",
"MetricName": "smi_cycles",
"MetricThreshold": "smi_cycles > 0.1",
"ScaleUnit": "100%"
},
- Test parsing metric thresholds with the fake PMU in 'perf test
pmu-events'.
- Support for printing metric thresholds in 'perf list'.
- Add --metric-no-threshold option to 'perf stat'.
- Add rand (reverse and) and has_pmem (optane memory) support to
metrics.
- Sort list of input files to avoid depending on the order from
readdir() helping in obtaining reproducible builds.
S/390:
- Add common metrics: - CPI (cycles per instruction), prbstate (ratio
of instructions executed in problem state compared to total number
of instructions), l1mp (Level one instruction and data cache misses
per 100 instructions).
- Add cache metrics for z13, z14, z15 and z16.
- Add metric for TLB and cache.
ARM:
- Add raw decoding for SPE (Statistical Profiling Extension) v1.3 MTE
(Memory Tagging Extension) and MOPS (Memory Operations) load/store.
Intel PT hardware tracing:
- Add event type names UINTR (User interrupt delivered) and UIRET
(Exiting from user interrupt routine), documented in table 32-50
"CFE Packet Type and Vector Fields Details" in the Intel Processor
Trace chapter of The Intel SDM Volume 3 version 078.
- Add support for new branch instructions ERETS and ERETU.
- Fix CYC timestamps after standalone CBR
ARM CoreSight hardware tracing:
- Allow user to override timestamp and contextid settings.
- Fix segfault in dso lookup.
- Fix timeless decode mode detection.
- Add separate decode paths for timeless and per-thread modes.
auxtrace:
- Fix address filter entire kernel size.
Miscellaneous:
- Fix use-after-free and unaligned bugs in the PLT handling routines.
- Use zfree() to reduce chances of use after free.
- Add missing 0x prefix for addresses printed in hexadecimal in 'perf
probe'.
- Suppress massive unsupported target platform errors in the unwind
code.
- Fix return incorrect build_id size in elf_read_build_id().
- Fix 'perf scripts intel-pt-events.py' IPC output for Python 2 .
- Add missing new parameter in kfree_skb tracepoint to the python
scripts using it.
- Add 'perf bench syscall fork' benchmark.
- Add support for printing PERF_MEM_LVLNUM_UNC (Uncached access) in
'perf mem'.
- Fix wrong size expectation for perf test 'Setup struct
perf_event_attr' caused by the patch adding
perf_event_attr::config3.
- Fix some spelling mistakes"
* tag 'perf-tools-for-v6.4-3-2023-05-06' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: (365 commits)
Revert "perf build: Make BUILD_BPF_SKEL default, rename to NO_BPF_SKEL"
Revert "perf build: Warn for BPF skeletons if endian mismatches"
perf metrics: Fix SEGV with --for-each-cgroup
perf bpf skels: Stop using vmlinux.h generated from BTF, use subset of used structs + CO-RE
perf stat: Separate bperf from bpf_profiler
perf test record+probe_libc_inet_pton: Fix call chain match on x86_64
perf test record+probe_libc_inet_pton: Fix call chain match on s390
perf tracepoint: Fix memory leak in is_valid_tracepoint()
perf cs-etm: Add fix for coresight trace for any range of CPUs
perf build: Fix unescaped # in perf build-test
perf unwind: Suppress massive unsupported target platform errors
perf script: Add new parameter in kfree_skb tracepoint to the python scripts using it
perf script: Print raw ip instead of binary offset for callchain
perf symbols: Fix return incorrect build_id size in elf_read_build_id()
perf list: Modify the warning message about scandirat(3)
perf list: Fix memory leaks in print_tracepoint_events()
perf lock contention: Rework offset calculation with BPF CO-RE
perf lock contention: Fix struct rq lock access
perf stat: Disable TopdownL1 on hybrid
perf stat: Avoid SEGV on counter->name
...
Linus Torvalds [Sun, 7 May 2023 18:04:26 +0000 (11:04 -0700)]
Merge tag 'core-debugobjects-2023-05-06' of git://git./linux/kernel/git/tip/tip
Pull debugobjects fix from Thomas Gleixner:
"A single fix for debugobjects:
The recent fix to ensure atomicity of lookup and allocation
inadvertently broke the pool refill mechanism, so that debugobject
OOMs now in certain situations. The reason is that the functions which
got updated no longer invoke debug_objecs_init(), which is now the
only place to care about refilling the tracking object pool.
Restore the original behaviour by adding explicit refill opportunities
to those places"
* tag 'core-debugobjects-2023-05-06' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
debugobject: Ensure pool refill (again)
Linus Torvalds [Sun, 7 May 2023 17:57:14 +0000 (10:57 -0700)]
Merge tag 'v6.4-p2' of git://git./linux/kernel/git/herbert/crypto-2.6
Pull crypto fixes from Herbert Xu:
- A long-standing bug in crypto_engine
- A buggy but harmless check in the sun8i-ss driver
- A regression in the CRYPTO_USER interface
* tag 'v6.4-p2' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
crypto: api - Fix CRYPTO_USER checks for report function
crypto: engine - fix crypto_queue backlog handling
crypto: sun8i-ss - Fix a test in sun8i_ss_setup_ivs()
Linus Torvalds [Sun, 7 May 2023 17:46:21 +0000 (10:46 -0700)]
Merge tag '6.4-rc-smb3-client-fixes-part2' of git://git.samba.org/sfrench/cifs-2.6
Pull cifs fixes from Steve French:
"smb3 client fixes, mostly DFS or reconnect related:
- Two DFS connection sharing fixes
- DFS refresh fix
- Reconnect fix
- Two potential use after free fixes
- Also print prefix patch in mount debug msg
- Two small cleanup fixes"
* tag '6.4-rc-smb3-client-fixes-part2' of git://git.samba.org/sfrench/cifs-2.6:
cifs: Remove unneeded semicolon
cifs: fix sharing of DFS connections
cifs: avoid potential races when handling multiple dfs tcons
cifs: protect access of TCP_Server_Info::{origin,leaf}_fullpath
cifs: fix potential race when tree connecting ipc
cifs: fix potential use-after-free bugs in TCP_Server_Info::hostname
cifs: print smb3_fs_context::source when mounting
cifs: protect session status check in smb2_reconnect()
SMB3.1.1: correct definition for app_instance_id create contexts
Linus Torvalds [Sun, 7 May 2023 17:31:45 +0000 (10:31 -0700)]
Merge tag 'clk-for-linus' of git://git./linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A couple more patches that would be good to get into -rc1:
- Revert an i.MX patch that's causing video failures because division
math goes sideways
- Fix a clang + W=1 build isue where FIELD_PREP() is taking a 32-bit
variable instead of the usual u64 type
- Fix a Kconfig bug in the StarFive JH7110 clk config that selects a
reset controller when it can't be selected"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: starfive: Fix RESET_STARFIVE_JH7110 can't be selected in a specified case
clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()
Revert "clk: imx: composite-8m: Add support to determine_rate"
Linus Torvalds [Sun, 7 May 2023 17:17:33 +0000 (10:17 -0700)]
Merge tag 'mailbox-v6.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar:
- mailbox api: allow direct registration to a channel and convert omap
and pcc to use mbox_bind_client
- omap and hi6220 : use of_property_read_bool
- test: fix double-free and use spinlock header
- rockchip and bcm-pdc: drop of_match_ptr
- mpfs: change config symbol
- mediatek gce: support MT6795
- qcom apcs: consolidate of_device_id and support IPQ9574
* tag 'mailbox-v6.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
dt-bindings: mailbox: qcom: add compatible for IPQ9574 SoC
mailbox: qcom-apcs-ipc: do not grow the of_device_id
dt-bindings: mailbox: qcom,apcs-kpss-global: use fallbacks for few variants
dt-bindings: mailbox: mediatek,gce-mailbox: Add support for MT6795
mailbox: mpfs: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE
mailbox: bcm-pdc: drop of_match_ptr for ID table
mailbox: rockchip: drop of_match_ptr for ID table
mailbox: mailbox-test: Fix potential double-free in mbox_test_message_write()
mailbox: mailbox-test: Explicitly include header for spinlock support
mailbox: Use of_property_read_bool() for boolean properties
mailbox: pcc: Use mbox_bind_client
mailbox: omap: Use mbox_bind_client
mailbox: Allow direct registration to a channel
Linus Torvalds [Sun, 7 May 2023 17:00:09 +0000 (10:00 -0700)]
Merge tag 'for-6.4/io_uring-2023-05-07' of git://git.kernel.dk/linux
Pull more io_uring updates from Jens Axboe:
"Nothing major in here, just two different parts:
- A small series from Breno that enables passing the full SQE down
for ->uring_cmd().
This is a prerequisite for enabling full network socket operations.
Queued up a bit late because of some stylistic concerns that got
resolved, would be nice to have this in 6.4-rc1 so the dependent
work will be easier to handle for 6.5.
- Fix for the huge page coalescing, which was a regression introduced
in the 6.3 kernel release (Tobias)"
* tag 'for-6.4/io_uring-2023-05-07' of git://git.kernel.dk/linux:
io_uring: Remove unnecessary BUILD_BUG_ON
io_uring: Pass whole sqe to commands
io_uring: Create a helper to return the SQE size
io_uring/rsrc: check for nonconsecutive pages
Arnaldo Carvalho de Melo [Sat, 6 May 2023 21:07:37 +0000 (18:07 -0300)]
Revert "perf build: Make BUILD_BPF_SKEL default, rename to NO_BPF_SKEL"
This reverts commit
a980755beb5aca9002e1c95ba519b83a44242b5b.
We need to better polish building with BPF skels, so revert back to
making it an experimental feature that has to be explicitely enabled
using BUILD_BPF_SKEL=1.
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Arnaldo Carvalho de Melo [Sat, 6 May 2023 21:06:43 +0000 (18:06 -0300)]
Revert "perf build: Warn for BPF skeletons if endian mismatches"
This reverts commit
51924ae69eea5bc90b5da525fbcf4bbd5f8551b3.
We need to better polish building with BPF skels, so revert back to
making it an experimental feature that has to be explicitely enabled
using BUILD_BPF_SKEL=1.
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Linus Torvalds [Sat, 6 May 2023 18:43:08 +0000 (11:43 -0700)]
Merge tag 'mm-stable-2023-05-06-10-49' of git://git./linux/kernel/git/akpm/mm
Pull dmapool updates - again - from Andrew Morton:
"Reinstate the dmapool changes which were accidentally removed by a
mishap on the last commit in the previous attempt at the series"
Fixes:
2d55c16c0c54 ("dmapool: create/destroy cleanup").
[ The whole old series:
def8574308ed..
2d55c16c0c54 results in an empty
diff because that last commit ended up being just a revert of all that
came everything before it. - Linus ]
* tag 'mm-stable-2023-05-06-10-49' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm:
dmapool: link blocks across pages
dmapool: don't memset on free twice
dmapool: simplify freeing
dmapool: consolidate page initialization
dmapool: rearrange page alloc failure handling
dmapool: move debug code to own functions
dmapool: speedup DMAPOOL_DEBUG with init_on_alloc
dmapool: cleanup integer types
dmapool: use sysfs_emit() instead of scnprintf()
dmapool: remove checks for dev == NULL
Linus Torvalds [Sat, 6 May 2023 18:25:03 +0000 (11:25 -0700)]
Merge tag 'mm-hotfixes-stable-2023-05-06-10-45' of git://git./linux/kernel/git/akpm/mm
Pull hotfixes from Andrew Morton:
"Five hotfixes.
Three are cc:stable, two pertain to merge window changes"
* tag 'mm-hotfixes-stable-2023-05-06-10-45' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm:
afs: fix the afs_dir_get_folio return value
nilfs2: do not write dirty data after degenerating to read-only
mm: do not reclaim private data from pinned page
nilfs2: fix infinite loop in nilfs_mdt_get_block()
mm/mmap/vma_merge: always check invariants
Keith Busch [Thu, 26 Jan 2023 21:51:24 +0000 (13:51 -0800)]
dmapool: link blocks across pages
The allocated dmapool pages are never freed for the lifetime of the pool.
There is no need for the two level list+stack lookup for finding a free
block since nothing is ever removed from the list. Just use a simple
stack, reducing time complexity to constant.
The implementation inserts the stack linking elements and the dma handle
of the block within itself when freed. This means the smallest possible
dmapool block is increased to at most 16 bytes to accommodate these
fields, but there are no exisiting users requesting a dma pool smaller
than that anyway.
Removing the list has a significant change in performance. Using the
kernel's micro-benchmarking self test:
Before:
# modprobe dmapool_test
dmapool test: size:16 blocks:8192 time:57282
dmapool test: size:64 blocks:8192 time:172562
dmapool test: size:256 blocks:8192 time:789247
dmapool test: size:1024 blocks:2048 time:371823
dmapool test: size:4096 blocks:1024 time:362237
After:
# modprobe dmapool_test
dmapool test: size:16 blocks:8192 time:24997
dmapool test: size:64 blocks:8192 time:26584
dmapool test: size:256 blocks:8192 time:33542
dmapool test: size:1024 blocks:2048 time:9022
dmapool test: size:4096 blocks:1024 time:6045
The module test allocates quite a few blocks that may not accurately
represent how these pools are used in real life. For a more marco level
benchmark, running fio high-depth + high-batched on nvme, this patch shows
submission and completion latency reduced by ~100usec each, 1% IOPs
improvement, and perf record's time spent in dma_pool_alloc/free were
reduced by half.
[kbusch@kernel.org: push new blocks in ascending order]
Link: https://lkml.kernel.org/r/20230221165400.1595247-1-kbusch@meta.com
Link: https://lkml.kernel.org/r/20230126215125.4069751-12-kbusch@meta.com
Fixes:
2d55c16c0c54 ("dmapool: create/destroy cleanup")
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Tony Battersby <tonyb@cybernetics.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Keith Busch [Thu, 26 Jan 2023 21:51:23 +0000 (13:51 -0800)]
dmapool: don't memset on free twice
If debug is enabled, dmapool will poison the range, so no need to clear it
to 0 immediately before writing over it.
Link: https://lkml.kernel.org/r/20230126215125.4069751-11-kbusch@meta.com
Fixes:
2d55c16c0c54 ("dmapool: create/destroy cleanup")
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Tony Battersby <tonyb@cybernetics.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Keith Busch [Thu, 26 Jan 2023 21:51:22 +0000 (13:51 -0800)]
dmapool: simplify freeing
The actions for busy and not busy are mostly the same, so combine these
and remove the unnecessary function. Also, the pool is about to be freed
so there's no need to poison the page data since we only check for poison
on alloc, which can't be done on a freed pool.
Link: https://lkml.kernel.org/r/20230126215125.4069751-10-kbusch@meta.com
Fixes:
2d55c16c0c54 ("dmapool: create/destroy cleanup")
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Tony Battersby <tonyb@cybernetics.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Keith Busch [Thu, 26 Jan 2023 21:51:21 +0000 (13:51 -0800)]
dmapool: consolidate page initialization
Various fields of the dma pool are set in different places. Move it all
to one function.
Link: https://lkml.kernel.org/r/20230126215125.4069751-9-kbusch@meta.com
Fixes:
2d55c16c0c54 ("dmapool: create/destroy cleanup")
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Tony Battersby <tonyb@cybernetics.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Keith Busch [Thu, 26 Jan 2023 21:51:20 +0000 (13:51 -0800)]
dmapool: rearrange page alloc failure handling
Handle the error in a condition so the good path can be in the normal
flow.
Link: https://lkml.kernel.org/r/20230126215125.4069751-8-kbusch@meta.com
Fixes:
2d55c16c0c54 ("dmapool: create/destroy cleanup")
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Tony Battersby <tonyb@cybernetics.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Keith Busch [Thu, 26 Jan 2023 21:51:19 +0000 (13:51 -0800)]
dmapool: move debug code to own functions
Clean up the normal path by moving the debug code outside it.
Link: https://lkml.kernel.org/r/20230126215125.4069751-7-kbusch@meta.com
Fixes:
2d55c16c0c54 ("dmapool: create/destroy cleanup")
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Tony Battersby <tonyb@cybernetics.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Tony Battersby [Thu, 26 Jan 2023 21:51:18 +0000 (13:51 -0800)]
dmapool: speedup DMAPOOL_DEBUG with init_on_alloc
Avoid double-memset of the same allocated memory in dma_pool_alloc() when
both DMAPOOL_DEBUG is enabled and init_on_alloc=1.
Link: https://lkml.kernel.org/r/20230126215125.4069751-6-kbusch@meta.com
Fixes:
2d55c16c0c54 ("dmapool: create/destroy cleanup")
Signed-off-by: Tony Battersby <tonyb@cybernetics.com>
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Matthew Wilcox <willy@infradead.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Tony Battersby [Thu, 26 Jan 2023 21:51:17 +0000 (13:51 -0800)]
dmapool: cleanup integer types
To represent the size of a single allocation, dmapool currently uses
'unsigned int' in some places and 'size_t' in other places. Standardize
on 'unsigned int' to reduce overhead, but use 'size_t' when counting all
the blocks in the entire pool.
Link: https://lkml.kernel.org/r/20230126215125.4069751-5-kbusch@meta.com
Fixes:
2d55c16c0c54 ("dmapool: create/destroy cleanup")
Signed-off-by: Tony Battersby <tonyb@cybernetics.com>
Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Cc: Matthew Wilcox <willy@infradead.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>