Iago Toral Quiroga [Tue, 30 May 2017 11:25:35 +0000 (13:25 +0200)]
glcpp: fix #undef to match latest spec update and GLSLang implementation
GLSL ES spec includes the following:
"It is an error to undefine or to redefine a built-in
(pre-defined) macro name."
But desktop GLSL doesn't. This has sparked some discussion
in Khronos, and the final conclusion was to update the
GLSL 4.50 spec to include the following:
"By convention, all macro names containing two consecutive
underscores ( __ ) are reserved for use by underlying
software layers. Defining or undefining such a name in a
shader does not itself result in an error, but may result
in unintended behaviors that stem from having multiple
definitions of the same name. All macro names prefixed
with “GL_” (“GL” followed by a single underscore) are also
reserved, and defining or undefining such a name results in
a compile-time error."
In other words, undefining GL_* names should be an error, but
undefining other names with a double underscore in them is
not strictly prohibited in desktop GLSL.
This patch fixes the preprocessor to apply these rules,
following exactly the implementation already present
in GLSLang. This fixes some tests in CTS.
Khronos bug:
https://cvs.khronos.org/bugzilla/show_bug.cgi?id=16003
Fixes:
KHR-GL45.shaders.preprocessor.definitions.undefine_core_profile_vertex
KHR-GL45.shaders.preprocessor.definitions.undefine_core_profile_fragment
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Mon, 5 Jun 2017 20:20:33 +0000 (21:20 +0100)]
ac/nir: move gpr counting inside argument handling.
This just moves this code in here to it's cleaner.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 20:11:05 +0000 (21:11 +0100)]
ac/nir: assign argument param pointers in one place.
Instead of having the fragile code to do a second pass, just
give the pointers you want params in to the initial code,
then call a later pass to assign them.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 06:51:07 +0000 (07:51 +0100)]
ac/nir: consolidate setting userdata location
Just pass a pointer and increment inside the function,
makes the code less error prone.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Tue, 6 Jun 2017 05:08:16 +0000 (15:08 +1000)]
glthread: remove extra _mesa_glthread_finish() from generated code
The other user of print_sync_dispatch() was ending up with code that
looked like:
_mesa_glthread_finish(ctx);
_mesa_glthread_restore_dispatch(ctx);
_mesa_glthread_finish(ctx);
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Anuj Phogat [Tue, 6 Jun 2017 23:14:19 +0000 (16:14 -0700)]
intel: Fix broxton 2x6 way size computation
This patch is undoing the changes to way size computation
in broxton 2x6, made by below commit:
Commit:
0d576fbfbe912cf3fb9ab594bb31eb58bccf2138
Author: Anuj Phogat <anuj.phogat@gmail.com>
i965: Simplify l3 way size computations
By making use of l3_banks field in gen_device_info struct
l3_way_size for gen7+ = 2 * l3_banks.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101306
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Dave Airlie [Tue, 6 Jun 2017 23:34:28 +0000 (09:34 +1000)]
radv: move chip_class extraction down further.
This seems to matter here in a profile, without this we spend a lot
more time exiting this function with no flush bits.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 6 Jun 2017 23:14:54 +0000 (09:14 +1000)]
radv: move lots of index related things into the bind.
This just moves lots of stuff to the bind stage rather than
dealing with it in the draw stage.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 6 Jun 2017 23:04:30 +0000 (09:04 +1000)]
radv: move calculating the vertex sgpr to the pipeline.
There is no need to calculate this at draw time.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 6 Jun 2017 23:01:38 +0000 (09:01 +1000)]
radv: rename and make global some functions.
I want to use these in the pipeline setup stage.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Engestrom [Thu, 1 Jun 2017 13:48:06 +0000 (14:48 +0100)]
tree-wide: remove trailing backslash
Simple search for a backslash followed by two newlines.
If one of the newlines were to be removed, this would cause issues, so
let's just remove these trailing backslashes.
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Dave Airlie [Tue, 6 Jun 2017 22:09:03 +0000 (08:09 +1000)]
radv/gfx9: use correct register setting for uconfig regs
Thanks to Marek for pointing this out.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 6 Jun 2017 20:03:49 +0000 (22:03 +0200)]
radv: Remove SI num RB override for occlusion queries.
radeonsi doesn't have it anymore either.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 6 Jun 2017 19:52:15 +0000 (21:52 +0200)]
radv: Split out updating the vertex descriptors.
Simple refactor.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 6 Jun 2017 19:39:42 +0000 (21:39 +0200)]
radv: Move pipeline stuff from flush_state to emit_graphics_pipeline.
No functional changes.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 6 Jun 2017 17:15:47 +0000 (19:15 +0200)]
radv: Add early exit for cache flushes.
No sense checking each bit separately in the common case of none
being set.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 6 Jun 2017 16:43:38 +0000 (18:43 +0200)]
radv: Remove vertex_descriptors_dirty.
Redundant.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 6 Jun 2017 16:22:23 +0000 (18:22 +0200)]
radv: Don't use a divide by index_size.
Divides are pretty slow, and this is in the hot path of a draw.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Chris Wilson [Fri, 17 Mar 2017 07:58:13 +0000 (00:58 -0700)]
i965: Explicitly disallow tiled memcpy path on Gen4 with swizzling.
The manual detiling paths are not prepared to handle Gen4-G45 with
swizzling enabled, so explicitly disable them. (They're already
disabled because these platforms don't have LLC but a future patch could
enable this path).
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 1 Jun 2017 04:18:38 +0000 (21:18 -0700)]
i965: Remove brw_bo_map_unsynchronized()
Call brw_bo_map() directly.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 5 Jun 2017 16:54:06 +0000 (09:54 -0700)]
i965: Use unsynchronized mappings for BufferSubData on non-LLC
Now that unsynchronized maps actually work, we can use them, like we do
on LLC platforms.
On Broxton, the performance of Unigine Valley 1.1-rc1 is improved by
37.6656% +/- 0.401389% (n=20) at 1280x720/QUALITY_LOW, and by
20.862% +/- 2.20901% (n=3) at 1920x1080/QUALITY_LOW.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 1 Jun 2017 04:14:15 +0000 (21:14 -0700)]
i965: Make unsynchronized maps unsynchronized on non-LLC
On Broxton, the performance of Unigine Valley 1.0 is improved by
13.3067% +/- 0.144322% (n=40) at 1280x720/QUALITY_LOW, and by
1.68478% +/- 0.484226% (n=3) at 1920x1080/QUALITY_LOW.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 1 Jun 2017 04:12:01 +0000 (21:12 -0700)]
i965: Implement brw_bo_map_unsynchronized() with MAP_ASYNC
This way we can let brw_bo_map() choose the best mapping type.
Part of the patch inlines map_gtt() into brw_bo_map_gtt() (and removes
map_gtt()). brw_bo_map_gtt() just wrapped map_gtt() with locking and a
call to set_domain(). map_gtt() is called by brw_bo_map_unsynchronized()
to avoid the call to set_domain(). With the MAP_ASYNC flag, we now have
the same behavior previously provided by brw_bo_map_unsynchronized().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 1 Jun 2017 04:06:18 +0000 (21:06 -0700)]
i965: Elide call to set_domain() if MAP_ASYNC
No functional change (no callers currently pass MAP_ASYNC)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 18 May 2017 18:26:08 +0000 (11:26 -0700)]
i965: Add and use brw_bo_map()
We can encapsulate the logic for choosing the mapping type. This will
also help when we add WC mappings.
A few functional changes are made in this patch. On non-LLC, what were
previously WB mappings are now GTT mappings (in the prefilling debug
code in brw_performance_query.c; the shader_time code in brw_program.c;
and in the case of an RW mapping in intel_buffer_objects.c).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 18 May 2017 18:29:00 +0000 (11:29 -0700)]
i965: Drop MAP_READ from some write-only mappings
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 18 May 2017 17:59:23 +0000 (10:59 -0700)]
i965: Pass flags to brw_bo_map_*
brw_bo_map_cpu() took a write_enable arg, but it wasn't always clear
whether we were also planning to read from the buffer. I kept everything
semantically identical by passing only MAP_READ or MAP_READ | MAP_WRITE
depending on the write_enable argument.
The other flags are not used yet, but MAP_ASYNC for instance, will be
used in a later patch to remove the need for a separate
brw_bo_map_unsynchronized() function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 17 May 2017 22:44:30 +0000 (15:44 -0700)]
i965: Rename brw_bo_map() -> brw_bo_map_cpu()
I'm going to make a new function named brw_bo_map() in a later patch
that is responsible for choosing the mapping type, so this patch clears
the way.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 17 May 2017 18:41:40 +0000 (11:41 -0700)]
i965: Rename *_virtual -> map_*
I think these are better names, and it reduces the delta between
upstream and Chris Wilson's brw-batch branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Wed, 6 May 2015 10:19:44 +0000 (11:19 +0100)]
i965: Pass the map-mode along to intel_mipmap_tree_map_raw()
Since we can distinguish when mapping between READ and WRITE, we can
pass along the map mode to avoid stalls and flushes where possible.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Thu, 18 May 2017 19:02:39 +0000 (12:02 -0700)]
i965: Add a cache_coherent field to brw_bo
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 11 May 2017 18:53:27 +0000 (11:53 -0700)]
i965: Remove unused 'use_resource_streamer' field
Missing in the resource streamer removal of commit
951f56cd43bc.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Fri, 5 May 2017 18:20:05 +0000 (11:20 -0700)]
i965: Remove brw_bo's virtual member
Just return the map from brw_map_bo_*
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 3 May 2017 21:19:11 +0000 (14:19 -0700)]
i965: Remove unused brw_bo_map__* functions
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alex Smith [Mon, 5 Jun 2017 14:49:05 +0000 (15:49 +0100)]
anv: Set better descriptor set limits
Based on discussions with Jason, Ivy Bridge and Bay Trail only actually
support 16 samplers, while newer hardware can support more than the
current limit of 64. Therefore set the lower limit where needed, and
bump up to 128 for everything else. There is also a limit on the total
number of other resources of around 250.
This allows Dawn of War III to render correctly on ANV.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alex Smith [Tue, 6 Jun 2017 09:42:41 +0000 (10:42 +0100)]
anv: Set driver version to Mesa version
As already done by RADV.
v2: Move version calculation function to src/vulkan/util to share with
RADV.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alex Smith [Tue, 6 Jun 2017 15:09:07 +0000 (16:09 +0100)]
radv/vulkan: Move radv_get_driver_version to src/vulkan/util
This means it can be reused for other Vulkan drivers. Also fix up a
typo, need to search for '.' in the version string rather than ','.
v2: Remove unneeded temporary version variable (Emil, Eric)
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alex Smith [Tue, 6 Jun 2017 11:31:05 +0000 (12:31 +0100)]
util/vulkan: Move Vulkan utilities to src/vulkan/util
We have Vulkan utilities in both src/util and src/vulkan/util. The
latter seems a more appropriate place for Vulkan-specific things, so
move them there.
v2: Android build system changes (from Tapani Pälli)
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Tue, 30 May 2017 19:06:48 +0000 (20:06 +0100)]
intel: gen-decoder: rework how we handle groups
The current way of handling groups doesn't seem to be able to handle
MI_LOAD_REGISTER_* with more than one register. This change reworks
the way we handle groups by building a traversal list on loading the
GENXML files.
Let's say you have
Instruction {
Field0
Field1
Field2
Group0 (count=2) {
Field0-0
Field0-1
}
Group1 (count=4) {
Field1-0
Field1-1
}
}
We build of linked on load that goes :
Instruction -> Group0 -> Group1
All of those are gen_group structures, making the traversal trivial.
We just need to iterate groups for the right number of timers (count
field in genxml).
The more fancy case is when you have only a single group of unknown
size (count=0). In that case we keep on reading that group for as long
as we're within the DWordLength of that instruction.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Marek Olšák [Tue, 23 May 2017 19:52:11 +0000 (21:52 +0200)]
radeonsi: fix a GPU hang with tessellation on 2-CU configs
Only harvested Stoney has 2 CUs. Tested on 2-CU Stoney and Fiji forced
to 2 CUs.
Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Samuel Pitoiset [Fri, 2 Jun 2017 12:31:49 +0000 (14:31 +0200)]
mesa: make use of NewWindowRectangles driver flags
Now, st_update_window_rectangles() won't be called when the
scissor is going to be updated.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 12:31:48 +0000 (14:31 +0200)]
mesa: add new gl_driver_flags::NewWindowRectangles
This new driver flag will replace _NEW_SCISSOR which is
emitted when setting new window rectangles but it actually
triggers useless changes in the state tracker (like scissor
and rasterizer).
EXT_window_rectangles is currently only supported by Nouveau.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 12:31:47 +0000 (14:31 +0200)]
mesa: remove call to Driver.Scissor() in _mesa_WindowRectanglesEXT()
This is actually useless because this driver call is only used
by the classic DRI drivers which don't support that extension
and probably won't never support it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 15:52:49 +0000 (17:52 +0200)]
mesa: only emit _NEW_MULTISAMPLE when min sample shading changes
We usually check that given parameters are different before
updating the state.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 15:52:48 +0000 (17:52 +0200)]
mesa: only emit _NEW_MULTISAMPLE when sample mask changes
We usually check that given parameters are different before
updating the state.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 2 Jun 2017 15:52:47 +0000 (17:52 +0200)]
mesa: only emit _NEW_MULTISAMPLE when coverage parameters change
We usually check that given parameters are different before
updating the state.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Sat, 3 Jun 2017 19:26:29 +0000 (12:26 -0700)]
i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.
We moved to INTEL_SCALAR_* when we added more than a single stage, but
never went back and converted the VS to work that way. Be consistent.
Also update the documentation to actually mention these debug variables.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Mon, 15 May 2017 01:27:10 +0000 (11:27 +1000)]
radv: expose integrated device type for APUs.
This just sets the vulkan device type depending on whether
this is an APU or GPU.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Bas Nieuwenhuizen [Sun, 21 May 2017 21:40:54 +0000 (23:40 +0200)]
ac/surface: Fix HTILE for radv.
We always compute HTILE size using addrlib, even when not TC compatible.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlied <airlied@redhat.com>
Dave Airlie [Tue, 6 Jun 2017 00:39:16 +0000 (10:39 +1000)]
radv: fix write event eop on vega.
Typo here, fixes command submission hangs on vega
Dave Airlie [Mon, 5 Jun 2017 23:06:57 +0000 (09:06 +1000)]
radv: enable GFX9 on radv
I'm open to reverting this closer to release if bad things
happen, but it might be easier to debugging to leave it for now.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:06:41 +0000 (09:06 +1000)]
radv: turn off geom/tess for gfx9.
We don't support these yet, and it'll take a bit of work to do so.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:06:21 +0000 (09:06 +1000)]
radv: misc GFX9 changes.
These are just some register changes ported from radeonsi for gfx9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:05:47 +0000 (09:05 +1000)]
radv: add some GFX9 specific events.
These are ported from radeonsi, don't know all the rules for
when they should be inserted.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:05:12 +0000 (09:05 +1000)]
radv: add IA_MULTI_VGT_PARAM support for GFX9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:03:55 +0000 (09:03 +1000)]
radv: add rb+ support for GFX9
This adds some rb+ support, as on GFX9 we have to disable
it as per radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 23:01:48 +0000 (09:01 +1000)]
radv: add GFX9 cache flushing support.
GFX9 needs to write event EOP to a fence buffer, allocate some
space for this, and just write an ever increasing number to it,
this isn't exactly what radeonsi does, but it seems to work.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:54:38 +0000 (08:54 +1000)]
radv: add texture descriptor/fmask/cmask support for GFX9
This adds gfx9 support for the texture descriptor along
with the fmask/cmask allocation routines.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:50:14 +0000 (08:50 +1000)]
radv: add GFX9 to initialisation cmd buffer.
This just adds support for initialising some GFX9 registers,
and handles the different init for the VGT reuse reg.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:48:25 +0000 (08:48 +1000)]
radv: don't setup raster_config on gfx9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:47:22 +0000 (08:47 +1000)]
radv: add gfx9 cp dma support.
This adds support to the CP dma code for GFX9, ported from
radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:39:44 +0000 (08:39 +1000)]
radv: add gfx9 depth/stencil surface support.
This is ported from radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:38:36 +0000 (08:38 +1000)]
radv: add GFX9 support for color surfaces.
This is ported from radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:33:53 +0000 (08:33 +1000)]
radv: add some misc gfx9 pieces.
This just adds the strings and includes the gfx9 register defs
in some files that we need them in.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:36:24 +0000 (08:36 +1000)]
radv: set offchip hs param like radeonsi.
radeonsi never uses 512 here anymore.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:58:54 +0000 (08:58 +1000)]
radv: fix typo in comment.
Dave Airlie [Mon, 5 Jun 2017 22:43:38 +0000 (08:43 +1000)]
radv: add a comment from radeonsi before cp dma function.
This is just copied over.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 22:27:35 +0000 (08:27 +1000)]
radv: remove doubled up prototype.
Must have snuck in during a rebase.
Dave Airlie [Wed, 24 May 2017 01:37:06 +0000 (11:37 +1000)]
radv: split metadata struct into legacy/gfx9 parts.
This is just ported from radeonsi.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 01:09:30 +0000 (02:09 +0100)]
radv: refactor some texture descriptor state.
This just splits out some non-gfx9 bits in advance to avoid
regressions.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 01:05:59 +0000 (02:05 +0100)]
radv: refactor color surface init before gfx9.
This just moves the code around in preparation for gfx9 support.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 01:01:10 +0000 (02:01 +0100)]
radv: refactor depth/stencil state setup
In advance of GFX9 to reduce chances for regression, refactor
this code out so adding the GFX9 changes will be more obvious.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 5 Jun 2017 02:07:26 +0000 (12:07 +1000)]
radv: use radv_foreach_stage in a couple of places.
This just collapses a few per-stage things into a loop,
shouldn't affect anything.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Emil Velikov [Wed, 31 May 2017 20:08:45 +0000 (15:08 -0500)]
radeon: remove out of date LLVM_REVISION.txt
The file was introduced to track which LLVM revision was required, yet
that has quickly gone out of shape.
It has seen no updates since 2013.
Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Aaron Watry <awatry@gmail.com>
Juan A. Suarez Romero [Mon, 5 Jun 2017 21:21:35 +0000 (21:21 +0000)]
docs: update calendar, add news item and link release notes for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Juan A. Suarez Romero [Mon, 5 Jun 2017 21:15:43 +0000 (21:15 +0000)]
docs: add sha256 checksums for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
4908b1e909ba4cfd5391f61ea551d21cccb52e2f)
Juan A. Suarez Romero [Mon, 5 Jun 2017 20:27:24 +0000 (20:27 +0000)]
docs: add release notes for 17.1.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
97f6404e50212fb65fe047e467f5497bcba5b8ac)
Brian Paul [Mon, 5 Jun 2017 20:13:14 +0000 (14:13 -0600)]
gallium/u_threaded: fixes for MSVC
Replace some static assertions with runtime assertions. The static
asserts don't work/fail on MSVC, despite the offsets being multiples
of 16 (checked with softpipe).
Use correct parameter types for a few gallium context functions.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Mon, 5 Jun 2017 03:34:05 +0000 (13:34 +1000)]
r600: refactor out some compressed resource state code.
This just takes this out to a separate function as it will
get more complex with images.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Dave Airlie [Mon, 5 Jun 2017 03:25:29 +0000 (13:25 +1000)]
r600: document some of the missing shader constants.
These are used for fragment shader thread calculations.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Dave Airlie [Mon, 5 Jun 2017 03:24:12 +0000 (13:24 +1000)]
r600: add register info for atomic counters.
The atomic counters on evergreen are implemented via append/consume
UAV counters. This just adds the register info for them. The EOS
packets are used to get the atomic totals extracted post shader
execution for storing into a buffer.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Dave Airlie [Mon, 5 Jun 2017 03:22:07 +0000 (13:22 +1000)]
r600: add missing RAT registers and operations.
This just documents in the headers the RAT operation list,
and the RAT encoding for exports.
The immediate registers are used to point to buffers for the
RAT return values (_RTN instructions).
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Dave Airlie [Mon, 5 Jun 2017 19:38:34 +0000 (05:38 +1000)]
r600/sb: fix typo in field definitions
Pointed out by glennk.
Marek Olšák [Tue, 30 May 2017 00:04:29 +0000 (02:04 +0200)]
tgsi/scan: fix scanning fragment shaders with PrimID and Position/Face
Not relevant to radeonsi, because Position/Face are system values
with radeonsi, while this codepath is for drivers where Position and
Face are ordinary inputs.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jason Ekstrand [Fri, 26 May 2017 17:57:33 +0000 (10:57 -0700)]
i965: Finalize miptrees before prepare_texture
In order to do resolves for texture views with different formats, we
need intel_texture_object::_Format to be valid. Calling
intel_finalize_mipmap_tree can safely be done multiple times in a row
and should be a fairly cheap operation.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Marek Olšák [Tue, 30 May 2017 23:46:40 +0000 (01:46 +0200)]
gallium/u_threaded: remove 16 bytes from tc_batch
All other sentinels occupy what is otherwise unused space.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Tue, 30 May 2017 23:32:01 +0000 (01:32 +0200)]
gallium/u_threaded: align batches and call slots to 16 bytes
not sure if this helps
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Wed, 31 May 2017 11:07:04 +0000 (13:07 +0200)]
st/mesa: don't load cached TGSI shaders on demand
This fixes a performance issue with the shader cache that delayed Gallium
shader create calls until draw calls.
I'd like this in stable, but it's not a showstopper.
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Chih-Wei Huang [Sun, 4 Jun 2017 04:53:01 +0000 (12:53 +0800)]
Android: use bionic pthread_barrier_* if possible
The pthread_barrier_* functions were introduced to bionic
since Nougat.
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Dave Airlie [Mon, 5 Jun 2017 03:19:18 +0000 (13:19 +1000)]
r600: fix incorrect and missing bit field in register headers.
The compression field was incorrect, and we were missing the
depth before shader field.
Nicolai Hähnle [Thu, 11 May 2017 23:46:46 +0000 (01:46 +0200)]
radv: use ac_compute_surface
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Sun, 14 May 2017 23:43:25 +0000 (09:43 +1000)]
radv: prepare fmask surface creation
The old code copied over all the surface info from the image
surface, we only want some bits of it, and to modify the flags.
This prevents a regression in dEQP-VK.api.copy_and_blit.resolve_image.*
and others in the subsequent switch to ac_compute_surface.
v2:
- also disable opt4Space in radv_amdgpu_surface, so that we can
apply this patch separately *before* switching to ac_compute_surface
and hopefully avoid intermittent regressions (Nicolai)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Thu, 11 May 2017 23:38:49 +0000 (01:38 +0200)]
radv: use amdgpu_addr_create
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Thu, 11 May 2017 23:38:30 +0000 (01:38 +0200)]
radv: stop using radv_amdgpu_winsys::family
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Thu, 11 May 2017 23:11:27 +0000 (01:11 +0200)]
radv: use ac_gpu_info
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Thu, 11 May 2017 22:56:06 +0000 (00:56 +0200)]
radv: remove radeon_info::name
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 21:01:00 +0000 (23:01 +0200)]
radv: use ac_surface data structures
This is mostly mechanical changes of renaming types and introducing
"legacy" everywhere.
It doesn't use the ac_surface computation functions yet.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 20:41:36 +0000 (22:41 +0200)]
radv: rename radeon_surf::bo_{size,alignment} to surf_{size,alignment}
To match radeonsi / ac_surface.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 20:33:13 +0000 (22:33 +0200)]
radv: remove unused RADEON_SURF_HAS_SBUFFER_MIPTREE
Reviewed-by: Dave Airlie <airlied@redhat.com>
Nicolai Hähnle [Wed, 10 May 2017 20:25:15 +0000 (22:25 +0200)]
radv: remove radeon_surf_level::nblk_z
We're not using thick tiling modes, so we can just derive the value
ourselves.
Reviewed-by: Dave Airlie <airlied@redhat.com>